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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +08002/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +08004 */
5
6#include <common.h>
7#include <asm/fsl_law.h>
8#include <asm/mmu.h>
9
10struct law_entry law_table[] = {
Tom Rini6a5dccc2022-11-16 13:10:41 -050011 SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
12#ifdef CFG_SYS_BMAN_MEM_PHYS
13 SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +080014#endif
Tom Rini6a5dccc2022-11-16 13:10:41 -050015#ifdef CFG_SYS_QMAN_MEM_PHYS
16 SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +080017#endif
Tom Rini6a5dccc2022-11-16 13:10:41 -050018#ifdef CFG_SYS_CPLD_BASE_PHYS
19 SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
Chunhe Lanc3eb88d2014-09-12 14:47:09 +080020#endif
Tom Rini6a5dccc2022-11-16 13:10:41 -050021#ifdef CFG_SYS_DCSRBAR_PHYS
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +080022 /* Limit DCSR to 32M to access NPC Trace Buffer */
Tom Rini6a5dccc2022-11-16 13:10:41 -050023 SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +080024#endif
Tom Rinib4213492022-11-12 17:36:51 -050025#ifdef CFG_SYS_NAND_BASE_PHYS
26 SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +080027#endif
28};
29
30int num_law_entries = ARRAY_SIZE(law_table);