blob: 268fb912b502d84f3345841f19325160d5a5fc67 [file] [log] [blame]
Tom Warren795f9d72013-01-23 14:01:01 -07001/*
2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/* Tegra SoC common clock control functions */
18
19#include <common.h>
20#include <asm/io.h>
21#include <asm/arch/clock.h>
22#include <asm/arch/tegra.h>
23#include <asm/arch-tegra/clk_rst.h>
24#include <asm/arch-tegra/timer.h>
25#include <div64.h>
26#include <fdtdec.h>
27
28/*
29 * This is our record of the current clock rate of each clock. We don't
30 * fill all of these in since we are only really interested in clocks which
31 * we use as parents.
32 */
33static unsigned pll_rate[CLOCK_ID_COUNT];
34
35/*
36 * The oscillator frequency is fixed to one of four set values. Based on this
37 * the other clocks are set up appropriately.
38 */
39static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
40 13000000,
41 19200000,
42 12000000,
43 26000000,
44};
45
46/* return 1 if a peripheral ID is in range */
47#define clock_type_id_isvalid(id) ((id) >= 0 && \
48 (id) < CLOCK_TYPE_COUNT)
49
50char pllp_valid = 1; /* PLLP is set up correctly */
51
52/* return 1 if a periphc_internal_id is in range */
53#define periphc_internal_id_isvalid(id) ((id) >= 0 && \
54 (id) < PERIPHC_COUNT)
55
56/* number of clock outputs of a PLL */
57static const u8 pll_num_clkouts[] = {
58 1, /* PLLC */
59 1, /* PLLM */
60 4, /* PLLP */
61 1, /* PLLA */
62 0, /* PLLU */
63 0, /* PLLD */
64};
65
66int clock_get_osc_bypass(void)
67{
68 struct clk_rst_ctlr *clkrst =
69 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
70 u32 reg;
71
72 reg = readl(&clkrst->crc_osc_ctrl);
73 return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT;
74}
75
76/* Returns a pointer to the registers of the given pll */
77static struct clk_pll *get_pll(enum clock_id clkid)
78{
79 struct clk_rst_ctlr *clkrst =
80 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
81
82 assert(clock_id_is_pll(clkid));
83 return &clkrst->crc_pll[clkid];
84}
85
86int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
87 u32 *divp, u32 *cpcon, u32 *lfcon)
88{
89 struct clk_pll *pll = get_pll(clkid);
90 u32 data;
91
92 assert(clkid != CLOCK_ID_USB);
93
94 /* Safety check, adds to code size but is small */
95 if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
96 return -1;
97 data = readl(&pll->pll_base);
98 *divm = (data & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
99 *divn = (data & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT;
100 *divp = (data & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
101 data = readl(&pll->pll_misc);
102 *cpcon = (data & PLL_CPCON_MASK) >> PLL_CPCON_SHIFT;
103 *lfcon = (data & PLL_LFCON_MASK) >> PLL_LFCON_SHIFT;
104
105 return 0;
106}
107
108unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
109 u32 divp, u32 cpcon, u32 lfcon)
110{
111 struct clk_pll *pll = get_pll(clkid);
112 u32 data;
113
114 /*
115 * We cheat by treating all PLL (except PLLU) in the same fashion.
116 * This works only because:
117 * - same fields are always mapped at same offsets, except DCCON
118 * - DCCON is always 0, doesn't conflict
119 * - M,N, P of PLLP values are ignored for PLLP
120 */
121 data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
122 writel(data, &pll->pll_misc);
123
124 data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
125 (0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
126
127 if (clkid == CLOCK_ID_USB)
128 data |= divp << PLLU_VCO_FREQ_SHIFT;
129 else
130 data |= divp << PLL_DIVP_SHIFT;
131 writel(data, &pll->pll_base);
132
133 /* calculate the stable time */
134 return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
135}
136
137void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
138 unsigned divisor)
139{
140 u32 *reg = get_periph_source_reg(periph_id);
141 u32 value;
142
143 value = readl(reg);
144
145 value &= ~OUT_CLK_SOURCE_MASK;
146 value |= source << OUT_CLK_SOURCE_SHIFT;
147
148 value &= ~OUT_CLK_DIVISOR_MASK;
149 value |= divisor << OUT_CLK_DIVISOR_SHIFT;
150
151 writel(value, reg);
152}
153
154void clock_ll_set_source(enum periph_id periph_id, unsigned source)
155{
156 u32 *reg = get_periph_source_reg(periph_id);
157
158 clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
159 source << OUT_CLK_SOURCE_SHIFT);
160}
161
162/**
163 * Given the parent's rate and the required rate for the children, this works
164 * out the peripheral clock divider to use, in 7.1 binary format.
165 *
166 * @param divider_bits number of divider bits (8 or 16)
167 * @param parent_rate clock rate of parent clock in Hz
168 * @param rate required clock rate for this clock
169 * @return divider which should be used
170 */
171static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
172 unsigned long rate)
173{
174 u64 divider = parent_rate * 2;
175 unsigned max_divider = 1 << divider_bits;
176
177 divider += rate - 1;
178 do_div(divider, rate);
179
180 if ((s64)divider - 2 < 0)
181 return 0;
182
183 if ((s64)divider - 2 >= max_divider)
184 return -1;
185
186 return divider - 2;
187}
188
189int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
190{
191 struct clk_pll *pll = get_pll(clkid);
192 int data = 0, div = 0, offset = 0;
193
194 if (!clock_id_is_pll(clkid))
195 return -1;
196
197 if (pllout + 1 > pll_num_clkouts[clkid])
198 return -1;
199
200 div = clk_get_divider(8, pll_rate[clkid], rate);
201
202 if (div < 0)
203 return -1;
204
205 /* out2 and out4 are in the high part of the register */
206 if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
207 offset = 16;
208
209 data = (div << PLL_OUT_RATIO_SHIFT) |
210 PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
211 clrsetbits_le32(&pll->pll_out[pllout >> 1],
212 PLL_OUT_RATIO_MASK << offset, data << offset);
213
214 return 0;
215}
216
217/**
218 * Given the parent's rate and the divider in 7.1 format, this works out the
219 * resulting peripheral clock rate.
220 *
221 * @param parent_rate clock rate of parent clock in Hz
222 * @param divider which should be used in 7.1 format
223 * @return effective clock rate of peripheral
224 */
225static unsigned long get_rate_from_divider(unsigned long parent_rate,
226 int divider)
227{
228 u64 rate;
229
230 rate = (u64)parent_rate * 2;
231 do_div(rate, divider + 2);
232 return rate;
233}
234
235unsigned long clock_get_periph_rate(enum periph_id periph_id,
236 enum clock_id parent)
237{
238 u32 *reg = get_periph_source_reg(periph_id);
239
240 return get_rate_from_divider(pll_rate[parent],
241 (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
242}
243
244/**
245 * Find the best available 7.1 format divisor given a parent clock rate and
246 * required child clock rate. This function assumes that a second-stage
247 * divisor is available which can divide by powers of 2 from 1 to 256.
248 *
249 * @param divider_bits number of divider bits (8 or 16)
250 * @param parent_rate clock rate of parent clock in Hz
251 * @param rate required clock rate for this clock
252 * @param extra_div value for the second-stage divisor (not set if this
253 * function returns -1.
254 * @return divider which should be used, or -1 if nothing is valid
255 *
256 */
257static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
258 unsigned long rate, int *extra_div)
259{
260 int shift;
261 int best_divider = -1;
262 int best_error = rate;
263
264 /* try dividers from 1 to 256 and find closest match */
265 for (shift = 0; shift <= 8 && best_error > 0; shift++) {
266 unsigned divided_parent = parent_rate >> shift;
267 int divider = clk_get_divider(divider_bits, divided_parent,
268 rate);
269 unsigned effective_rate = get_rate_from_divider(divided_parent,
270 divider);
271 int error = rate - effective_rate;
272
273 /* Given a valid divider, look for the lowest error */
274 if (divider != -1 && error < best_error) {
275 best_error = error;
276 *extra_div = 1 << shift;
277 best_divider = divider;
278 }
279 }
280
281 /* return what we found - *extra_div will already be set */
282 return best_divider;
283}
284
285/**
286 * Adjust peripheral PLL to use the given divider and source.
287 *
288 * @param periph_id peripheral to adjust
289 * @param source Source number (0-3 or 0-7)
290 * @param mux_bits Number of mux bits (2 or 4)
291 * @param divider Required divider in 7.1 or 15.1 format
292 * @return 0 if ok, -1 on error (requesting a parent clock which is not valid
293 * for this peripheral)
294 */
295static int adjust_periph_pll(enum periph_id periph_id, int source,
296 int mux_bits, unsigned divider)
297{
298 u32 *reg = get_periph_source_reg(periph_id);
299
300 clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
301 divider << OUT_CLK_DIVISOR_SHIFT);
302 udelay(1);
303
304 /* work out the source clock and set it */
305 if (source < 0)
306 return -1;
307 if (mux_bits == 4) {
308 clrsetbits_le32(reg, OUT_CLK_SOURCE4_MASK,
309 source << OUT_CLK_SOURCE4_SHIFT);
310 } else {
311 clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
312 source << OUT_CLK_SOURCE_SHIFT);
313 }
314 udelay(2);
315 return 0;
316}
317
318unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
319 enum clock_id parent, unsigned rate, int *extra_div)
320{
321 unsigned effective_rate;
322 int mux_bits, divider_bits, source;
323 int divider;
Allen Martin810a4e42013-05-10 16:56:55 +0000324 int xdiv = 0;
Tom Warren795f9d72013-01-23 14:01:01 -0700325
326 /* work out the source clock and set it */
327 source = get_periph_clock_source(periph_id, parent, &mux_bits,
328 &divider_bits);
329
Allen Martin810a4e42013-05-10 16:56:55 +0000330 divider = find_best_divider(divider_bits, pll_rate[parent],
331 rate, &xdiv);
Tom Warren795f9d72013-01-23 14:01:01 -0700332 if (extra_div)
Allen Martin810a4e42013-05-10 16:56:55 +0000333 *extra_div = xdiv;
334
Tom Warren795f9d72013-01-23 14:01:01 -0700335 assert(divider >= 0);
336 if (adjust_periph_pll(periph_id, source, mux_bits, divider))
337 return -1U;
338 debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
339 get_periph_source_reg(periph_id),
340 readl(get_periph_source_reg(periph_id)));
341
342 /* Check what we ended up with. This shouldn't matter though */
343 effective_rate = clock_get_periph_rate(periph_id, parent);
344 if (extra_div)
345 effective_rate /= *extra_div;
346 if (rate != effective_rate)
347 debug("Requested clock rate %u not honored (got %u)\n",
348 rate, effective_rate);
349 return effective_rate;
350}
351
352unsigned clock_start_periph_pll(enum periph_id periph_id,
353 enum clock_id parent, unsigned rate)
354{
355 unsigned effective_rate;
356
357 reset_set_enable(periph_id, 1);
358 clock_enable(periph_id);
359
360 effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
361 NULL);
362
363 reset_set_enable(periph_id, 0);
364 return effective_rate;
365}
366
367void clock_enable(enum periph_id clkid)
368{
369 clock_set_enable(clkid, 1);
370}
371
372void clock_disable(enum periph_id clkid)
373{
374 clock_set_enable(clkid, 0);
375}
376
377void reset_periph(enum periph_id periph_id, int us_delay)
378{
379 /* Put peripheral into reset */
380 reset_set_enable(periph_id, 1);
381 udelay(us_delay);
382
383 /* Remove reset */
384 reset_set_enable(periph_id, 0);
385
386 udelay(us_delay);
387}
388
389void reset_cmplx_set_enable(int cpu, int which, int reset)
390{
391 struct clk_rst_ctlr *clkrst =
392 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
393 u32 mask;
394
395 /* Form the mask, which depends on the cpu chosen (2 or 4) */
396 assert(cpu >= 0 && cpu < MAX_NUM_CPU);
397 mask = which << cpu;
398
399 /* either enable or disable those reset for that CPU */
400 if (reset)
401 writel(mask, &clkrst->crc_cpu_cmplx_set);
402 else
403 writel(mask, &clkrst->crc_cpu_cmplx_clr);
404}
405
406unsigned clock_get_rate(enum clock_id clkid)
407{
408 struct clk_pll *pll;
409 u32 base;
410 u32 divm;
411 u64 parent_rate;
412 u64 rate;
413
414 parent_rate = osc_freq[clock_get_osc_freq()];
415 if (clkid == CLOCK_ID_OSC)
416 return parent_rate;
417
418 pll = get_pll(clkid);
419 base = readl(&pll->pll_base);
420
421 /* Oh for bf_unpack()... */
422 rate = parent_rate * ((base & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT);
423 divm = (base & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
424 if (clkid == CLOCK_ID_USB)
425 divm <<= (base & PLLU_VCO_FREQ_MASK) >> PLLU_VCO_FREQ_SHIFT;
426 else
427 divm <<= (base & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
428 do_div(rate, divm);
429 return rate;
430}
431
432/**
433 * Set the output frequency you want for each PLL clock.
434 * PLL output frequencies are programmed by setting their N, M and P values.
435 * The governing equations are:
436 * VCO = (Fi / m) * n, Fo = VCO / (2^p)
437 * where Fo is the output frequency from the PLL.
438 * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
439 * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
440 * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
441 *
442 * @param n PLL feedback divider(DIVN)
443 * @param m PLL input divider(DIVN)
444 * @param p post divider(DIVP)
445 * @param cpcon base PLL charge pump(CPCON)
446 * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
447 * be overriden), 1 if PLL is already correct
448 */
449int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
450{
451 u32 base_reg;
452 u32 misc_reg;
453 struct clk_pll *pll;
454
455 pll = get_pll(clkid);
456
457 base_reg = readl(&pll->pll_base);
458
459 /* Set BYPASS, m, n and p to PLL_BASE */
460 base_reg &= ~PLL_DIVM_MASK;
461 base_reg |= m << PLL_DIVM_SHIFT;
462
463 base_reg &= ~PLL_DIVN_MASK;
464 base_reg |= n << PLL_DIVN_SHIFT;
465
466 base_reg &= ~PLL_DIVP_MASK;
467 base_reg |= p << PLL_DIVP_SHIFT;
468
469 if (clkid == CLOCK_ID_PERIPH) {
470 /*
471 * If the PLL is already set up, check that it is correct
472 * and record this info for clock_verify() to check.
473 */
474 if (base_reg & PLL_BASE_OVRRIDE_MASK) {
475 base_reg |= PLL_ENABLE_MASK;
476 if (base_reg != readl(&pll->pll_base))
477 pllp_valid = 0;
478 return pllp_valid ? 1 : -1;
479 }
480 base_reg |= PLL_BASE_OVRRIDE_MASK;
481 }
482
483 base_reg |= PLL_BYPASS_MASK;
484 writel(base_reg, &pll->pll_base);
485
486 /* Set cpcon to PLL_MISC */
487 misc_reg = readl(&pll->pll_misc);
488 misc_reg &= ~PLL_CPCON_MASK;
489 misc_reg |= cpcon << PLL_CPCON_SHIFT;
490 writel(misc_reg, &pll->pll_misc);
491
492 /* Enable PLL */
493 base_reg |= PLL_ENABLE_MASK;
494 writel(base_reg, &pll->pll_base);
495
496 /* Disable BYPASS */
497 base_reg &= ~PLL_BYPASS_MASK;
498 writel(base_reg, &pll->pll_base);
499
500 return 0;
501}
502
503void clock_ll_start_uart(enum periph_id periph_id)
504{
505 /* Assert UART reset and enable clock */
506 reset_set_enable(periph_id, 1);
507 clock_enable(periph_id);
508 clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
509
510 /* wait for 2us */
511 udelay(2);
512
513 /* De-assert reset to UART */
514 reset_set_enable(periph_id, 0);
515}
516
517#ifdef CONFIG_OF_CONTROL
518int clock_decode_periph_id(const void *blob, int node)
519{
520 enum periph_id id;
521 u32 cell[2];
522 int err;
523
524 err = fdtdec_get_int_array(blob, node, "clocks", cell,
525 ARRAY_SIZE(cell));
526 if (err)
527 return -1;
528 id = clk_id_to_periph_id(cell[1]);
529 assert(clock_periph_id_isvalid(id));
530 return id;
531}
532#endif /* CONFIG_OF_CONTROL */
533
534int clock_verify(void)
535{
536 struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
537 u32 reg = readl(&pll->pll_base);
538
539 if (!pllp_valid) {
540 printf("Warning: PLLP %x is not correct\n", reg);
541 return -1;
542 }
543 debug("PLLP %x is correct\n", reg);
544 return 0;
545}
546
547void clock_init(void)
548{
549 pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
550 pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
551 pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
552 pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
553 pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
554 pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
555 debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
556 debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
557 debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
558 debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
559 debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
Tom Warrenfbef3552013-04-01 15:48:54 -0700560
561 /* Do any special system timer/TSC setup */
562 arch_timer_init();
Tom Warren795f9d72013-01-23 14:01:01 -0700563}