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git01.mediatek.com / filogic / uboot / 5a0baf4ce36e74735b5fd1426a1cc690f27922d5 / . / arch / arm / dts / r8a774b1.dtsi
blob: 23119c0ae7b4ff796ac2a73e2e342764c89fd181 [file] [log] [blame]
Biju Das25e0b962020-09-16 09:05:07 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774b1 SoC
4 *
5 * Copyright (C) 2020 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/clock/r8a774b1-cpg-mssr.h>
11#include <dt-bindings/power/r8a774b1-sysc.h>
12
13#define CPG_AUDIO_CLK_I R8A774B1_CLK_S0D4
14
15/ {
16 compatible = "renesas,r8a774b1";
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 /*
21 * The external audio clocks are configured as 0 Hz fixed frequency
22 * clocks by default.
23 * Boards that provide audio clocks should override them.
24 */
25 audio_clk_a: audio_clk_a {
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <0>;
29 };
30
31 audio_clk_b: audio_clk_b {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <0>;
35 };
36
37 audio_clk_c: audio_clk_c {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <0>;
41 };
42
43 /* External CAN clock - to be overridden by boards that provide it */
44 can_clk: can {
45 compatible = "fixed-clock";
46 #clock-cells = <0>;
47 clock-frequency = <0>;
48 };
49
50 cluster0_opp: opp_table0 {
51 compatible = "operating-points-v2";
52 opp-shared;
53
54 opp-500000000 {
55 opp-hz = /bits/ 64 <500000000>;
56 opp-microvolt = <830000>;
57 clock-latency-ns = <300000>;
58 };
59 opp-1000000000 {
60 opp-hz = /bits/ 64 <1000000000>;
61 opp-microvolt = <830000>;
62 clock-latency-ns = <300000>;
63 };
64 opp-1500000000 {
65 opp-hz = /bits/ 64 <1500000000>;
66 opp-microvolt = <830000>;
67 clock-latency-ns = <300000>;
68 opp-suspend;
69 };
70 };
71
72 cpus {
73 #address-cells = <1>;
74 #size-cells = <0>;
75
76 a57_0: cpu@0 {
77 compatible = "arm,cortex-a57";
78 reg = <0x0>;
79 device_type = "cpu";
80 power-domains = <&sysc R8A774B1_PD_CA57_CPU0>;
81 next-level-cache = <&L2_CA57>;
82 enable-method = "psci";
83 #cooling-cells = <2>;
84 dynamic-power-coefficient = <854>;
85 clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
86 operating-points-v2 = <&cluster0_opp>;
87 };
88
89 a57_1: cpu@1 {
90 compatible = "arm,cortex-a57";
91 reg = <0x1>;
92 device_type = "cpu";
93 power-domains = <&sysc R8A774B1_PD_CA57_CPU1>;
94 next-level-cache = <&L2_CA57>;
95 enable-method = "psci";
96 clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
97 operating-points-v2 = <&cluster0_opp>;
98 };
99
100 L2_CA57: cache-controller-0 {
101 compatible = "cache";
102 power-domains = <&sysc R8A774B1_PD_CA57_SCU>;
103 cache-unified;
104 cache-level = <2>;
105 };
106 };
107
108 extal_clk: extal {
109 compatible = "fixed-clock";
110 #clock-cells = <0>;
111 /* This value must be overridden by the board */
112 clock-frequency = <0>;
113 };
114
115 extalr_clk: extalr {
116 compatible = "fixed-clock";
117 #clock-cells = <0>;
118 /* This value must be overridden by the board */
119 clock-frequency = <0>;
120 };
121
122 /* External PCIe clock - can be overridden by the board */
123 pcie_bus_clk: pcie_bus {
124 compatible = "fixed-clock";
125 #clock-cells = <0>;
126 clock-frequency = <0>;
127 };
128
129 pmu_a57 {
130 compatible = "arm,cortex-a57-pmu";
131 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
132 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
133 interrupt-affinity = <&a57_0>, <&a57_1>;
134 };
135
136 psci {
137 compatible = "arm,psci-1.0", "arm,psci-0.2";
138 method = "smc";
139 };
140
141 /* External SCIF clock - to be overridden by boards that provide it */
142 scif_clk: scif {
143 compatible = "fixed-clock";
144 #clock-cells = <0>;
145 clock-frequency = <0>;
146 };
147
148 soc {
149 compatible = "simple-bus";
150 interrupt-parent = <&gic>;
151 #address-cells = <2>;
152 #size-cells = <2>;
153 ranges;
154
155 rwdt: watchdog@e6020000 {
156 compatible = "renesas,r8a774b1-wdt",
157 "renesas,rcar-gen3-wdt";
158 reg = <0 0xe6020000 0 0x0c>;
159 clocks = <&cpg CPG_MOD 402>;
160 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
161 resets = <&cpg 402>;
162 status = "disabled";
163 };
164
165 gpio0: gpio@e6050000 {
166 compatible = "renesas,gpio-r8a774b1",
167 "renesas,rcar-gen3-gpio";
168 reg = <0 0xe6050000 0 0x50>;
169 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
170 #gpio-cells = <2>;
171 gpio-controller;
172 gpio-ranges = <&pfc 0 0 16>;
173 #interrupt-cells = <2>;
174 interrupt-controller;
175 clocks = <&cpg CPG_MOD 912>;
176 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
177 resets = <&cpg 912>;
178 };
179
180 gpio1: gpio@e6051000 {
181 compatible = "renesas,gpio-r8a774b1",
182 "renesas,rcar-gen3-gpio";
183 reg = <0 0xe6051000 0 0x50>;
184 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
185 #gpio-cells = <2>;
186 gpio-controller;
187 gpio-ranges = <&pfc 0 32 29>;
188 #interrupt-cells = <2>;
189 interrupt-controller;
190 clocks = <&cpg CPG_MOD 911>;
191 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
192 resets = <&cpg 911>;
193 };
194
195 gpio2: gpio@e6052000 {
196 compatible = "renesas,gpio-r8a774b1",
197 "renesas,rcar-gen3-gpio";
198 reg = <0 0xe6052000 0 0x50>;
199 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
200 #gpio-cells = <2>;
201 gpio-controller;
202 gpio-ranges = <&pfc 0 64 15>;
203 #interrupt-cells = <2>;
204 interrupt-controller;
205 clocks = <&cpg CPG_MOD 910>;
206 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
207 resets = <&cpg 910>;
208 };
209
210 gpio3: gpio@e6053000 {
211 compatible = "renesas,gpio-r8a774b1",
212 "renesas,rcar-gen3-gpio";
213 reg = <0 0xe6053000 0 0x50>;
214 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
215 #gpio-cells = <2>;
216 gpio-controller;
217 gpio-ranges = <&pfc 0 96 16>;
218 #interrupt-cells = <2>;
219 interrupt-controller;
220 clocks = <&cpg CPG_MOD 909>;
221 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
222 resets = <&cpg 909>;
223 };
224
225 gpio4: gpio@e6054000 {
226 compatible = "renesas,gpio-r8a774b1",
227 "renesas,rcar-gen3-gpio";
228 reg = <0 0xe6054000 0 0x50>;
229 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
230 #gpio-cells = <2>;
231 gpio-controller;
232 gpio-ranges = <&pfc 0 128 18>;
233 #interrupt-cells = <2>;
234 interrupt-controller;
235 clocks = <&cpg CPG_MOD 908>;
236 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
237 resets = <&cpg 908>;
238 };
239
240 gpio5: gpio@e6055000 {
241 compatible = "renesas,gpio-r8a774b1",
242 "renesas,rcar-gen3-gpio";
243 reg = <0 0xe6055000 0 0x50>;
244 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
245 #gpio-cells = <2>;
246 gpio-controller;
247 gpio-ranges = <&pfc 0 160 26>;
248 #interrupt-cells = <2>;
249 interrupt-controller;
250 clocks = <&cpg CPG_MOD 907>;
251 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
252 resets = <&cpg 907>;
253 };
254
255 gpio6: gpio@e6055400 {
256 compatible = "renesas,gpio-r8a774b1",
257 "renesas,rcar-gen3-gpio";
258 reg = <0 0xe6055400 0 0x50>;
259 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
260 #gpio-cells = <2>;
261 gpio-controller;
262 gpio-ranges = <&pfc 0 192 32>;
263 #interrupt-cells = <2>;
264 interrupt-controller;
265 clocks = <&cpg CPG_MOD 906>;
266 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
267 resets = <&cpg 906>;
268 };
269
270 gpio7: gpio@e6055800 {
271 compatible = "renesas,gpio-r8a774b1",
272 "renesas,rcar-gen3-gpio";
273 reg = <0 0xe6055800 0 0x50>;
274 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
275 #gpio-cells = <2>;
276 gpio-controller;
277 gpio-ranges = <&pfc 0 224 4>;
278 #interrupt-cells = <2>;
279 interrupt-controller;
280 clocks = <&cpg CPG_MOD 905>;
281 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
282 resets = <&cpg 905>;
283 };
284
285 pfc: pin-controller@e6060000 {
286 compatible = "renesas,pfc-r8a774b1";
287 reg = <0 0xe6060000 0 0x50c>;
288 };
289
290 cmt0: timer@e60f0000 {
291 compatible = "renesas,r8a774b1-cmt0",
292 "renesas,rcar-gen3-cmt0";
293 reg = <0 0xe60f0000 0 0x1004>;
294 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&cpg CPG_MOD 303>;
297 clock-names = "fck";
298 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
299 resets = <&cpg 303>;
300 status = "disabled";
301 };
302
303 cmt1: timer@e6130000 {
304 compatible = "renesas,r8a774b1-cmt1",
305 "renesas,rcar-gen3-cmt1";
306 reg = <0 0xe6130000 0 0x1004>;
307 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&cpg CPG_MOD 302>;
316 clock-names = "fck";
317 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
318 resets = <&cpg 302>;
319 status = "disabled";
320 };
321
322 cmt2: timer@e6140000 {
323 compatible = "renesas,r8a774b1-cmt1",
324 "renesas,rcar-gen3-cmt1";
325 reg = <0 0xe6140000 0 0x1004>;
326 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&cpg CPG_MOD 301>;
335 clock-names = "fck";
336 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
337 resets = <&cpg 301>;
338 status = "disabled";
339 };
340
341 cmt3: timer@e6148000 {
342 compatible = "renesas,r8a774b1-cmt1",
343 "renesas,rcar-gen3-cmt1";
344 reg = <0 0xe6148000 0 0x1004>;
345 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
347 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
350 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&cpg CPG_MOD 300>;
354 clock-names = "fck";
355 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
356 resets = <&cpg 300>;
357 status = "disabled";
358 };
359
360 cpg: clock-controller@e6150000 {
361 compatible = "renesas,r8a774b1-cpg-mssr";
362 reg = <0 0xe6150000 0 0x1000>;
363 clocks = <&extal_clk>, <&extalr_clk>;
364 clock-names = "extal", "extalr";
365 #clock-cells = <2>;
366 #power-domain-cells = <0>;
367 #reset-cells = <1>;
368 };
369
370 rst: reset-controller@e6160000 {
371 compatible = "renesas,r8a774b1-rst";
372 reg = <0 0xe6160000 0 0x0200>;
373 };
374
375 sysc: system-controller@e6180000 {
376 compatible = "renesas,r8a774b1-sysc";
377 reg = <0 0xe6180000 0 0x0400>;
378 #power-domain-cells = <1>;
379 };
380
381 tsc: thermal@e6198000 {
382 compatible = "renesas,r8a774b1-thermal";
383 reg = <0 0xe6198000 0 0x100>,
384 <0 0xe61a0000 0 0x100>,
385 <0 0xe61a8000 0 0x100>;
386 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
387 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
388 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
389 clocks = <&cpg CPG_MOD 522>;
390 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
391 resets = <&cpg 522>;
392 #thermal-sensor-cells = <1>;
393 };
394
395 intc_ex: interrupt-controller@e61c0000 {
396 compatible = "renesas,intc-ex-r8a774b1", "renesas,irqc";
397 #interrupt-cells = <2>;
398 interrupt-controller;
399 reg = <0 0xe61c0000 0 0x200>;
400 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&cpg CPG_MOD 407>;
407 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
408 resets = <&cpg 407>;
409 };
410
411 tmu0: timer@e61e0000 {
412 compatible = "renesas,tmu-r8a774b1", "renesas,tmu";
413 reg = <0 0xe61e0000 0 0x30>;
414 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&cpg CPG_MOD 125>;
418 clock-names = "fck";
419 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
420 resets = <&cpg 125>;
421 status = "disabled";
422 };
423
424 tmu1: timer@e6fc0000 {
425 compatible = "renesas,tmu-r8a774b1", "renesas,tmu";
426 reg = <0 0xe6fc0000 0 0x30>;
427 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
429 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&cpg CPG_MOD 124>;
431 clock-names = "fck";
432 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
433 resets = <&cpg 124>;
434 status = "disabled";
435 };
436
437 tmu2: timer@e6fd0000 {
438 compatible = "renesas,tmu-r8a774b1", "renesas,tmu";
439 reg = <0 0xe6fd0000 0 0x30>;
440 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
441 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&cpg CPG_MOD 123>;
444 clock-names = "fck";
445 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
446 resets = <&cpg 123>;
447 status = "disabled";
448 };
449
450 tmu3: timer@e6fe0000 {
451 compatible = "renesas,tmu-r8a774b1", "renesas,tmu";
452 reg = <0 0xe6fe0000 0 0x30>;
453 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
454 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
455 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&cpg CPG_MOD 122>;
457 clock-names = "fck";
458 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
459 resets = <&cpg 122>;
460 status = "disabled";
461 };
462
463 tmu4: timer@ffc00000 {
464 compatible = "renesas,tmu-r8a774b1", "renesas,tmu";
465 reg = <0 0xffc00000 0 0x30>;
466 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
467 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&cpg CPG_MOD 121>;
470 clock-names = "fck";
471 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
472 resets = <&cpg 121>;
473 status = "disabled";
474 };
475
476 i2c0: i2c@e6500000 {
477 #address-cells = <1>;
478 #size-cells = <0>;
479 compatible = "renesas,i2c-r8a774b1",
480 "renesas,rcar-gen3-i2c";
481 reg = <0 0xe6500000 0 0x40>;
482 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
483 clocks = <&cpg CPG_MOD 931>;
484 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
485 resets = <&cpg 931>;
486 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
487 <&dmac2 0x91>, <&dmac2 0x90>;
488 dma-names = "tx", "rx", "tx", "rx";
489 i2c-scl-internal-delay-ns = <110>;
490 status = "disabled";
491 };
492
493 i2c1: i2c@e6508000 {
494 #address-cells = <1>;
495 #size-cells = <0>;
496 compatible = "renesas,i2c-r8a774b1",
497 "renesas,rcar-gen3-i2c";
498 reg = <0 0xe6508000 0 0x40>;
499 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
500 clocks = <&cpg CPG_MOD 930>;
501 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
502 resets = <&cpg 930>;
503 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
504 <&dmac2 0x93>, <&dmac2 0x92>;
505 dma-names = "tx", "rx", "tx", "rx";
506 i2c-scl-internal-delay-ns = <6>;
507 status = "disabled";
508 };
509
510 i2c2: i2c@e6510000 {
511 #address-cells = <1>;
512 #size-cells = <0>;
513 compatible = "renesas,i2c-r8a774b1",
514 "renesas,rcar-gen3-i2c";
515 reg = <0 0xe6510000 0 0x40>;
516 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&cpg CPG_MOD 929>;
518 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
519 resets = <&cpg 929>;
520 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
521 <&dmac2 0x95>, <&dmac2 0x94>;
522 dma-names = "tx", "rx", "tx", "rx";
523 i2c-scl-internal-delay-ns = <6>;
524 status = "disabled";
525 };
526
527 i2c3: i2c@e66d0000 {
528 #address-cells = <1>;
529 #size-cells = <0>;
530 compatible = "renesas,i2c-r8a774b1",
531 "renesas,rcar-gen3-i2c";
532 reg = <0 0xe66d0000 0 0x40>;
533 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&cpg CPG_MOD 928>;
535 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
536 resets = <&cpg 928>;
537 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
538 dma-names = "tx", "rx";
539 i2c-scl-internal-delay-ns = <110>;
540 status = "disabled";
541 };
542
543 i2c4: i2c@e66d8000 {
544 #address-cells = <1>;
545 #size-cells = <0>;
546 compatible = "renesas,i2c-r8a774b1",
547 "renesas,rcar-gen3-i2c";
548 reg = <0 0xe66d8000 0 0x40>;
549 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
550 clocks = <&cpg CPG_MOD 927>;
551 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
552 resets = <&cpg 927>;
553 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
554 dma-names = "tx", "rx";
555 i2c-scl-internal-delay-ns = <110>;
556 status = "disabled";
557 };
558
559 i2c5: i2c@e66e0000 {
560 #address-cells = <1>;
561 #size-cells = <0>;
562 compatible = "renesas,i2c-r8a774b1",
563 "renesas,rcar-gen3-i2c";
564 reg = <0 0xe66e0000 0 0x40>;
565 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&cpg CPG_MOD 919>;
567 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
568 resets = <&cpg 919>;
569 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
570 dma-names = "tx", "rx";
571 i2c-scl-internal-delay-ns = <110>;
572 status = "disabled";
573 };
574
575 i2c6: i2c@e66e8000 {
576 #address-cells = <1>;
577 #size-cells = <0>;
578 compatible = "renesas,i2c-r8a774b1",
579 "renesas,rcar-gen3-i2c";
580 reg = <0 0xe66e8000 0 0x40>;
581 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
582 clocks = <&cpg CPG_MOD 918>;
583 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
584 resets = <&cpg 918>;
585 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
586 dma-names = "tx", "rx";
587 i2c-scl-internal-delay-ns = <6>;
588 status = "disabled";
589 };
590
591 i2c_dvfs: i2c@e60b0000 {
592 #address-cells = <1>;
593 #size-cells = <0>;
594 compatible = "renesas,iic-r8a774b1",
595 "renesas,rcar-gen3-iic",
596 "renesas,rmobile-iic";
597 reg = <0 0xe60b0000 0 0x425>;
598 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&cpg CPG_MOD 926>;
600 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
601 resets = <&cpg 926>;
602 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
603 dma-names = "tx", "rx";
604 status = "disabled";
605 };
606
607 hscif0: serial@e6540000 {
608 compatible = "renesas,hscif-r8a774b1",
609 "renesas,rcar-gen3-hscif",
610 "renesas,hscif";
611 reg = <0 0xe6540000 0 0x60>;
612 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&cpg CPG_MOD 520>,
614 <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
615 <&scif_clk>;
616 clock-names = "fck", "brg_int", "scif_clk";
617 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
618 <&dmac2 0x31>, <&dmac2 0x30>;
619 dma-names = "tx", "rx", "tx", "rx";
620 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
621 resets = <&cpg 520>;
622 status = "disabled";
623 };
624
625 hscif1: serial@e6550000 {
626 compatible = "renesas,hscif-r8a774b1",
627 "renesas,rcar-gen3-hscif",
628 "renesas,hscif";
629 reg = <0 0xe6550000 0 0x60>;
630 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&cpg CPG_MOD 519>,
632 <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
633 <&scif_clk>;
634 clock-names = "fck", "brg_int", "scif_clk";
635 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
636 <&dmac2 0x33>, <&dmac2 0x32>;
637 dma-names = "tx", "rx", "tx", "rx";
638 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
639 resets = <&cpg 519>;
640 status = "disabled";
641 };
642
643 hscif2: serial@e6560000 {
644 compatible = "renesas,hscif-r8a774b1",
645 "renesas,rcar-gen3-hscif",
646 "renesas,hscif";
647 reg = <0 0xe6560000 0 0x60>;
648 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&cpg CPG_MOD 518>,
650 <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
651 <&scif_clk>;
652 clock-names = "fck", "brg_int", "scif_clk";
653 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
654 <&dmac2 0x35>, <&dmac2 0x34>;
655 dma-names = "tx", "rx", "tx", "rx";
656 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
657 resets = <&cpg 518>;
658 status = "disabled";
659 };
660
661 hscif3: serial@e66a0000 {
662 compatible = "renesas,hscif-r8a774b1",
663 "renesas,rcar-gen3-hscif",
664 "renesas,hscif";
665 reg = <0 0xe66a0000 0 0x60>;
666 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
667 clocks = <&cpg CPG_MOD 517>,
668 <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
669 <&scif_clk>;
670 clock-names = "fck", "brg_int", "scif_clk";
671 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
672 dma-names = "tx", "rx";
673 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
674 resets = <&cpg 517>;
675 status = "disabled";
676 };
677
678 hscif4: serial@e66b0000 {
679 compatible = "renesas,hscif-r8a774b1",
680 "renesas,rcar-gen3-hscif",
681 "renesas,hscif";
682 reg = <0 0xe66b0000 0 0x60>;
683 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
684 clocks = <&cpg CPG_MOD 516>,
685 <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
686 <&scif_clk>;
687 clock-names = "fck", "brg_int", "scif_clk";
688 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
689 dma-names = "tx", "rx";
690 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
691 resets = <&cpg 516>;
692 status = "disabled";
693 };
694
695 hsusb: usb@e6590000 {
696 compatible = "renesas,usbhs-r8a774b1",
697 "renesas,rcar-gen3-usbhs";
698 reg = <0 0xe6590000 0 0x200>;
699 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
700 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
701 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
702 <&usb_dmac1 0>, <&usb_dmac1 1>;
703 dma-names = "ch0", "ch1", "ch2", "ch3";
704 renesas,buswait = <11>;
705 phys = <&usb2_phy0 3>;
706 phy-names = "usb";
707 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
708 resets = <&cpg 704>, <&cpg 703>;
709 status = "disabled";
710 };
711
712 usb_dmac0: dma-controller@e65a0000 {
713 compatible = "renesas,r8a774b1-usb-dmac",
714 "renesas,usb-dmac";
715 reg = <0 0xe65a0000 0 0x100>;
716 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
717 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
718 interrupt-names = "ch0", "ch1";
719 clocks = <&cpg CPG_MOD 330>;
720 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
721 resets = <&cpg 330>;
722 #dma-cells = <1>;
723 dma-channels = <2>;
724 };
725
726 usb_dmac1: dma-controller@e65b0000 {
727 compatible = "renesas,r8a774b1-usb-dmac",
728 "renesas,usb-dmac";
729 reg = <0 0xe65b0000 0 0x100>;
730 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
731 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
732 interrupt-names = "ch0", "ch1";
733 clocks = <&cpg CPG_MOD 331>;
734 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
735 resets = <&cpg 331>;
736 #dma-cells = <1>;
737 dma-channels = <2>;
738 };
739
740 usb3_phy0: usb-phy@e65ee000 {
741 compatible = "renesas,r8a774b1-usb3-phy",
742 "renesas,rcar-gen3-usb3-phy";
743 reg = <0 0xe65ee000 0 0x90>;
744 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
745 <&usb_extal_clk>;
746 clock-names = "usb3-if", "usb3s_clk", "usb_extal";
747 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
748 resets = <&cpg 328>;
749 #phy-cells = <0>;
750 status = "disabled";
751 };
752
753 dmac0: dma-controller@e6700000 {
754 compatible = "renesas,dmac-r8a774b1",
755 "renesas,rcar-dmac";
756 reg = <0 0xe6700000 0 0x10000>;
757 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
758 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
759 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
760 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
761 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
762 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
763 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
764 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
765 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
766 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
767 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
768 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
769 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
770 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
771 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
772 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
773 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
774 interrupt-names = "error",
775 "ch0", "ch1", "ch2", "ch3",
776 "ch4", "ch5", "ch6", "ch7",
777 "ch8", "ch9", "ch10", "ch11",
778 "ch12", "ch13", "ch14", "ch15";
779 clocks = <&cpg CPG_MOD 219>;
780 clock-names = "fck";
781 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
782 resets = <&cpg 219>;
783 #dma-cells = <1>;
784 dma-channels = <16>;
785 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
786 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
787 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
788 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
789 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
790 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
791 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
792 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
793 };
794
795 dmac1: dma-controller@e7300000 {
796 compatible = "renesas,dmac-r8a774b1",
797 "renesas,rcar-dmac";
798 reg = <0 0xe7300000 0 0x10000>;
799 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
800 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
801 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
802 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
803 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
804 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
805 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
806 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
807 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
808 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
809 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
810 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
811 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
812 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
813 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
814 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
815 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
816 interrupt-names = "error",
817 "ch0", "ch1", "ch2", "ch3",
818 "ch4", "ch5", "ch6", "ch7",
819 "ch8", "ch9", "ch10", "ch11",
820 "ch12", "ch13", "ch14", "ch15";
821 clocks = <&cpg CPG_MOD 218>;
822 clock-names = "fck";
823 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
824 resets = <&cpg 218>;
825 #dma-cells = <1>;
826 dma-channels = <16>;
827 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
828 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
829 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
830 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
831 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
832 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
833 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
834 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
835 };
836
837 dmac2: dma-controller@e7310000 {
838 compatible = "renesas,dmac-r8a774b1",
839 "renesas,rcar-dmac";
840 reg = <0 0xe7310000 0 0x10000>;
841 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
842 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
843 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
844 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
845 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
846 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
847 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
848 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
849 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
850 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
851 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
852 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
853 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
854 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
855 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
856 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
857 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
858 interrupt-names = "error",
859 "ch0", "ch1", "ch2", "ch3",
860 "ch4", "ch5", "ch6", "ch7",
861 "ch8", "ch9", "ch10", "ch11",
862 "ch12", "ch13", "ch14", "ch15";
863 clocks = <&cpg CPG_MOD 217>;
864 clock-names = "fck";
865 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
866 resets = <&cpg 217>;
867 #dma-cells = <1>;
868 dma-channels = <16>;
869 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
870 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
871 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
872 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
873 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
874 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
875 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
876 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
877 };
878
879 ipmmu_ds0: iommu@e6740000 {
880 compatible = "renesas,ipmmu-r8a774b1";
881 reg = <0 0xe6740000 0 0x1000>;
882 renesas,ipmmu-main = <&ipmmu_mm 0>;
883 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
884 #iommu-cells = <1>;
885 };
886
887 ipmmu_ds1: iommu@e7740000 {
888 compatible = "renesas,ipmmu-r8a774b1";
889 reg = <0 0xe7740000 0 0x1000>;
890 renesas,ipmmu-main = <&ipmmu_mm 1>;
891 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
892 #iommu-cells = <1>;
893 };
894
895 ipmmu_hc: iommu@e6570000 {
896 compatible = "renesas,ipmmu-r8a774b1";
897 reg = <0 0xe6570000 0 0x1000>;
898 renesas,ipmmu-main = <&ipmmu_mm 2>;
899 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
900 #iommu-cells = <1>;
901 };
902
903 ipmmu_mm: iommu@e67b0000 {
904 compatible = "renesas,ipmmu-r8a774b1";
905 reg = <0 0xe67b0000 0 0x1000>;
906 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
907 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
908 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
909 #iommu-cells = <1>;
910 };
911
912 ipmmu_mp: iommu@ec670000 {
913 compatible = "renesas,ipmmu-r8a774b1";
914 reg = <0 0xec670000 0 0x1000>;
915 renesas,ipmmu-main = <&ipmmu_mm 4>;
916 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
917 #iommu-cells = <1>;
918 };
919
920 ipmmu_pv0: iommu@fd800000 {
921 compatible = "renesas,ipmmu-r8a774b1";
922 reg = <0 0xfd800000 0 0x1000>;
923 renesas,ipmmu-main = <&ipmmu_mm 6>;
924 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
925 #iommu-cells = <1>;
926 };
927
928 ipmmu_vc0: iommu@fe6b0000 {
929 compatible = "renesas,ipmmu-r8a774b1";
930 reg = <0 0xfe6b0000 0 0x1000>;
931 renesas,ipmmu-main = <&ipmmu_mm 12>;
932 power-domains = <&sysc R8A774B1_PD_A3VC>;
933 #iommu-cells = <1>;
934 };
935
936 ipmmu_vi0: iommu@febd0000 {
937 compatible = "renesas,ipmmu-r8a774b1";
938 reg = <0 0xfebd0000 0 0x1000>;
939 renesas,ipmmu-main = <&ipmmu_mm 14>;
940 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
941 #iommu-cells = <1>;
942 };
943
944 ipmmu_vp0: iommu@fe990000 {
945 compatible = "renesas,ipmmu-r8a774b1";
946 reg = <0 0xfe990000 0 0x1000>;
947 renesas,ipmmu-main = <&ipmmu_mm 16>;
948 power-domains = <&sysc R8A774B1_PD_A3VP>;
949 #iommu-cells = <1>;
950 };
951
952 avb: ethernet@e6800000 {
953 compatible = "renesas,etheravb-r8a774b1",
954 "renesas,etheravb-rcar-gen3";
955 reg = <0 0xe6800000 0 0x800>;
956 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
957 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
958 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
959 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
960 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
961 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
962 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
963 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
964 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
965 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
966 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
967 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
968 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
969 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
970 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
971 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
972 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
973 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
974 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
975 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
976 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
977 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
978 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
979 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
981 interrupt-names = "ch0", "ch1", "ch2", "ch3",
982 "ch4", "ch5", "ch6", "ch7",
983 "ch8", "ch9", "ch10", "ch11",
984 "ch12", "ch13", "ch14", "ch15",
985 "ch16", "ch17", "ch18", "ch19",
986 "ch20", "ch21", "ch22", "ch23",
987 "ch24";
988 clocks = <&cpg CPG_MOD 812>;
989 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
990 resets = <&cpg 812>;
991 phy-mode = "rgmii";
992 iommus = <&ipmmu_ds0 16>;
993 #address-cells = <1>;
994 #size-cells = <0>;
995 status = "disabled";
996 };
997
998 can0: can@e6c30000 {
999 compatible = "renesas,can-r8a774b1",
1000 "renesas,rcar-gen3-can";
1001 reg = <0 0xe6c30000 0 0x1000>;
1002 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1003 clocks = <&cpg CPG_MOD 916>,
1004 <&cpg CPG_CORE R8A774B1_CLK_CANFD>,
1005 <&can_clk>;
1006 clock-names = "clkp1", "clkp2", "can_clk";
1007 assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>;
1008 assigned-clock-rates = <40000000>;
1009 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1010 resets = <&cpg 916>;
1011 status = "disabled";
1012 };
1013
1014 can1: can@e6c38000 {
1015 compatible = "renesas,can-r8a774b1",
1016 "renesas,rcar-gen3-can";
1017 reg = <0 0xe6c38000 0 0x1000>;
1018 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1019 clocks = <&cpg CPG_MOD 915>,
1020 <&cpg CPG_CORE R8A774B1_CLK_CANFD>,
1021 <&can_clk>;
1022 clock-names = "clkp1", "clkp2", "can_clk";
1023 assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>;
1024 assigned-clock-rates = <40000000>;
1025 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1026 resets = <&cpg 915>;
1027 status = "disabled";
1028 };
1029
1030 canfd: can@e66c0000 {
1031 compatible = "renesas,r8a774b1-canfd",
1032 "renesas,rcar-gen3-canfd";
1033 reg = <0 0xe66c0000 0 0x8000>;
1034 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1035 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1036 clocks = <&cpg CPG_MOD 914>,
1037 <&cpg CPG_CORE R8A774B1_CLK_CANFD>,
1038 <&can_clk>;
1039 clock-names = "fck", "canfd", "can_clk";
1040 assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>;
1041 assigned-clock-rates = <40000000>;
1042 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1043 resets = <&cpg 914>;
1044 status = "disabled";
1045
1046 channel0 {
1047 status = "disabled";
1048 };
1049
1050 channel1 {
1051 status = "disabled";
1052 };
1053 };
1054
1055 pwm0: pwm@e6e30000 {
1056 compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
1057 reg = <0 0xe6e30000 0 0x8>;
1058 #pwm-cells = <2>;
1059 clocks = <&cpg CPG_MOD 523>;
1060 resets = <&cpg 523>;
1061 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1062 status = "disabled";
1063 };
1064
1065 pwm1: pwm@e6e31000 {
1066 compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
1067 reg = <0 0xe6e31000 0 0x8>;
1068 #pwm-cells = <2>;
1069 clocks = <&cpg CPG_MOD 523>;
1070 resets = <&cpg 523>;
1071 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1072 status = "disabled";
1073 };
1074
1075 pwm2: pwm@e6e32000 {
1076 compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
1077 reg = <0 0xe6e32000 0 0x8>;
1078 #pwm-cells = <2>;
1079 clocks = <&cpg CPG_MOD 523>;
1080 resets = <&cpg 523>;
1081 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1082 status = "disabled";
1083 };
1084
1085 pwm3: pwm@e6e33000 {
1086 compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
1087 reg = <0 0xe6e33000 0 0x8>;
1088 #pwm-cells = <2>;
1089 clocks = <&cpg CPG_MOD 523>;
1090 resets = <&cpg 523>;
1091 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1092 status = "disabled";
1093 };
1094
1095 pwm4: pwm@e6e34000 {
1096 compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
1097 reg = <0 0xe6e34000 0 0x8>;
1098 #pwm-cells = <2>;
1099 clocks = <&cpg CPG_MOD 523>;
1100 resets = <&cpg 523>;
1101 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1102 status = "disabled";
1103 };
1104
1105 pwm5: pwm@e6e35000 {
1106 compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
1107 reg = <0 0xe6e35000 0 0x8>;
1108 #pwm-cells = <2>;
1109 clocks = <&cpg CPG_MOD 523>;
1110 resets = <&cpg 523>;
1111 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1112 status = "disabled";
1113 };
1114
1115 pwm6: pwm@e6e36000 {
1116 compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
1117 reg = <0 0xe6e36000 0 0x8>;
1118 #pwm-cells = <2>;
1119 clocks = <&cpg CPG_MOD 523>;
1120 resets = <&cpg 523>;
1121 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1122 status = "disabled";
1123 };
1124
1125 scif0: serial@e6e60000 {
1126 compatible = "renesas,scif-r8a774b1",
1127 "renesas,rcar-gen3-scif", "renesas,scif";
1128 reg = <0 0xe6e60000 0 0x40>;
1129 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1130 clocks = <&cpg CPG_MOD 207>,
1131 <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
1132 <&scif_clk>;
1133 clock-names = "fck", "brg_int", "scif_clk";
1134 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1135 <&dmac2 0x51>, <&dmac2 0x50>;
1136 dma-names = "tx", "rx", "tx", "rx";
1137 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1138 resets = <&cpg 207>;
1139 status = "disabled";
1140 };
1141
1142 scif1: serial@e6e68000 {
1143 compatible = "renesas,scif-r8a774b1",
1144 "renesas,rcar-gen3-scif", "renesas,scif";
1145 reg = <0 0xe6e68000 0 0x40>;
1146 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1147 clocks = <&cpg CPG_MOD 206>,
1148 <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
1149 <&scif_clk>;
1150 clock-names = "fck", "brg_int", "scif_clk";
1151 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1152 <&dmac2 0x53>, <&dmac2 0x52>;
1153 dma-names = "tx", "rx", "tx", "rx";
1154 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1155 resets = <&cpg 206>;
1156 status = "disabled";
1157 };
1158
1159 scif2: serial@e6e88000 {
1160 compatible = "renesas,scif-r8a774b1",
1161 "renesas,rcar-gen3-scif", "renesas,scif";
1162 reg = <0 0xe6e88000 0 0x40>;
1163 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1164 clocks = <&cpg CPG_MOD 310>,
1165 <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
1166 <&scif_clk>;
1167 clock-names = "fck", "brg_int", "scif_clk";
1168 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1169 <&dmac2 0x13>, <&dmac2 0x12>;
1170 dma-names = "tx", "rx", "tx", "rx";
1171 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1172 resets = <&cpg 310>;
1173 status = "disabled";
1174 };
1175
1176 scif3: serial@e6c50000 {
1177 compatible = "renesas,scif-r8a774b1",
1178 "renesas,rcar-gen3-scif", "renesas,scif";
1179 reg = <0 0xe6c50000 0 0x40>;
1180 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1181 clocks = <&cpg CPG_MOD 204>,
1182 <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
1183 <&scif_clk>;
1184 clock-names = "fck", "brg_int", "scif_clk";
1185 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1186 dma-names = "tx", "rx";
1187 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1188 resets = <&cpg 204>;
1189 status = "disabled";
1190 };
1191
1192 scif4: serial@e6c40000 {
1193 compatible = "renesas,scif-r8a774b1",
1194 "renesas,rcar-gen3-scif", "renesas,scif";
1195 reg = <0 0xe6c40000 0 0x40>;
1196 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1197 clocks = <&cpg CPG_MOD 203>,
1198 <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
1199 <&scif_clk>;
1200 clock-names = "fck", "brg_int", "scif_clk";
1201 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1202 dma-names = "tx", "rx";
1203 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1204 resets = <&cpg 203>;
1205 status = "disabled";
1206 };
1207
1208 scif5: serial@e6f30000 {
1209 compatible = "renesas,scif-r8a774b1",
1210 "renesas,rcar-gen3-scif", "renesas,scif";
1211 reg = <0 0xe6f30000 0 0x40>;
1212 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1213 clocks = <&cpg CPG_MOD 202>,
1214 <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
1215 <&scif_clk>;
1216 clock-names = "fck", "brg_int", "scif_clk";
1217 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1218 <&dmac2 0x5b>, <&dmac2 0x5a>;
1219 dma-names = "tx", "rx", "tx", "rx";
1220 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1221 resets = <&cpg 202>;
1222 status = "disabled";
1223 };
1224
1225 msiof0: spi@e6e90000 {
1226 compatible = "renesas,msiof-r8a774b1",
1227 "renesas,rcar-gen3-msiof";
1228 reg = <0 0xe6e90000 0 0x0064>;
1229 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1230 clocks = <&cpg CPG_MOD 211>;
1231 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1232 <&dmac2 0x41>, <&dmac2 0x40>;
1233 dma-names = "tx", "rx", "tx", "rx";
1234 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1235 resets = <&cpg 211>;
1236 #address-cells = <1>;
1237 #size-cells = <0>;
1238 status = "disabled";
1239 };
1240
1241 msiof1: spi@e6ea0000 {
1242 compatible = "renesas,msiof-r8a774b1",
1243 "renesas,rcar-gen3-msiof";
1244 reg = <0 0xe6ea0000 0 0x0064>;
1245 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1246 clocks = <&cpg CPG_MOD 210>;
1247 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1248 <&dmac2 0x43>, <&dmac2 0x42>;
1249 dma-names = "tx", "rx", "tx", "rx";
1250 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1251 resets = <&cpg 210>;
1252 #address-cells = <1>;
1253 #size-cells = <0>;
1254 status = "disabled";
1255 };
1256
1257 msiof2: spi@e6c00000 {
1258 compatible = "renesas,msiof-r8a774b1",
1259 "renesas,rcar-gen3-msiof";
1260 reg = <0 0xe6c00000 0 0x0064>;
1261 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1262 clocks = <&cpg CPG_MOD 209>;
1263 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1264 dma-names = "tx", "rx";
1265 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1266 resets = <&cpg 209>;
1267 #address-cells = <1>;
1268 #size-cells = <0>;
1269 status = "disabled";
1270 };
1271
1272 msiof3: spi@e6c10000 {
1273 compatible = "renesas,msiof-r8a774b1",
1274 "renesas,rcar-gen3-msiof";
1275 reg = <0 0xe6c10000 0 0x0064>;
1276 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1277 clocks = <&cpg CPG_MOD 208>;
1278 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1279 dma-names = "tx", "rx";
1280 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1281 resets = <&cpg 208>;
1282 #address-cells = <1>;
1283 #size-cells = <0>;
1284 status = "disabled";
1285 };
1286
1287 vin0: video@e6ef0000 {
1288 compatible = "renesas,vin-r8a774b1";
1289 reg = <0 0xe6ef0000 0 0x1000>;
1290 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1291 clocks = <&cpg CPG_MOD 811>;
1292 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1293 resets = <&cpg 811>;
1294 renesas,id = <0>;
1295 status = "disabled";
1296
1297 ports {
1298 #address-cells = <1>;
1299 #size-cells = <0>;
1300
1301 port@1 {
1302 #address-cells = <1>;
1303 #size-cells = <0>;
1304
1305 reg = <1>;
1306
1307 vin0csi20: endpoint@0 {
1308 reg = <0>;
1309 remote-endpoint = <&csi20vin0>;
1310 };
1311 vin0csi40: endpoint@2 {
1312 reg = <2>;
1313 remote-endpoint = <&csi40vin0>;
1314 };
1315 };
1316 };
1317 };
1318
1319 vin1: video@e6ef1000 {
1320 compatible = "renesas,vin-r8a774b1";
1321 reg = <0 0xe6ef1000 0 0x1000>;
1322 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1323 clocks = <&cpg CPG_MOD 810>;
1324 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1325 resets = <&cpg 810>;
1326 renesas,id = <1>;
1327 status = "disabled";
1328
1329 ports {
1330 #address-cells = <1>;
1331 #size-cells = <0>;
1332
1333 port@1 {
1334 #address-cells = <1>;
1335 #size-cells = <0>;
1336
1337 reg = <1>;
1338
1339 vin1csi20: endpoint@0 {
1340 reg = <0>;
1341 remote-endpoint = <&csi20vin1>;
1342 };
1343 vin1csi40: endpoint@2 {
1344 reg = <2>;
1345 remote-endpoint = <&csi40vin1>;
1346 };
1347 };
1348 };
1349 };
1350
1351 vin2: video@e6ef2000 {
1352 compatible = "renesas,vin-r8a774b1";
1353 reg = <0 0xe6ef2000 0 0x1000>;
1354 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1355 clocks = <&cpg CPG_MOD 809>;
1356 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1357 resets = <&cpg 809>;
1358 renesas,id = <2>;
1359 status = "disabled";
1360
1361 ports {
1362 #address-cells = <1>;
1363 #size-cells = <0>;
1364
1365 port@1 {
1366 #address-cells = <1>;
1367 #size-cells = <0>;
1368
1369 reg = <1>;
1370
1371 vin2csi20: endpoint@0 {
1372 reg = <0>;
1373 remote-endpoint = <&csi20vin2>;
1374 };
1375 vin2csi40: endpoint@2 {
1376 reg = <2>;
1377 remote-endpoint = <&csi40vin2>;
1378 };
1379 };
1380 };
1381 };
1382
1383 vin3: video@e6ef3000 {
1384 compatible = "renesas,vin-r8a774b1";
1385 reg = <0 0xe6ef3000 0 0x1000>;
1386 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1387 clocks = <&cpg CPG_MOD 808>;
1388 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1389 resets = <&cpg 808>;
1390 renesas,id = <3>;
1391 status = "disabled";
1392
1393 ports {
1394 #address-cells = <1>;
1395 #size-cells = <0>;
1396
1397 port@1 {
1398 #address-cells = <1>;
1399 #size-cells = <0>;
1400
1401 reg = <1>;
1402
1403 vin3csi20: endpoint@0 {
1404 reg = <0>;
1405 remote-endpoint = <&csi20vin3>;
1406 };
1407 vin3csi40: endpoint@2 {
1408 reg = <2>;
1409 remote-endpoint = <&csi40vin3>;
1410 };
1411 };
1412 };
1413 };
1414
1415 vin4: video@e6ef4000 {
1416 compatible = "renesas,vin-r8a774b1";
1417 reg = <0 0xe6ef4000 0 0x1000>;
1418 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1419 clocks = <&cpg CPG_MOD 807>;
1420 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1421 resets = <&cpg 807>;
1422 renesas,id = <4>;
1423 status = "disabled";
1424
1425 ports {
1426 #address-cells = <1>;
1427 #size-cells = <0>;
1428
1429 port@1 {
1430 #address-cells = <1>;
1431 #size-cells = <0>;
1432
1433 reg = <1>;
1434
1435 vin4csi20: endpoint@0 {
1436 reg = <0>;
1437 remote-endpoint = <&csi20vin4>;
1438 };
1439 vin4csi40: endpoint@2 {
1440 reg = <2>;
1441 remote-endpoint = <&csi40vin4>;
1442 };
1443 };
1444 };
1445 };
1446
1447 vin5: video@e6ef5000 {
1448 compatible = "renesas,vin-r8a774b1";
1449 reg = <0 0xe6ef5000 0 0x1000>;
1450 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1451 clocks = <&cpg CPG_MOD 806>;
1452 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1453 resets = <&cpg 806>;
1454 renesas,id = <5>;
1455 status = "disabled";
1456
1457 ports {
1458 #address-cells = <1>;
1459 #size-cells = <0>;
1460
1461 port@1 {
1462 #address-cells = <1>;
1463 #size-cells = <0>;
1464
1465 reg = <1>;
1466
1467 vin5csi20: endpoint@0 {
1468 reg = <0>;
1469 remote-endpoint = <&csi20vin5>;
1470 };
1471 vin5csi40: endpoint@2 {
1472 reg = <2>;
1473 remote-endpoint = <&csi40vin5>;
1474 };
1475 };
1476 };
1477 };
1478
1479 vin6: video@e6ef6000 {
1480 compatible = "renesas,vin-r8a774b1";
1481 reg = <0 0xe6ef6000 0 0x1000>;
1482 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1483 clocks = <&cpg CPG_MOD 805>;
1484 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1485 resets = <&cpg 805>;
1486 renesas,id = <6>;
1487 status = "disabled";
1488
1489 ports {
1490 #address-cells = <1>;
1491 #size-cells = <0>;
1492
1493 port@1 {
1494 #address-cells = <1>;
1495 #size-cells = <0>;
1496
1497 reg = <1>;
1498
1499 vin6csi20: endpoint@0 {
1500 reg = <0>;
1501 remote-endpoint = <&csi20vin6>;
1502 };
1503 vin6csi40: endpoint@2 {
1504 reg = <2>;
1505 remote-endpoint = <&csi40vin6>;
1506 };
1507 };
1508 };
1509 };
1510
1511 vin7: video@e6ef7000 {
1512 compatible = "renesas,vin-r8a774b1";
1513 reg = <0 0xe6ef7000 0 0x1000>;
1514 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
1515 clocks = <&cpg CPG_MOD 804>;
1516 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1517 resets = <&cpg 804>;
1518 renesas,id = <7>;
1519 status = "disabled";
1520
1521 ports {
1522 #address-cells = <1>;
1523 #size-cells = <0>;
1524
1525 port@1 {
1526 #address-cells = <1>;
1527 #size-cells = <0>;
1528
1529 reg = <1>;
1530
1531 vin7csi20: endpoint@0 {
1532 reg = <0>;
1533 remote-endpoint = <&csi20vin7>;
1534 };
1535 vin7csi40: endpoint@2 {
1536 reg = <2>;
1537 remote-endpoint = <&csi40vin7>;
1538 };
1539 };
1540 };
1541 };
1542
1543 rcar_sound: sound@ec500000 {
1544 /*
1545 * #sound-dai-cells is required
1546 *
1547 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1548 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1549 */
1550 /*
1551 * #clock-cells is required for audio_clkout0/1/2/3
1552 *
1553 * clkout : #clock-cells = <0>; <&rcar_sound>;
1554 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1555 */
1556 compatible = "renesas,rcar_sound-r8a774b1", "renesas,rcar_sound-gen3";
1557 reg = <0 0xec500000 0 0x1000>, /* SCU */
1558 <0 0xec5a0000 0 0x100>, /* ADG */
1559 <0 0xec540000 0 0x1000>, /* SSIU */
1560 <0 0xec541000 0 0x280>, /* SSI */
1561 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1562 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1563
1564 clocks = <&cpg CPG_MOD 1005>,
1565 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1566 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1567 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1568 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1569 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1570 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1571 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1572 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1573 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1574 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1575 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1576 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1577 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1578 <&audio_clk_a>, <&audio_clk_b>,
1579 <&audio_clk_c>,
1580 <&cpg CPG_CORE R8A774B1_CLK_S0D4>;
1581 clock-names = "ssi-all",
1582 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1583 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1584 "ssi.1", "ssi.0",
1585 "src.9", "src.8", "src.7", "src.6",
1586 "src.5", "src.4", "src.3", "src.2",
1587 "src.1", "src.0",
1588 "mix.1", "mix.0",
1589 "ctu.1", "ctu.0",
1590 "dvc.0", "dvc.1",
1591 "clk_a", "clk_b", "clk_c", "clk_i";
1592 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1593 resets = <&cpg 1005>,
1594 <&cpg 1006>, <&cpg 1007>,
1595 <&cpg 1008>, <&cpg 1009>,
1596 <&cpg 1010>, <&cpg 1011>,
1597 <&cpg 1012>, <&cpg 1013>,
1598 <&cpg 1014>, <&cpg 1015>;
1599 reset-names = "ssi-all",
1600 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1601 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1602 "ssi.1", "ssi.0";
1603 status = "disabled";
1604
1605 rcar_sound,ctu {
1606 ctu00: ctu-0 { };
1607 ctu01: ctu-1 { };
1608 ctu02: ctu-2 { };
1609 ctu03: ctu-3 { };
1610 ctu10: ctu-4 { };
1611 ctu11: ctu-5 { };
1612 ctu12: ctu-6 { };
1613 ctu13: ctu-7 { };
1614 };
1615
1616 rcar_sound,dvc {
1617 dvc0: dvc-0 {
1618 dmas = <&audma1 0xbc>;
1619 dma-names = "tx";
1620 };
1621 dvc1: dvc-1 {
1622 dmas = <&audma1 0xbe>;
1623 dma-names = "tx";
1624 };
1625 };
1626
1627 rcar_sound,mix {
1628 mix0: mix-0 { };
1629 mix1: mix-1 { };
1630 };
1631
1632 rcar_sound,src {
1633 src0: src-0 {
1634 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1635 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1636 dma-names = "rx", "tx";
1637 };
1638 src1: src-1 {
1639 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1640 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1641 dma-names = "rx", "tx";
1642 };
1643 src2: src-2 {
1644 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1645 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1646 dma-names = "rx", "tx";
1647 };
1648 src3: src-3 {
1649 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1650 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1651 dma-names = "rx", "tx";
1652 };
1653 src4: src-4 {
1654 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1655 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1656 dma-names = "rx", "tx";
1657 };
1658 src5: src-5 {
1659 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1660 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1661 dma-names = "rx", "tx";
1662 };
1663 src6: src-6 {
1664 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1665 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1666 dma-names = "rx", "tx";
1667 };
1668 src7: src-7 {
1669 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1670 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1671 dma-names = "rx", "tx";
1672 };
1673 src8: src-8 {
1674 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1675 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1676 dma-names = "rx", "tx";
1677 };
1678 src9: src-9 {
1679 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1680 dmas = <&audma0 0x97>, <&audma1 0xba>;
1681 dma-names = "rx", "tx";
1682 };
1683 };
1684
1685 rcar_sound,ssi {
1686 ssi0: ssi-0 {
1687 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1688 dmas = <&audma0 0x01>, <&audma1 0x02>;
1689 dma-names = "rx", "tx";
1690 };
1691 ssi1: ssi-1 {
1692 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1693 dmas = <&audma0 0x03>, <&audma1 0x04>;
1694 dma-names = "rx", "tx";
1695 };
1696 ssi2: ssi-2 {
1697 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1698 dmas = <&audma0 0x05>, <&audma1 0x06>;
1699 dma-names = "rx", "tx";
1700 };
1701 ssi3: ssi-3 {
1702 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1703 dmas = <&audma0 0x07>, <&audma1 0x08>;
1704 dma-names = "rx", "tx";
1705 };
1706 ssi4: ssi-4 {
1707 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1708 dmas = <&audma0 0x09>, <&audma1 0x0a>;
1709 dma-names = "rx", "tx";
1710 };
1711 ssi5: ssi-5 {
1712 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1713 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
1714 dma-names = "rx", "tx";
1715 };
1716 ssi6: ssi-6 {
1717 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1718 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
1719 dma-names = "rx", "tx";
1720 };
1721 ssi7: ssi-7 {
1722 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1723 dmas = <&audma0 0x0f>, <&audma1 0x10>;
1724 dma-names = "rx", "tx";
1725 };
1726 ssi8: ssi-8 {
1727 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1728 dmas = <&audma0 0x11>, <&audma1 0x12>;
1729 dma-names = "rx", "tx";
1730 };
1731 ssi9: ssi-9 {
1732 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1733 dmas = <&audma0 0x13>, <&audma1 0x14>;
1734 dma-names = "rx", "tx";
1735 };
1736 };
1737
1738 rcar_sound,ssiu {
1739 ssiu00: ssiu-0 {
1740 dmas = <&audma0 0x15>, <&audma1 0x16>;
1741 dma-names = "rx", "tx";
1742 };
1743 ssiu01: ssiu-1 {
1744 dmas = <&audma0 0x35>, <&audma1 0x36>;
1745 dma-names = "rx", "tx";
1746 };
1747 ssiu02: ssiu-2 {
1748 dmas = <&audma0 0x37>, <&audma1 0x38>;
1749 dma-names = "rx", "tx";
1750 };
1751 ssiu03: ssiu-3 {
1752 dmas = <&audma0 0x47>, <&audma1 0x48>;
1753 dma-names = "rx", "tx";
1754 };
1755 ssiu04: ssiu-4 {
1756 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1757 dma-names = "rx", "tx";
1758 };
1759 ssiu05: ssiu-5 {
1760 dmas = <&audma0 0x43>, <&audma1 0x44>;
1761 dma-names = "rx", "tx";
1762 };
1763 ssiu06: ssiu-6 {
1764 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1765 dma-names = "rx", "tx";
1766 };
1767 ssiu07: ssiu-7 {
1768 dmas = <&audma0 0x53>, <&audma1 0x54>;
1769 dma-names = "rx", "tx";
1770 };
1771 ssiu10: ssiu-8 {
1772 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1773 dma-names = "rx", "tx";
1774 };
1775 ssiu11: ssiu-9 {
1776 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1777 dma-names = "rx", "tx";
1778 };
1779 ssiu12: ssiu-10 {
1780 dmas = <&audma0 0x57>, <&audma1 0x58>;
1781 dma-names = "rx", "tx";
1782 };
1783 ssiu13: ssiu-11 {
1784 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1785 dma-names = "rx", "tx";
1786 };
1787 ssiu14: ssiu-12 {
1788 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1789 dma-names = "rx", "tx";
1790 };
1791 ssiu15: ssiu-13 {
1792 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1793 dma-names = "rx", "tx";
1794 };
1795 ssiu16: ssiu-14 {
1796 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1797 dma-names = "rx", "tx";
1798 };
1799 ssiu17: ssiu-15 {
1800 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1801 dma-names = "rx", "tx";
1802 };
1803 ssiu20: ssiu-16 {
1804 dmas = <&audma0 0x63>, <&audma1 0x64>;
1805 dma-names = "rx", "tx";
1806 };
1807 ssiu21: ssiu-17 {
1808 dmas = <&audma0 0x67>, <&audma1 0x68>;
1809 dma-names = "rx", "tx";
1810 };
1811 ssiu22: ssiu-18 {
1812 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1813 dma-names = "rx", "tx";
1814 };
1815 ssiu23: ssiu-19 {
1816 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1817 dma-names = "rx", "tx";
1818 };
1819 ssiu24: ssiu-20 {
1820 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
1821 dma-names = "rx", "tx";
1822 };
1823 ssiu25: ssiu-21 {
1824 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
1825 dma-names = "rx", "tx";
1826 };
1827 ssiu26: ssiu-22 {
1828 dmas = <&audma0 0xED>, <&audma1 0xEE>;
1829 dma-names = "rx", "tx";
1830 };
1831 ssiu27: ssiu-23 {
1832 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
1833 dma-names = "rx", "tx";
1834 };
1835 ssiu30: ssiu-24 {
1836 dmas = <&audma0 0x6f>, <&audma1 0x70>;
1837 dma-names = "rx", "tx";
1838 };
1839 ssiu31: ssiu-25 {
1840 dmas = <&audma0 0x21>, <&audma1 0x22>;
1841 dma-names = "rx", "tx";
1842 };
1843 ssiu32: ssiu-26 {
1844 dmas = <&audma0 0x23>, <&audma1 0x24>;
1845 dma-names = "rx", "tx";
1846 };
1847 ssiu33: ssiu-27 {
1848 dmas = <&audma0 0x25>, <&audma1 0x26>;
1849 dma-names = "rx", "tx";
1850 };
1851 ssiu34: ssiu-28 {
1852 dmas = <&audma0 0x27>, <&audma1 0x28>;
1853 dma-names = "rx", "tx";
1854 };
1855 ssiu35: ssiu-29 {
1856 dmas = <&audma0 0x29>, <&audma1 0x2A>;
1857 dma-names = "rx", "tx";
1858 };
1859 ssiu36: ssiu-30 {
1860 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
1861 dma-names = "rx", "tx";
1862 };
1863 ssiu37: ssiu-31 {
1864 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
1865 dma-names = "rx", "tx";
1866 };
1867 ssiu40: ssiu-32 {
1868 dmas = <&audma0 0x71>, <&audma1 0x72>;
1869 dma-names = "rx", "tx";
1870 };
1871 ssiu41: ssiu-33 {
1872 dmas = <&audma0 0x17>, <&audma1 0x18>;
1873 dma-names = "rx", "tx";
1874 };
1875 ssiu42: ssiu-34 {
1876 dmas = <&audma0 0x19>, <&audma1 0x1A>;
1877 dma-names = "rx", "tx";
1878 };
1879 ssiu43: ssiu-35 {
1880 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
1881 dma-names = "rx", "tx";
1882 };
1883 ssiu44: ssiu-36 {
1884 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
1885 dma-names = "rx", "tx";
1886 };
1887 ssiu45: ssiu-37 {
1888 dmas = <&audma0 0x1F>, <&audma1 0x20>;
1889 dma-names = "rx", "tx";
1890 };
1891 ssiu46: ssiu-38 {
1892 dmas = <&audma0 0x31>, <&audma1 0x32>;
1893 dma-names = "rx", "tx";
1894 };
1895 ssiu47: ssiu-39 {
1896 dmas = <&audma0 0x33>, <&audma1 0x34>;
1897 dma-names = "rx", "tx";
1898 };
1899 ssiu50: ssiu-40 {
1900 dmas = <&audma0 0x73>, <&audma1 0x74>;
1901 dma-names = "rx", "tx";
1902 };
1903 ssiu60: ssiu-41 {
1904 dmas = <&audma0 0x75>, <&audma1 0x76>;
1905 dma-names = "rx", "tx";
1906 };
1907 ssiu70: ssiu-42 {
1908 dmas = <&audma0 0x79>, <&audma1 0x7a>;
1909 dma-names = "rx", "tx";
1910 };
1911 ssiu80: ssiu-43 {
1912 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
1913 dma-names = "rx", "tx";
1914 };
1915 ssiu90: ssiu-44 {
1916 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
1917 dma-names = "rx", "tx";
1918 };
1919 ssiu91: ssiu-45 {
1920 dmas = <&audma0 0x7F>, <&audma1 0x80>;
1921 dma-names = "rx", "tx";
1922 };
1923 ssiu92: ssiu-46 {
1924 dmas = <&audma0 0x81>, <&audma1 0x82>;
1925 dma-names = "rx", "tx";
1926 };
1927 ssiu93: ssiu-47 {
1928 dmas = <&audma0 0x83>, <&audma1 0x84>;
1929 dma-names = "rx", "tx";
1930 };
1931 ssiu94: ssiu-48 {
1932 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
1933 dma-names = "rx", "tx";
1934 };
1935 ssiu95: ssiu-49 {
1936 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
1937 dma-names = "rx", "tx";
1938 };
1939 ssiu96: ssiu-50 {
1940 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
1941 dma-names = "rx", "tx";
1942 };
1943 ssiu97: ssiu-51 {
1944 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
1945 dma-names = "rx", "tx";
1946 };
1947 };
1948 };
1949
1950 audma0: dma-controller@ec700000 {
1951 compatible = "renesas,dmac-r8a774b1",
1952 "renesas,rcar-dmac";
1953 reg = <0 0xec700000 0 0x10000>;
1954 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
1955 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1956 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1957 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1958 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1959 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1960 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1961 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1962 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1963 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1964 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1965 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1966 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1967 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1968 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1969 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1970 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
1971 interrupt-names = "error",
1972 "ch0", "ch1", "ch2", "ch3",
1973 "ch4", "ch5", "ch6", "ch7",
1974 "ch8", "ch9", "ch10", "ch11",
1975 "ch12", "ch13", "ch14", "ch15";
1976 clocks = <&cpg CPG_MOD 502>;
1977 clock-names = "fck";
1978 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
1979 resets = <&cpg 502>;
1980 #dma-cells = <1>;
1981 dma-channels = <16>;
1982 };
1983
1984 audma1: dma-controller@ec720000 {
1985 compatible = "renesas,dmac-r8a774b1",
1986 "renesas,rcar-dmac";
1987 reg = <0 0xec720000 0 0x10000>;
1988 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
1989 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1990 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1991 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1992 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1993 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1994 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1995 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1996 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1997 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
1998 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
1999 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
2000 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2001 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
2002 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
2003 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
2004 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
2005 interrupt-names = "error",
2006 "ch0", "ch1", "ch2", "ch3",
2007 "ch4", "ch5", "ch6", "ch7",
2008 "ch8", "ch9", "ch10", "ch11",
2009 "ch12", "ch13", "ch14", "ch15";
2010 clocks = <&cpg CPG_MOD 501>;
2011 clock-names = "fck";
2012 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2013 resets = <&cpg 501>;
2014 #dma-cells = <1>;
2015 dma-channels = <16>;
2016 };
2017
2018 xhci0: usb@ee000000 {
2019 compatible = "renesas,xhci-r8a774b1",
2020 "renesas,rcar-gen3-xhci";
2021 reg = <0 0xee000000 0 0xc00>;
2022 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2023 clocks = <&cpg CPG_MOD 328>;
2024 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2025 resets = <&cpg 328>;
2026 status = "disabled";
2027 };
2028
2029 usb3_peri0: usb@ee020000 {
2030 compatible = "renesas,r8a774b1-usb3-peri",
2031 "renesas,rcar-gen3-usb3-peri";
2032 reg = <0 0xee020000 0 0x400>;
2033 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2034 clocks = <&cpg CPG_MOD 328>;
2035 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2036 resets = <&cpg 328>;
2037 status = "disabled";
2038 };
2039
2040 ohci0: usb@ee080000 {
2041 compatible = "generic-ohci";
2042 reg = <0 0xee080000 0 0x100>;
2043 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2044 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2045 phys = <&usb2_phy0 1>;
2046 phy-names = "usb";
2047 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2048 resets = <&cpg 703>, <&cpg 704>;
2049 status = "disabled";
2050 };
2051
2052 ohci1: usb@ee0a0000 {
2053 compatible = "generic-ohci";
2054 reg = <0 0xee0a0000 0 0x100>;
2055 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2056 clocks = <&cpg CPG_MOD 702>;
2057 phys = <&usb2_phy1 1>;
2058 phy-names = "usb";
2059 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2060 resets = <&cpg 702>;
2061 status = "disabled";
2062 };
2063
2064 ehci0: usb@ee080100 {
2065 compatible = "generic-ehci";
2066 reg = <0 0xee080100 0 0x100>;
2067 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2068 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2069 phys = <&usb2_phy0 2>;
2070 phy-names = "usb";
2071 companion = <&ohci0>;
2072 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2073 resets = <&cpg 703>, <&cpg 704>;
2074 status = "disabled";
2075 };
2076
2077 ehci1: usb@ee0a0100 {
2078 compatible = "generic-ehci";
2079 reg = <0 0xee0a0100 0 0x100>;
2080 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2081 clocks = <&cpg CPG_MOD 702>;
2082 phys = <&usb2_phy1 2>;
2083 phy-names = "usb";
2084 companion = <&ohci1>;
2085 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2086 resets = <&cpg 702>;
2087 status = "disabled";
2088 };
2089
2090 usb2_phy0: usb-phy@ee080200 {
2091 compatible = "renesas,usb2-phy-r8a774b1",
2092 "renesas,rcar-gen3-usb2-phy";
2093 reg = <0 0xee080200 0 0x700>;
2094 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2095 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2096 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2097 resets = <&cpg 703>, <&cpg 704>;
2098 #phy-cells = <1>;
2099 status = "disabled";
2100 };
2101
2102 usb2_phy1: usb-phy@ee0a0200 {
2103 compatible = "renesas,usb2-phy-r8a774b1",
2104 "renesas,rcar-gen3-usb2-phy";
2105 reg = <0 0xee0a0200 0 0x700>;
2106 clocks = <&cpg CPG_MOD 702>;
2107 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2108 resets = <&cpg 702>;
2109 #phy-cells = <1>;
2110 status = "disabled";
2111 };
2112
2113 sdhi0: mmc@ee100000 {
2114 compatible = "renesas,sdhi-r8a774b1",
2115 "renesas,rcar-gen3-sdhi";
2116 reg = <0 0xee100000 0 0x2000>;
2117 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
2118 clocks = <&cpg CPG_MOD 314>;
2119 max-frequency = <200000000>;
2120 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2121 resets = <&cpg 314>;
2122 status = "disabled";
2123 };
2124
2125 sdhi1: mmc@ee120000 {
2126 compatible = "renesas,sdhi-r8a774b1",
2127 "renesas,rcar-gen3-sdhi";
2128 reg = <0 0xee120000 0 0x2000>;
2129 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
2130 clocks = <&cpg CPG_MOD 313>;
2131 max-frequency = <200000000>;
2132 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2133 resets = <&cpg 313>;
2134 status = "disabled";
2135 };
2136
2137 sdhi2: mmc@ee140000 {
2138 compatible = "renesas,sdhi-r8a774b1",
2139 "renesas,rcar-gen3-sdhi";
2140 reg = <0 0xee140000 0 0x2000>;
2141 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
2142 clocks = <&cpg CPG_MOD 312>;
2143 max-frequency = <200000000>;
2144 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2145 resets = <&cpg 312>;
2146 status = "disabled";
2147 };
2148
2149 sdhi3: mmc@ee160000 {
2150 compatible = "renesas,sdhi-r8a774b1",
2151 "renesas,rcar-gen3-sdhi";
2152 reg = <0 0xee160000 0 0x2000>;
2153 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
2154 clocks = <&cpg CPG_MOD 311>;
2155 max-frequency = <200000000>;
2156 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2157 resets = <&cpg 311>;
2158 status = "disabled";
2159 };
2160
2161 sata: sata@ee300000 {
2162 compatible = "renesas,sata-r8a774b1",
2163 "renesas,rcar-gen3-sata";
2164 reg = <0 0xee300000 0 0x200000>;
2165 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2166 clocks = <&cpg CPG_MOD 815>;
2167 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2168 resets = <&cpg 815>;
2169 status = "disabled";
2170 };
2171
2172 gic: interrupt-controller@f1010000 {
2173 compatible = "arm,gic-400";
2174 #interrupt-cells = <3>;
2175 #address-cells = <0>;
2176 interrupt-controller;
2177 reg = <0x0 0xf1010000 0 0x1000>,
2178 <0x0 0xf1020000 0 0x20000>,
2179 <0x0 0xf1040000 0 0x20000>,
2180 <0x0 0xf1060000 0 0x20000>;
2181 interrupts = <GIC_PPI 9
2182 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
2183 clocks = <&cpg CPG_MOD 408>;
2184 clock-names = "clk";
2185 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2186 resets = <&cpg 408>;
2187 };
2188
2189 pciec0: pcie@fe000000 {
2190 compatible = "renesas,pcie-r8a774b1",
2191 "renesas,pcie-rcar-gen3";
2192 reg = <0 0xfe000000 0 0x80000>;
2193 #address-cells = <3>;
2194 #size-cells = <2>;
2195 bus-range = <0x00 0xff>;
2196 device_type = "pci";
2197 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2198 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2199 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2200 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2201 /* Map all possible DDR as inbound ranges */
2202 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2203 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2204 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2205 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2206 #interrupt-cells = <1>;
2207 interrupt-map-mask = <0 0 0 0>;
2208 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2209 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
2210 clock-names = "pcie", "pcie_bus";
2211 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2212 resets = <&cpg 319>;
2213 status = "disabled";
2214 };
2215
2216 pciec1: pcie@ee800000 {
2217 compatible = "renesas,pcie-r8a774b1",
2218 "renesas,pcie-rcar-gen3";
2219 reg = <0 0xee800000 0 0x80000>;
2220 #address-cells = <3>;
2221 #size-cells = <2>;
2222 bus-range = <0x00 0xff>;
2223 device_type = "pci";
2224 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2225 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2226 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2227 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2228 /* Map all possible DDR as inbound ranges */
2229 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2230 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2231 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2232 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2233 #interrupt-cells = <1>;
2234 interrupt-map-mask = <0 0 0 0>;
2235 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2236 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
2237 clock-names = "pcie", "pcie_bus";
2238 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2239 resets = <&cpg 318>;
2240 status = "disabled";
2241 };
2242
2243 fdp1@fe940000 {
2244 compatible = "renesas,fdp1";
2245 reg = <0 0xfe940000 0 0x2400>;
2246 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
2247 clocks = <&cpg CPG_MOD 119>;
2248 power-domains = <&sysc R8A774B1_PD_A3VP>;
2249 resets = <&cpg 119>;
2250 renesas,fcp = <&fcpf0>;
2251 };
2252
2253 fcpf0: fcp@fe950000 {
2254 compatible = "renesas,fcpf";
2255 reg = <0 0xfe950000 0 0x200>;
2256 clocks = <&cpg CPG_MOD 615>;
2257 power-domains = <&sysc R8A774B1_PD_A3VP>;
2258 resets = <&cpg 615>;
2259 };
2260
2261 vspb: vsp@fe960000 {
2262 compatible = "renesas,vsp2";
2263 reg = <0 0xfe960000 0 0x8000>;
2264 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
2265 clocks = <&cpg CPG_MOD 626>;
2266 power-domains = <&sysc R8A774B1_PD_A3VP>;
2267 resets = <&cpg 626>;
2268
2269 renesas,fcp = <&fcpvb0>;
2270 };
2271
2272 vspi0: vsp@fe9a0000 {
2273 compatible = "renesas,vsp2";
2274 reg = <0 0xfe9a0000 0 0x8000>;
2275 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
2276 clocks = <&cpg CPG_MOD 631>;
2277 power-domains = <&sysc R8A774B1_PD_A3VP>;
2278 resets = <&cpg 631>;
2279
2280 renesas,fcp = <&fcpvi0>;
2281 };
2282
2283 vspd0: vsp@fea20000 {
2284 compatible = "renesas,vsp2";
2285 reg = <0 0xfea20000 0 0x5000>;
2286 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
2287 clocks = <&cpg CPG_MOD 623>;
2288 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2289 resets = <&cpg 623>;
2290
2291 renesas,fcp = <&fcpvd0>;
2292 };
2293
2294 vspd1: vsp@fea28000 {
2295 compatible = "renesas,vsp2";
2296 reg = <0 0xfea28000 0 0x5000>;
2297 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
2298 clocks = <&cpg CPG_MOD 622>;
2299 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2300 resets = <&cpg 622>;
2301
2302 renesas,fcp = <&fcpvd1>;
2303 };
2304
2305 fcpvb0: fcp@fe96f000 {
2306 compatible = "renesas,fcpv";
2307 reg = <0 0xfe96f000 0 0x200>;
2308 clocks = <&cpg CPG_MOD 607>;
2309 power-domains = <&sysc R8A774B1_PD_A3VP>;
2310 resets = <&cpg 607>;
2311 };
2312
2313 fcpvd0: fcp@fea27000 {
2314 compatible = "renesas,fcpv";
2315 reg = <0 0xfea27000 0 0x200>;
2316 clocks = <&cpg CPG_MOD 603>;
2317 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2318 resets = <&cpg 603>;
2319 };
2320
2321 fcpvd1: fcp@fea2f000 {
2322 compatible = "renesas,fcpv";
2323 reg = <0 0xfea2f000 0 0x200>;
2324 clocks = <&cpg CPG_MOD 602>;
2325 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2326 resets = <&cpg 602>;
2327 };
2328
2329 fcpvi0: fcp@fe9af000 {
2330 compatible = "renesas,fcpv";
2331 reg = <0 0xfe9af000 0 0x200>;
2332 clocks = <&cpg CPG_MOD 611>;
2333 power-domains = <&sysc R8A774B1_PD_A3VP>;
2334 resets = <&cpg 611>;
2335 };
2336
2337 csi20: csi2@fea80000 {
2338 compatible = "renesas,r8a774b1-csi2";
2339 reg = <0 0xfea80000 0 0x10000>;
2340 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
2341 clocks = <&cpg CPG_MOD 714>;
2342 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2343 resets = <&cpg 714>;
2344 status = "disabled";
2345
2346 ports {
2347 #address-cells = <1>;
2348 #size-cells = <0>;
2349
2350 port@1 {
2351 #address-cells = <1>;
2352 #size-cells = <0>;
2353
2354 reg = <1>;
2355
2356 csi20vin0: endpoint@0 {
2357 reg = <0>;
2358 remote-endpoint = <&vin0csi20>;
2359 };
2360 csi20vin1: endpoint@1 {
2361 reg = <1>;
2362 remote-endpoint = <&vin1csi20>;
2363 };
2364 csi20vin2: endpoint@2 {
2365 reg = <2>;
2366 remote-endpoint = <&vin2csi20>;
2367 };
2368 csi20vin3: endpoint@3 {
2369 reg = <3>;
2370 remote-endpoint = <&vin3csi20>;
2371 };
2372 csi20vin4: endpoint@4 {
2373 reg = <4>;
2374 remote-endpoint = <&vin4csi20>;
2375 };
2376 csi20vin5: endpoint@5 {
2377 reg = <5>;
2378 remote-endpoint = <&vin5csi20>;
2379 };
2380 csi20vin6: endpoint@6 {
2381 reg = <6>;
2382 remote-endpoint = <&vin6csi20>;
2383 };
2384 csi20vin7: endpoint@7 {
2385 reg = <7>;
2386 remote-endpoint = <&vin7csi20>;
2387 };
2388 };
2389 };
2390 };
2391
2392 csi40: csi2@feaa0000 {
2393 compatible = "renesas,r8a774b1-csi2";
2394 reg = <0 0xfeaa0000 0 0x10000>;
2395 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2396 clocks = <&cpg CPG_MOD 716>;
2397 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2398 resets = <&cpg 716>;
2399 status = "disabled";
2400
2401 ports {
2402 #address-cells = <1>;
2403 #size-cells = <0>;
2404
2405 port@1 {
2406 #address-cells = <1>;
2407 #size-cells = <0>;
2408
2409 reg = <1>;
2410
2411 csi40vin0: endpoint@0 {
2412 reg = <0>;
2413 remote-endpoint = <&vin0csi40>;
2414 };
2415 csi40vin1: endpoint@1 {
2416 reg = <1>;
2417 remote-endpoint = <&vin1csi40>;
2418 };
2419 csi40vin2: endpoint@2 {
2420 reg = <2>;
2421 remote-endpoint = <&vin2csi40>;
2422 };
2423 csi40vin3: endpoint@3 {
2424 reg = <3>;
2425 remote-endpoint = <&vin3csi40>;
2426 };
2427 csi40vin4: endpoint@4 {
2428 reg = <4>;
2429 remote-endpoint = <&vin4csi40>;
2430 };
2431 csi40vin5: endpoint@5 {
2432 reg = <5>;
2433 remote-endpoint = <&vin5csi40>;
2434 };
2435 csi40vin6: endpoint@6 {
2436 reg = <6>;
2437 remote-endpoint = <&vin6csi40>;
2438 };
2439 csi40vin7: endpoint@7 {
2440 reg = <7>;
2441 remote-endpoint = <&vin7csi40>;
2442 };
2443 };
2444 };
2445 };
2446
2447 hdmi0: hdmi@fead0000 {
2448 compatible = "renesas,r8a774b1-hdmi",
2449 "renesas,rcar-gen3-hdmi";
2450 reg = <0 0xfead0000 0 0x10000>;
2451 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
2452 clocks = <&cpg CPG_MOD 729>,
2453 <&cpg CPG_CORE R8A774B1_CLK_HDMI>;
2454 clock-names = "iahb", "isfr";
2455 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2456 resets = <&cpg 729>;
2457 status = "disabled";
2458
2459 ports {
2460 #address-cells = <1>;
2461 #size-cells = <0>;
2462
2463 port@0 {
2464 reg = <0>;
2465 dw_hdmi0_in: endpoint {
2466 remote-endpoint = <&du_out_hdmi0>;
2467 };
2468 };
2469 port@1 {
2470 reg = <1>;
2471 };
2472 port@2 {
2473 /* HDMI sound */
2474 reg = <2>;
2475 };
2476 };
2477 };
2478
2479 du: display@feb00000 {
2480 compatible = "renesas,du-r8a774b1";
2481 reg = <0 0xfeb00000 0 0x80000>;
2482 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2483 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2484 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
2485 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
2486 <&cpg CPG_MOD 721>;
2487 clock-names = "du.0", "du.1", "du.3";
2488 resets = <&cpg 724>, <&cpg 722>;
2489 reset-names = "du.0", "du.3";
2490 status = "disabled";
2491
2492 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
2493
2494 ports {
2495 #address-cells = <1>;
2496 #size-cells = <0>;
2497
2498 port@0 {
2499 reg = <0>;
2500 du_out_rgb: endpoint {
2501 };
2502 };
2503 port@1 {
2504 reg = <1>;
2505 du_out_hdmi0: endpoint {
2506 remote-endpoint = <&dw_hdmi0_in>;
2507 };
2508 };
2509 port@2 {
2510 reg = <2>;
2511 du_out_lvds0: endpoint {
2512 remote-endpoint = <&lvds0_in>;
2513 };
2514 };
2515 };
2516 };
2517
2518 lvds0: lvds@feb90000 {
2519 compatible = "renesas,r8a774b1-lvds";
2520 reg = <0 0xfeb90000 0 0x14>;
2521 clocks = <&cpg CPG_MOD 727>;
2522 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
2523 resets = <&cpg 727>;
2524 status = "disabled";
2525
2526 ports {
2527 #address-cells = <1>;
2528 #size-cells = <0>;
2529
2530 port@0 {
2531 reg = <0>;
2532 lvds0_in: endpoint {
2533 remote-endpoint = <&du_out_lvds0>;
2534 };
2535 };
2536 port@1 {
2537 reg = <1>;
2538 lvds0_out: endpoint {
2539 };
2540 };
2541 };
2542 };
2543
2544 prr: chipid@fff00044 {
2545 compatible = "renesas,prr";
2546 reg = <0 0xfff00044 0 4>;
2547 };
2548 };
2549
2550 thermal-zones {
2551 sensor_thermal1: sensor-thermal1 {
2552 polling-delay-passive = <250>;
2553 polling-delay = <1000>;
2554 thermal-sensors = <&tsc 0>;
2555 sustainable-power = <2439>;
2556
2557 trips {
2558 sensor1_crit: sensor1-crit {
2559 temperature = <120000>;
2560 hysteresis = <1000>;
2561 type = "critical";
2562 };
2563 };
2564 };
2565
2566 sensor_thermal2: sensor-thermal2 {
2567 polling-delay-passive = <250>;
2568 polling-delay = <1000>;
2569 thermal-sensors = <&tsc 1>;
2570 sustainable-power = <2439>;
2571
2572 trips {
2573 sensor2_crit: sensor2-crit {
2574 temperature = <120000>;
2575 hysteresis = <1000>;
2576 type = "critical";
2577 };
2578 };
2579 };
2580
2581 sensor_thermal3: sensor-thermal3 {
2582 polling-delay-passive = <250>;
2583 polling-delay = <1000>;
2584 thermal-sensors = <&tsc 2>;
2585 sustainable-power = <2439>;
2586
2587 cooling-maps {
2588 map0 {
2589 trip = <&target>;
2590 cooling-device = <&a57_0 0 2>;
2591 contribution = <1024>;
2592 };
2593 };
2594 trips {
2595 target: trip-point1 {
2596 temperature = <100000>;
2597 hysteresis = <1000>;
2598 type = "passive";
2599 };
2600
2601 sensor3_crit: sensor3-crit {
2602 temperature = <120000>;
2603 hysteresis = <1000>;
2604 type = "critical";
2605 };
2606 };
2607 };
2608 };
2609
2610 timer {
2611 compatible = "arm,armv8-timer";
2612 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
2613 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
2614 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
2615 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
2616 };
2617
2618 /* External USB clocks - can be overridden by the board */
2619 usb3s0_clk: usb3s0 {
2620 compatible = "fixed-clock";
2621 #clock-cells = <0>;
2622 clock-frequency = <0>;
2623 };
2624
2625 usb_extal_clk: usb_extal {
2626 compatible = "fixed-clock";
2627 #clock-cells = <0>;
2628 clock-frequency = <0>;
2629 };
2630};