| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| Stephen Warren | 48a4c18 | 2016-10-19 15:18:45 -0600 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2016, NVIDIA CORPORATION. |
| Stephen Warren | 48a4c18 | 2016-10-19 15:18:45 -0600 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <config.h> |
| 7 | #include <linux/linkage.h> |
| 8 | |
| 9 | #define SMC_SIP_INVOKE_MCE 0x82FFFF00 |
| 10 | #define MCE_SMC_ROC_FLUSH_CACHE (SMC_SIP_INVOKE_MCE | 11) |
| Stephen Warren | 4146a9a | 2016-10-19 15:18:47 -0600 | [diff] [blame] | 11 | #define MCE_SMC_ROC_FLUSH_CACHE_ONLY (SMC_SIP_INVOKE_MCE | 14) |
| 12 | #define MCE_SMC_ROC_CLEAN_CACHE_ONLY (SMC_SIP_INVOKE_MCE | 15) |
| Stephen Warren | 48a4c18 | 2016-10-19 15:18:45 -0600 | [diff] [blame] | 13 | |
| Stephen Warren | 4146a9a | 2016-10-19 15:18:47 -0600 | [diff] [blame] | 14 | ENTRY(__asm_tegra_cache_smc) |
| Stephen Warren | 48a4c18 | 2016-10-19 15:18:45 -0600 | [diff] [blame] | 15 | mov x1, #0 |
| 16 | mov x2, #0 |
| 17 | mov x3, #0 |
| 18 | mov x4, #0 |
| 19 | mov x5, #0 |
| 20 | mov x6, #0 |
| 21 | smc #0 |
| 22 | mov x0, #0 |
| 23 | ret |
| Stephen Warren | 4146a9a | 2016-10-19 15:18:47 -0600 | [diff] [blame] | 24 | ENDPROC(__asm_invalidate_l3_dcache) |
| 25 | |
| 26 | ENTRY(__asm_invalidate_l3_dcache) |
| 27 | mov x0, #(MCE_SMC_ROC_FLUSH_CACHE_ONLY & 0xffff) |
| 28 | movk x0, #(MCE_SMC_ROC_FLUSH_CACHE_ONLY >> 16), lsl #16 |
| 29 | b __asm_tegra_cache_smc |
| 30 | ENDPROC(__asm_invalidate_l3_dcache) |
| 31 | |
| 32 | ENTRY(__asm_flush_l3_dcache) |
| 33 | mov x0, #(MCE_SMC_ROC_CLEAN_CACHE_ONLY & 0xffff) |
| 34 | movk x0, #(MCE_SMC_ROC_CLEAN_CACHE_ONLY >> 16), lsl #16 |
| 35 | b __asm_tegra_cache_smc |
| Stephen Warren | ddb0f63 | 2016-10-19 15:18:46 -0600 | [diff] [blame] | 36 | ENDPROC(__asm_flush_l3_dcache) |
| Stephen Warren | 4146a9a | 2016-10-19 15:18:47 -0600 | [diff] [blame] | 37 | |
| 38 | ENTRY(__asm_invalidate_l3_icache) |
| 39 | mov x0, #(MCE_SMC_ROC_FLUSH_CACHE & 0xffff) |
| 40 | movk x0, #(MCE_SMC_ROC_FLUSH_CACHE >> 16), lsl #16 |
| 41 | b __asm_tegra_cache_smc |
| 42 | ENDPROC(__asm_invalidate_l3_icache) |