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git01.mediatek.com / filogic / uboot / 5a03ae01e4eae5fb2df8859f67c8d18866348cd6 / . / drivers / net / pic32_eth.h
blob: 823c565a9b8d870347c9ebc0e52a50e216882b0a [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Purna Chandra Mandal6b731c92016-01-28 15:30:21 +0530[diff] [blame]2/*
3 * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
4 *
Purna Chandra Mandal6b731c92016-01-28 15:30:21 +0530[diff] [blame]5 */
6
7#ifndef __MICROCHIP_PIC32_ETH_H_
8#define __MICROCHIP_PIC32_ETH_H_
9
10#include <mach/pic32.h>
11
12/* Ethernet */
13struct pic32_ectl_regs {
14 struct pic32_reg_atomic con1; /* 0x00 */
15 struct pic32_reg_atomic con2; /* 0x10 */
16 struct pic32_reg_atomic txst; /* 0x20 */
17 struct pic32_reg_atomic rxst; /* 0x30 */
18 struct pic32_reg_atomic ht0; /* 0x40 */
19 struct pic32_reg_atomic ht1; /* 0x50 */
20 struct pic32_reg_atomic pmm0; /* 0x60 */
21 struct pic32_reg_atomic pmm1; /* 0x70 */
22 struct pic32_reg_atomic pmcs; /* 0x80 */
23 struct pic32_reg_atomic pmo; /* 0x90 */
24 struct pic32_reg_atomic rxfc; /* 0xa0 */
25 struct pic32_reg_atomic rxwm; /* 0xb0 */
26 struct pic32_reg_atomic ien; /* 0xc0 */
27 struct pic32_reg_atomic irq; /* 0xd0 */
28 struct pic32_reg_atomic stat; /* 0xe0 */
29};
30
31struct pic32_mii_regs {
32 struct pic32_reg_atomic mcfg; /* 0x280 */
33 struct pic32_reg_atomic mcmd; /* 0x290 */
34 struct pic32_reg_atomic madr; /* 0x2a0 */
35 struct pic32_reg_atomic mwtd; /* 0x2b0 */
36 struct pic32_reg_atomic mrdd; /* 0x2c0 */
37 struct pic32_reg_atomic mind; /* 0x2d0 */
38};
39
40struct pic32_emac_regs {
41 struct pic32_reg_atomic cfg1; /* 0x200*/
42 struct pic32_reg_atomic cfg2; /* 0x210*/
43 struct pic32_reg_atomic ipgt; /* 0x220*/
44 struct pic32_reg_atomic ipgr; /* 0x230*/
45 struct pic32_reg_atomic clrt; /* 0x240*/
46 struct pic32_reg_atomic maxf; /* 0x250*/
47 struct pic32_reg_atomic supp; /* 0x260*/
48 struct pic32_reg_atomic test; /* 0x270*/
49 struct pic32_mii_regs mii; /* 0x280 - 0x2d0 */
50 struct pic32_reg_atomic res1; /* 0x2e0 */
51 struct pic32_reg_atomic res2; /* 0x2f0 */
52 struct pic32_reg_atomic sa0; /* 0x300 */
53 struct pic32_reg_atomic sa1; /* 0x310 */
54 struct pic32_reg_atomic sa2; /* 0x320 */
55};
56
57/* ETHCON1 Reg field */
58#define ETHCON_BUFCDEC BIT(0)
59#define ETHCON_RXEN BIT(8)
60#define ETHCON_TXRTS BIT(9)
61#define ETHCON_ON BIT(15)
62
63/* ETHCON2 Reg field */
64#define ETHCON_RXBUFSZ 0x7f
65#define ETHCON_RXBUFSZ_SHFT 0x4
66
67/* ETHSTAT Reg field */
68#define ETHSTAT_BUSY BIT(7)
69#define ETHSTAT_BUFCNT 0x00ff0000
70
71/* ETHRXFC Register fields */
72#define ETHRXFC_BCEN BIT(0)
73#define ETHRXFC_MCEN BIT(1)
74#define ETHRXFC_UCEN BIT(3)
75#define ETHRXFC_RUNTEN BIT(4)
76#define ETHRXFC_CRCOKEN BIT(5)
77
78/* EMAC1CFG1 register offset */
79#define PIC32_EMAC1CFG1 0x0200
80
81/* EMAC1CFG1 register fields */
82#define EMAC_RXENABLE BIT(0)
83#define EMAC_RXPAUSE BIT(2)
84#define EMAC_TXPAUSE BIT(3)
85#define EMAC_SOFTRESET BIT(15)
86
87/* EMAC1CFG2 register fields */
88#define EMAC_FULLDUP BIT(0)
89#define EMAC_LENGTHCK BIT(1)
90#define EMAC_CRCENABLE BIT(4)
91#define EMAC_PADENABLE BIT(5)
92#define EMAC_AUTOPAD BIT(7)
93#define EMAC_EXCESS BIT(14)
94
95/* EMAC1IPGT register magic */
96#define FULLDUP_GAP_TIME 0x15
97#define HALFDUP_GAP_TIME 0x12
98
99/* EMAC1SUPP register fields */
100#define EMAC_RMII_SPD100 BIT(8)
101#define EMAC_RMII_RESET BIT(11)
102
103/* MII Management Configuration Register */
104#define MIIMCFG_RSTMGMT BIT(15)
105#define MIIMCFG_CLKSEL_DIV40 0x0020 /* 100Mhz / 40 */
106
107/* MII Management Command Register */
108#define MIIMCMD_READ BIT(0)
109#define MIIMCMD_SCAN BIT(1)
110
111/* MII Management Address Register */
112#define MIIMADD_REGADDR 0x1f
113#define MIIMADD_REGADDR_SHIFT 0
114#define MIIMADD_PHYADDR_SHIFT 8
115
116/* MII Management Indicator Register */
117#define MIIMIND_BUSY BIT(0)
118#define MIIMIND_NOTVALID BIT(2)
119#define MIIMIND_LINKFAIL BIT(3)
120
121/* Packet Descriptor */
122/* Received Packet Status */
123#define _RSV1_PKT_CSUM 0xffff
124#define _RSV2_CRC_ERR BIT(20)
125#define _RSV2_LEN_ERR BIT(21)
126#define _RSV2_RX_OK BIT(23)
127#define _RSV2_RX_COUNT 0xffff
128
129#define RSV_RX_CSUM(__rsv1) ((__rsv1) & _RSV1_PKT_CSUM)
130#define RSV_RX_COUNT(__rsv2) ((__rsv2) & _RSV2_RX_COUNT)
131#define RSV_RX_OK(__rsv2) ((__rsv2) & _RSV2_RX_OK)
132#define RSV_CRC_ERR(__rsv2) ((__rsv2) & _RSV2_CRC_ERR)
133
134/* Ethernet Hardware Descriptor Header bits */
135#define EDH_EOWN BIT(7)
136#define EDH_NPV BIT(8)
137#define EDH_STICKY BIT(9)
138#define _EDH_BCOUNT 0x07ff0000
139#define EDH_EOP BIT(30)
140#define EDH_SOP BIT(31)
141#define EDH_BCOUNT_SHIFT 16
142#define EDH_BCOUNT(len) ((len) << EDH_BCOUNT_SHIFT)
143
144/* Ethernet Hardware Descriptors
145 * ref: PIC32 Family Reference Manual Table 35-7
146 * This structure represents the layout of the DMA
147 * memory shared between the CPU and the Ethernet
148 * controller.
149 */
150/* TX/RX DMA descriptor */
151struct eth_dma_desc {
152 u32 hdr; /* header */
153 u32 data_buff; /* data buffer address */
154 u32 stat1; /* transmit/receive packet status */
155 u32 stat2; /* transmit/receive packet status */
156 u32 next_ed; /* next descriptor */
157};
158
159#define PIC32_MDIO_NAME "PIC32_EMAC"
160
161int pic32_mdio_init(const char *name, ulong ioaddr);
162
163#endif /* __MICROCHIP_PIC32_ETH_H_*/