Bo Shen | fd12de9 | 2013-11-15 11:12:37 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Atmel Corporation |
| 3 | * Bo Shen <voice.shen@atmel.com> |
| 4 | * |
Wenyou Yang | 0b32638 | 2016-02-01 18:12:16 +0800 | [diff] [blame] | 5 | * Copyright (C) 2015 Atmel Corporation |
| 6 | * Wenyou Yang <wenyou.yang@atmel.com> |
| 7 | * |
Bo Shen | fd12de9 | 2013-11-15 11:12:37 +0800 | [diff] [blame] | 8 | * SPDX-License-Identifier: GPL-2.0+ |
| 9 | */ |
| 10 | |
| 11 | #ifndef __ATMEL_MPDDRC_H__ |
| 12 | #define __ATMEL_MPDDRC_H__ |
| 13 | |
Wenyou Yang | aa0a58d | 2016-02-01 18:12:15 +0800 | [diff] [blame] | 14 | struct atmel_mpddrc_config { |
| 15 | u32 mr; |
| 16 | u32 rtr; |
| 17 | u32 cr; |
| 18 | u32 tpr0; |
| 19 | u32 tpr1; |
| 20 | u32 tpr2; |
| 21 | u32 md; |
| 22 | }; |
| 23 | |
Bo Shen | fd12de9 | 2013-11-15 11:12:37 +0800 | [diff] [blame] | 24 | /* |
| 25 | * Only define the needed register in mpddr |
| 26 | * If other register needed, will add them later |
| 27 | */ |
| 28 | struct atmel_mpddr { |
Wenyou Yang | 0b32638 | 2016-02-01 18:12:16 +0800 | [diff] [blame] | 29 | u32 mr; /* 0x00: Mode Register */ |
| 30 | u32 rtr; /* 0x04: Refresh Timer Register */ |
| 31 | u32 cr; /* 0x08: Configuration Register */ |
| 32 | u32 tpr0; /* 0x0c: Timing Parameter 0 Register */ |
| 33 | u32 tpr1; /* 0x10: Timing Parameter 1 Register */ |
| 34 | u32 tpr2; /* 0x14: Timing Parameter 2 Register */ |
| 35 | u32 reserved; /* 0x18: Reserved */ |
| 36 | u32 lpr; /* 0x1c: Low-power Register */ |
| 37 | u32 md; /* 0x20: Memory Device Register */ |
| 38 | u32 reserved1; /* 0x24: Reserved */ |
| 39 | u32 lpddr23_lpr; /* 0x28: LPDDR2-LPDDR3 Low-power Register*/ |
| 40 | u32 cal_mr4; /* 0x2c: Calibration and MR4 Register */ |
| 41 | u32 tim_cal; /* 0x30: Timing Calibration Register */ |
| 42 | u32 io_calibr; /* 0x34: IO Calibration */ |
| 43 | u32 ocms; /* 0x38: OCMS Register */ |
| 44 | u32 ocms_key1; /* 0x3c: OCMS KEY1 Register */ |
| 45 | u32 ocms_key2; /* 0x40: OCMS KEY2 Register */ |
| 46 | u32 conf_arbiter; /* 0x44: Configuration Arbiter Register */ |
| 47 | u32 timeout; /* 0x48: Timeout Port 0/1/2/3 Register */ |
| 48 | u32 req_port0123; /* 0x4c: Request Port 0/1/2/3 Register */ |
| 49 | u32 req_port4567; /* 0x50: Request Port 4/5/6/7 Register */ |
| 50 | u32 bdw_port0123; /* 0x54: Bandwidth Port 0/1/2/3 Register */ |
| 51 | u32 bdw_port4567; /* 0x58: Bandwidth Port 4/5/6/7 Register */ |
| 52 | u32 rd_data_path; /* 0x5c: Read Datapath Register */ |
| 53 | u32 reserved2[33]; |
| 54 | u32 wpmr; /* 0xe4: Write Protection Mode Register */ |
| 55 | u32 wpsr; /* 0xe8: Write Protection Status Register */ |
| 56 | u32 reserved3[4]; |
| 57 | u32 version; /* 0xfc: IP version */ |
Bo Shen | fd12de9 | 2013-11-15 11:12:37 +0800 | [diff] [blame] | 58 | }; |
| 59 | |
Erik van Luijk | 59d780a | 2015-08-13 15:43:18 +0200 | [diff] [blame] | 60 | |
| 61 | int ddr2_init(const unsigned int base, |
| 62 | const unsigned int ram_address, |
Wenyou Yang | aa0a58d | 2016-02-01 18:12:15 +0800 | [diff] [blame] | 63 | const struct atmel_mpddrc_config *mpddr_value); |
Bo Shen | fd12de9 | 2013-11-15 11:12:37 +0800 | [diff] [blame] | 64 | |
Wenyou Yang | 0b32638 | 2016-02-01 18:12:16 +0800 | [diff] [blame] | 65 | int ddr3_init(const unsigned int base, |
| 66 | const unsigned int ram_address, |
| 67 | const struct atmel_mpddrc_config *mpddr_value); |
| 68 | |
Bo Shen | fd12de9 | 2013-11-15 11:12:37 +0800 | [diff] [blame] | 69 | /* Bit field in mode register */ |
| 70 | #define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD 0x0 |
| 71 | #define ATMEL_MPDDRC_MR_MODE_NOP_CMD 0x1 |
| 72 | #define ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD 0x2 |
| 73 | #define ATMEL_MPDDRC_MR_MODE_LMR_CMD 0x3 |
| 74 | #define ATMEL_MPDDRC_MR_MODE_RFSH_CMD 0x4 |
| 75 | #define ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD 0x5 |
| 76 | #define ATMEL_MPDDRC_MR_MODE_DEEP_CMD 0x6 |
| 77 | #define ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD 0x7 |
| 78 | |
| 79 | /* Bit field in configuration register */ |
| 80 | #define ATMEL_MPDDRC_CR_NC_MASK 0x3 |
| 81 | #define ATMEL_MPDDRC_CR_NC_COL_9 0x0 |
| 82 | #define ATMEL_MPDDRC_CR_NC_COL_10 0x1 |
| 83 | #define ATMEL_MPDDRC_CR_NC_COL_11 0x2 |
| 84 | #define ATMEL_MPDDRC_CR_NC_COL_12 0x3 |
| 85 | #define ATMEL_MPDDRC_CR_NR_MASK (0x3 << 2) |
| 86 | #define ATMEL_MPDDRC_CR_NR_ROW_11 (0x0 << 2) |
| 87 | #define ATMEL_MPDDRC_CR_NR_ROW_12 (0x1 << 2) |
| 88 | #define ATMEL_MPDDRC_CR_NR_ROW_13 (0x2 << 2) |
| 89 | #define ATMEL_MPDDRC_CR_NR_ROW_14 (0x3 << 2) |
| 90 | #define ATMEL_MPDDRC_CR_CAS_MASK (0x7 << 4) |
| 91 | #define ATMEL_MPDDRC_CR_CAS_DDR_CAS2 (0x2 << 4) |
| 92 | #define ATMEL_MPDDRC_CR_CAS_DDR_CAS3 (0x3 << 4) |
| 93 | #define ATMEL_MPDDRC_CR_CAS_DDR_CAS4 (0x4 << 4) |
| 94 | #define ATMEL_MPDDRC_CR_CAS_DDR_CAS5 (0x5 << 4) |
| 95 | #define ATMEL_MPDDRC_CR_CAS_DDR_CAS6 (0x6 << 4) |
| 96 | #define ATMEL_MPDDRC_CR_DLL_RESET_ENABLED (0x1 << 7) |
| 97 | #define ATMEL_MPDDRC_CR_DIC_DS (0x1 << 8) |
| 98 | #define ATMEL_MPDDRC_CR_DIS_DLL (0x1 << 9) |
| 99 | #define ATMEL_MPDDRC_CR_OCD_DEFAULT (0x7 << 12) |
Heiko Schocher | 5834283 | 2014-10-31 08:30:59 +0100 | [diff] [blame] | 100 | #define ATMEL_MPDDRC_CR_DQMS_SHARED (0x1 << 16) |
Bo Shen | fd12de9 | 2013-11-15 11:12:37 +0800 | [diff] [blame] | 101 | #define ATMEL_MPDDRC_CR_ENRDM_ON (0x1 << 17) |
| 102 | #define ATMEL_MPDDRC_CR_NB_8BANKS (0x1 << 20) |
| 103 | #define ATMEL_MPDDRC_CR_NDQS_DISABLED (0x1 << 21) |
| 104 | #define ATMEL_MPDDRC_CR_DECOD_INTERLEAVED (0x1 << 22) |
| 105 | #define ATMEL_MPDDRC_CR_UNAL_SUPPORTED (0x1 << 23) |
| 106 | |
| 107 | /* Bit field in timing parameter 0 register */ |
| 108 | #define ATMEL_MPDDRC_TPR0_TRAS_OFFSET 0 |
| 109 | #define ATMEL_MPDDRC_TPR0_TRAS_MASK 0xf |
| 110 | #define ATMEL_MPDDRC_TPR0_TRCD_OFFSET 4 |
| 111 | #define ATMEL_MPDDRC_TPR0_TRCD_MASK 0xf |
| 112 | #define ATMEL_MPDDRC_TPR0_TWR_OFFSET 8 |
| 113 | #define ATMEL_MPDDRC_TPR0_TWR_MASK 0xf |
| 114 | #define ATMEL_MPDDRC_TPR0_TRC_OFFSET 12 |
| 115 | #define ATMEL_MPDDRC_TPR0_TRC_MASK 0xf |
| 116 | #define ATMEL_MPDDRC_TPR0_TRP_OFFSET 16 |
| 117 | #define ATMEL_MPDDRC_TPR0_TRP_MASK 0xf |
| 118 | #define ATMEL_MPDDRC_TPR0_TRRD_OFFSET 20 |
| 119 | #define ATMEL_MPDDRC_TPR0_TRRD_MASK 0xf |
| 120 | #define ATMEL_MPDDRC_TPR0_TWTR_OFFSET 24 |
| 121 | #define ATMEL_MPDDRC_TPR0_TWTR_MASK 0x7 |
| 122 | #define ATMEL_MPDDRC_TPR0_RDC_WRRD_OFFSET 27 |
| 123 | #define ATMEL_MPDDRC_TPR0_RDC_WRRD_MASK 0x1 |
| 124 | #define ATMEL_MPDDRC_TPR0_TMRD_OFFSET 28 |
| 125 | #define ATMEL_MPDDRC_TPR0_TMRD_MASK 0xf |
| 126 | |
| 127 | /* Bit field in timing parameter 1 register */ |
| 128 | #define ATMEL_MPDDRC_TPR1_TRFC_OFFSET 0 |
| 129 | #define ATMEL_MPDDRC_TPR1_TRFC_MASK 0x7f |
| 130 | #define ATMEL_MPDDRC_TPR1_TXSNR_OFFSET 8 |
| 131 | #define ATMEL_MPDDRC_TPR1_TXSNR_MASK 0xff |
| 132 | #define ATMEL_MPDDRC_TPR1_TXSRD_OFFSET 16 |
| 133 | #define ATMEL_MPDDRC_TPR1_TXSRD_MASK 0xff |
| 134 | #define ATMEL_MPDDRC_TPR1_TXP_OFFSET 24 |
| 135 | #define ATMEL_MPDDRC_TPR1_TXP_MASK 0xf |
| 136 | |
| 137 | /* Bit field in timing parameter 2 register */ |
| 138 | #define ATMEL_MPDDRC_TPR2_TXARD_OFFSET 0 |
| 139 | #define ATMEL_MPDDRC_TPR2_TXARD_MASK 0xf |
| 140 | #define ATMEL_MPDDRC_TPR2_TXARDS_OFFSET 4 |
| 141 | #define ATMEL_MPDDRC_TPR2_TXARDS_MASK 0xf |
| 142 | #define ATMEL_MPDDRC_TPR2_TRPA_OFFSET 8 |
| 143 | #define ATMEL_MPDDRC_TPR2_TRPA_MASK 0xf |
| 144 | #define ATMEL_MPDDRC_TPR2_TRTP_OFFSET 12 |
| 145 | #define ATMEL_MPDDRC_TPR2_TRTP_MASK 0x7 |
| 146 | #define ATMEL_MPDDRC_TPR2_TFAW_OFFSET 16 |
| 147 | #define ATMEL_MPDDRC_TPR2_TFAW_MASK 0xf |
| 148 | |
| 149 | /* Bit field in Memory Device Register */ |
Heiko Schocher | e98ecbc | 2016-08-17 09:13:23 +0200 | [diff] [blame] | 150 | #define ATMEL_MPDDRC_MD_SDR_SDRAM 0x0 |
| 151 | #define ATMEL_MPDDRC_MD_LP_SDR_SDRAM 0x1 |
| 152 | #define ATMEL_MPDDRC_MD_DDR_SDRAM 0x2 |
Bo Shen | fd12de9 | 2013-11-15 11:12:37 +0800 | [diff] [blame] | 153 | #define ATMEL_MPDDRC_MD_LPDDR_SDRAM 0x3 |
Wenyou Yang | 0b32638 | 2016-02-01 18:12:16 +0800 | [diff] [blame] | 154 | #define ATMEL_MPDDRC_MD_DDR3_SDRAM 0x4 |
| 155 | #define ATMEL_MPDDRC_MD_LPDDR3_SDRAM 0x5 |
Bo Shen | fd12de9 | 2013-11-15 11:12:37 +0800 | [diff] [blame] | 156 | #define ATMEL_MPDDRC_MD_DDR2_SDRAM 0x6 |
| 157 | #define ATMEL_MPDDRC_MD_DBW_MASK (0x1 << 4) |
| 158 | #define ATMEL_MPDDRC_MD_DBW_32_BITS (0x0 << 4) |
| 159 | #define ATMEL_MPDDRC_MD_DBW_16_BITS (0x1 << 4) |
| 160 | |
Wenyou Yang | 0b32638 | 2016-02-01 18:12:16 +0800 | [diff] [blame] | 161 | /* Bit field in I/O Calibration Register */ |
| 162 | #define ATMEL_MPDDRC_IO_CALIBR_RDIV 0x7 |
| 163 | |
| 164 | #define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_34_3 0x1 |
| 165 | #define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_40 0x2 |
| 166 | #define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_48 0x3 |
| 167 | #define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_60 0x4 |
| 168 | #define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_80 0x6 |
| 169 | #define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_120 0x7 |
| 170 | |
| 171 | #define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_35 0x2 |
| 172 | #define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_43 0x3 |
| 173 | #define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_52 0x4 |
| 174 | #define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_70 0x6 |
| 175 | #define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_105 0x7 |
| 176 | |
| 177 | #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_37 0x2 |
| 178 | #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_44 0x3 |
| 179 | #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55 0x4 |
| 180 | #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_73 0x6 |
| 181 | #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_110 0x7 |
| 182 | |
| 183 | #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_37 0x2 |
| 184 | #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_44 0x3 |
| 185 | #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55 0x4 |
| 186 | #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_73 0x6 |
| 187 | #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_110 0x7 |
| 188 | |
Wenyou Yang | 5a0243e | 2017-03-23 14:35:33 +0800 | [diff] [blame^] | 189 | #define ATMEL_MPDDRC_IO_CALIBR_TZQIO (0x7f << 8) |
Wenyou Yang | 0b32638 | 2016-02-01 18:12:16 +0800 | [diff] [blame] | 190 | #define ATMEL_MPDDRC_IO_CALIBR_TZQIO_(x) (((x) & 0x7f) << 8) |
| 191 | |
Wenyou Yang | 5a0243e | 2017-03-23 14:35:33 +0800 | [diff] [blame^] | 192 | #define ATMEL_MPDDRC_IO_CALIBR_CALCODEP (0xf << 16) |
| 193 | #define ATMEL_MPDDRC_IO_CALIBR_CALCODEP_(x) (((x) & 0xf) << 16) |
| 194 | #define ATMEL_MPDDRC_IO_CALIBR_CALCODEN (0xf << 20) |
| 195 | #define ATMEL_MPDDRC_IO_CALIBR_CALCODEN_(x) (((x) & 0xf) << 20) |
| 196 | |
Wenyou Yang | 0b32638 | 2016-02-01 18:12:16 +0800 | [diff] [blame] | 197 | #define ATMEL_MPDDRC_IO_CALIBR_EN_CALIB (0x1 << 4) |
| 198 | |
| 199 | /* Bit field in Read Data Path Register */ |
| 200 | #define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING 0x3 |
| 201 | #define ATMEL_MPDDRC_RD_DATA_PATH_NO_SHIFT 0x0 |
| 202 | #define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE 0x1 |
| 203 | #define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE 0x2 |
| 204 | #define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_THREE_CYCLE 0x3 |
| 205 | |
Bo Shen | fd12de9 | 2013-11-15 11:12:37 +0800 | [diff] [blame] | 206 | #endif |