John Rigby | 6478a75 | 2010-01-25 23:12:58 -0700 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2009 DENX Software Engineering |
| 3 | * Author: John Rigby <jrigby@gmail.com> |
| 4 | * |
| 5 | * Based on imx27lite.c: |
| 6 | * Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net> |
| 7 | * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com> |
| 8 | * And: |
| 9 | * RedBoot tx25_misc.c Copyright (C) 2009 Red Hat |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of |
| 14 | * the License, or (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 24 | * MA 02111-1307 USA |
| 25 | * |
| 26 | */ |
| 27 | #include <common.h> |
| 28 | #include <asm/io.h> |
| 29 | #include <asm/arch/imx-regs.h> |
| 30 | #include <asm/arch/imx25-pinmux.h> |
| 31 | |
| 32 | static void mdelay(int n) |
| 33 | { |
| 34 | while (n-- > 0) |
| 35 | udelay(1000); |
| 36 | } |
| 37 | |
| 38 | DECLARE_GLOBAL_DATA_PTR; |
| 39 | |
| 40 | #ifdef CONFIG_FEC_MXC |
| 41 | void tx25_fec_init(void) |
| 42 | { |
| 43 | struct iomuxc_mux_ctl *muxctl; |
| 44 | struct iomuxc_pad_ctl *padctl; |
| 45 | u32 val; |
| 46 | u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5); |
| 47 | struct gpio_regs *gpio4 = (struct gpio_regs *)IMX_GPIO4_BASE; |
| 48 | struct gpio_regs *gpio3 = (struct gpio_regs *)IMX_GPIO3_BASE; |
| 49 | u32 saved_rdata0_mode, saved_rdata1_mode, saved_rx_dv_mode; |
| 50 | |
| 51 | debug("tx25_fec_init\n"); |
| 52 | /* |
| 53 | * fec pin init is generic |
| 54 | */ |
| 55 | mx25_fec_init_pins(); |
| 56 | |
| 57 | /* |
| 58 | * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins. |
| 59 | * |
| 60 | * FEC_RESET_B: gpio4[7] is ALT 5 mode of pin D13 |
| 61 | * FEC_ENABLE_B: gpio4[9] is ALT 5 mode of pin D11 |
| 62 | */ |
| 63 | muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; |
| 64 | padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; |
| 65 | |
| 66 | writel(gpio_mux_mode, &muxctl->pad_d13); |
| 67 | writel(gpio_mux_mode, &muxctl->pad_d11); |
| 68 | |
| 69 | writel(0x0, &padctl->pad_d13); |
| 70 | writel(0x0, &padctl->pad_d11); |
| 71 | |
| 72 | /* drop PHY power and assert reset (low) */ |
| 73 | val = readl(&gpio4->dr) & ~((1 << 7) | (1 << 9)); |
| 74 | writel(val, &gpio4->dr); |
| 75 | val = readl(&gpio4->dir) | (1 << 7) | (1 << 9); |
| 76 | writel(val, &gpio4->dir); |
| 77 | |
| 78 | mdelay(5); |
| 79 | |
| 80 | debug("resetting phy\n"); |
| 81 | |
| 82 | /* turn on PHY power leaving reset asserted */ |
| 83 | val = readl(&gpio4->dr) | 1 << 9; |
| 84 | writel(val, &gpio4->dr); |
| 85 | |
| 86 | mdelay(10); |
| 87 | |
| 88 | /* |
| 89 | * Setup some strapping pins that are latched by the PHY |
| 90 | * as reset goes high. |
| 91 | * |
| 92 | * Set PHY mode to 111 |
| 93 | * mode0 comes from FEC_RDATA0 which is GPIO 3_10 in mux mode 5 |
| 94 | * mode1 comes from FEC_RDATA1 which is GPIO 3_11 in mux mode 5 |
| 95 | * mode2 is tied high so nothing to do |
| 96 | * |
| 97 | * Turn on RMII mode |
| 98 | * RMII mode is selected by FEC_RX_DV which is GPIO 3_12 in mux mode |
| 99 | */ |
| 100 | /* |
| 101 | * save three current mux modes and set each to gpio mode |
| 102 | */ |
| 103 | saved_rdata0_mode = readl(&muxctl->pad_fec_rdata0); |
| 104 | saved_rdata1_mode = readl(&muxctl->pad_fec_rdata1); |
| 105 | saved_rx_dv_mode = readl(&muxctl->pad_fec_rx_dv); |
| 106 | |
| 107 | writel(gpio_mux_mode, &muxctl->pad_fec_rdata0); |
| 108 | writel(gpio_mux_mode, &muxctl->pad_fec_rdata1); |
| 109 | writel(gpio_mux_mode, &muxctl->pad_fec_rx_dv); |
| 110 | |
| 111 | /* |
| 112 | * set each to 1 and make each an output |
| 113 | */ |
| 114 | val = readl(&gpio3->dr) | (1 << 10) | (1 << 11) | (1 << 12); |
| 115 | writel(val, &gpio3->dr); |
| 116 | val = readl(&gpio3->dir) | (1 << 10) | (1 << 11) | (1 << 12); |
| 117 | writel(val, &gpio3->dir); |
| 118 | |
| 119 | mdelay(22); /* this value came from RedBoot */ |
| 120 | |
| 121 | /* |
| 122 | * deassert PHY reset |
| 123 | */ |
| 124 | val = readl(&gpio4->dr) | 1 << 7; |
| 125 | writel(val, &gpio4->dr); |
| 126 | writel(val, &gpio4->dr); |
| 127 | |
| 128 | mdelay(5); |
| 129 | |
| 130 | /* |
| 131 | * set FEC pins back |
| 132 | */ |
| 133 | writel(saved_rdata0_mode, &muxctl->pad_fec_rdata0); |
| 134 | writel(saved_rdata1_mode, &muxctl->pad_fec_rdata1); |
| 135 | writel(saved_rx_dv_mode, &muxctl->pad_fec_rx_dv); |
| 136 | } |
| 137 | #else |
| 138 | #define tx25_fec_init() |
| 139 | #endif |
| 140 | |
| 141 | int board_init() |
| 142 | { |
| 143 | #ifdef CONFIG_MXC_UART |
Fabio Estevam | 59e6fc5 | 2011-03-02 10:14:27 +0100 | [diff] [blame^] | 144 | extern void mx25_uart1_init_pins(void); |
John Rigby | 6478a75 | 2010-01-25 23:12:58 -0700 | [diff] [blame] | 145 | |
Fabio Estevam | 59e6fc5 | 2011-03-02 10:14:27 +0100 | [diff] [blame^] | 146 | mx25_uart1_init_pins(); |
John Rigby | 6478a75 | 2010-01-25 23:12:58 -0700 | [diff] [blame] | 147 | #endif |
Anatolij Gustschin | af3e12a | 2010-04-21 13:52:38 +0200 | [diff] [blame] | 148 | /* board id for linux */ |
| 149 | gd->bd->bi_arch_number = MACH_TYPE_TX25; |
| 150 | gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; |
John Rigby | 6478a75 | 2010-01-25 23:12:58 -0700 | [diff] [blame] | 151 | return 0; |
| 152 | } |
| 153 | |
| 154 | int board_late_init(void) |
| 155 | { |
| 156 | tx25_fec_init(); |
| 157 | return 0; |
| 158 | } |
| 159 | |
| 160 | int dram_init (void) |
| 161 | { |
Heiko Schocher | 0e2412a | 2010-09-17 13:10:42 +0200 | [diff] [blame] | 162 | /* dram_init must store complete ramsize in gd->ram_size */ |
| 163 | gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1, |
| 164 | PHYS_SDRAM_1_SIZE); |
| 165 | return 0; |
| 166 | } |
John Rigby | 6478a75 | 2010-01-25 23:12:58 -0700 | [diff] [blame] | 167 | |
Heiko Schocher | 0e2412a | 2010-09-17 13:10:42 +0200 | [diff] [blame] | 168 | void dram_init_banksize(void) |
| 169 | { |
John Rigby | 6478a75 | 2010-01-25 23:12:58 -0700 | [diff] [blame] | 170 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
| 171 | gd->bd->bi_dram[0].size = get_ram_size((volatile void *)PHYS_SDRAM_1, |
| 172 | PHYS_SDRAM_1_SIZE); |
| 173 | #if CONFIG_NR_DRAM_BANKS > 1 |
| 174 | gd->bd->bi_dram[1].start = PHYS_SDRAM_2; |
| 175 | gd->bd->bi_dram[1].size = get_ram_size((volatile void *)PHYS_SDRAM_2, |
| 176 | PHYS_SDRAM_2_SIZE); |
Heiko Schocher | 0e2412a | 2010-09-17 13:10:42 +0200 | [diff] [blame] | 177 | #else |
John Rigby | 6478a75 | 2010-01-25 23:12:58 -0700 | [diff] [blame] | 178 | |
Heiko Schocher | 0e2412a | 2010-09-17 13:10:42 +0200 | [diff] [blame] | 179 | #endif |
John Rigby | 6478a75 | 2010-01-25 23:12:58 -0700 | [diff] [blame] | 180 | } |
| 181 | |
| 182 | int checkboard(void) |
| 183 | { |
| 184 | printf("KARO TX25\n"); |
| 185 | return 0; |
| 186 | } |