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git01.mediatek.com / filogic / uboot / 59d10d0d44a725fe7d65c713c2cb1570e281edaa / . / dts / upstream / src / arm / ti / omap / omap5.dtsi
blob: bac6fa83879368b447d9e0146d2c998ba6d81fe3 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
4 *
5 * Based on "omap4.dtsi"
6 */
7
8#include <dt-bindings/bus/ti-sysc.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/omap.h>
12#include <dt-bindings/clock/omap5.h>
13
14/ {
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 compatible = "ti,omap5";
19 interrupt-parent = <&wakeupgen>;
20 chosen { };
21
22 aliases {
23 i2c0 = &i2c1;
24 i2c1 = &i2c2;
25 i2c2 = &i2c3;
26 i2c3 = &i2c4;
27 i2c4 = &i2c5;
28 mmc0 = &mmc1;
29 mmc1 = &mmc2;
30 mmc2 = &mmc3;
31 mmc3 = &mmc4;
32 mmc4 = &mmc5;
33 serial0 = &uart1;
34 serial1 = &uart2;
35 serial2 = &uart3;
36 serial3 = &uart4;
37 serial4 = &uart5;
38 serial5 = &uart6;
39 rproc0 = &dsp;
40 rproc1 = &ipu;
41 };
42
43 cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
46
47 cpu0: cpu@0 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a15";
50 reg = <0x0>;
51
52 operating-points = <
53 /* kHz uV */
54 1000000 1060000
55 1500000 1250000
56 >;
57
58 clocks = <&dpll_mpu_ck>;
59 clock-names = "cpu";
60
61 clock-latency = <300000>; /* From omap-cpufreq driver */
62
63 /* cooling options */
64 #cooling-cells = <2>; /* min followed by max */
65 };
66 cpu@1 {
67 device_type = "cpu";
68 compatible = "arm,cortex-a15";
69 reg = <0x1>;
70
71 operating-points = <
72 /* kHz uV */
73 1000000 1060000
74 1500000 1250000
75 >;
76
77 clocks = <&dpll_mpu_ck>;
78 clock-names = "cpu";
79
80 clock-latency = <300000>; /* From omap-cpufreq driver */
81
82 /* cooling options */
83 #cooling-cells = <2>; /* min followed by max */
84 };
85 };
86
87 thermal-zones {
88 #include "omap4-cpu-thermal.dtsi"
89 #include "omap5-gpu-thermal.dtsi"
90 #include "omap5-core-thermal.dtsi"
91 };
92
93 timer {
94 compatible = "arm,armv7-timer";
95 /* PPI secure/nonsecure IRQ */
96 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
97 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
98 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
99 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
100 interrupt-parent = <&gic>;
101 };
102
103 pmu {
104 compatible = "arm,cortex-a15-pmu";
105 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
107 };
108
109 /*
110 * Needed early by omap4_sram_init() for barrier, do not move to l3
111 * interconnect as simple-pm-bus probes at module_init() time.
112 */
113 ocmcram: sram@40300000 {
114 compatible = "mmio-sram";
115 reg = <0 0x40300000 0 0x20000>; /* 128k */
116 };
117
118 gic: interrupt-controller@48211000 {
119 compatible = "arm,cortex-a15-gic";
120 interrupt-controller;
121 #interrupt-cells = <3>;
122 reg = <0 0x48211000 0 0x1000>,
123 <0 0x48212000 0 0x2000>,
124 <0 0x48214000 0 0x2000>,
125 <0 0x48216000 0 0x2000>;
126 interrupt-parent = <&gic>;
127 };
128
129 wakeupgen: interrupt-controller@48281000 {
130 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
131 interrupt-controller;
132 #interrupt-cells = <3>;
133 reg = <0 0x48281000 0 0x1000>;
134 interrupt-parent = <&gic>;
135 };
136
137 /*
138 * XXX: Use a flat representation of the OMAP3 interconnect.
139 * The real OMAP interconnect network is quite complex.
140 * Since it will not bring real advantage to represent that in DT for
141 * the moment, just use a fake OCP bus entry to represent the whole bus
142 * hierarchy.
143 */
144 ocp {
145 compatible = "simple-pm-bus";
146 power-domains = <&prm_core>;
147 clocks = <&l3main1_clkctrl OMAP5_L3_MAIN_1_CLKCTRL 0>,
148 <&l3main2_clkctrl OMAP5_L3_MAIN_2_CLKCTRL 0>,
149 <&l3instr_clkctrl OMAP5_L3_MAIN_3_CLKCTRL 0>;
150 #address-cells = <1>;
151 #size-cells = <1>;
152 ranges = <0 0 0 0xc0000000>;
153 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
154
155 l3-noc@44000000 {
156 compatible = "ti,omap5-l3-noc";
157 reg = <0x44000000 0x2000>,
158 <0x44800000 0x3000>,
159 <0x45000000 0x4000>;
160 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
162 };
163
164 l4_wkup: interconnect@4ae00000 {
165 };
166
167 l4_cfg: interconnect@4a000000 {
168 };
169
170 l4_per: interconnect@48000000 {
171 };
172
173 target-module@48210000 {
174 compatible = "ti,sysc-omap4-simple", "ti,sysc";
175 power-domains = <&prm_mpu>;
176 clocks = <&mpu_clkctrl OMAP5_MPU_CLKCTRL 0>;
177 clock-names = "fck";
178 #address-cells = <1>;
179 #size-cells = <1>;
180 ranges = <0 0x48210000 0x1f0000>;
181
182 mpu {
183 compatible = "ti,omap4-mpu";
184 sram = <&ocmcram>;
185 };
186 };
187
188 l4_abe: interconnect@40100000 {
189 };
190
191 target-module@50000000 {
192 compatible = "ti,sysc-omap2", "ti,sysc";
193 reg = <0x50000000 4>,
194 <0x50000010 4>,
195 <0x50000014 4>;
196 reg-names = "rev", "sysc", "syss";
197 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
198 <SYSC_IDLE_NO>,
199 <SYSC_IDLE_SMART>;
200 ti,syss-mask = <1>;
201 ti,no-idle-on-init;
202 clocks = <&l3main2_clkctrl OMAP5_L3_MAIN_2_GPMC_CLKCTRL 0>;
203 clock-names = "fck";
204 #address-cells = <1>;
205 #size-cells = <1>;
206 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
207 <0x00000000 0x00000000 0x40000000>; /* data */
208
209 gpmc: gpmc@50000000 {
210 compatible = "ti,omap4430-gpmc";
211 reg = <0x50000000 0x1000>;
212 #address-cells = <2>;
213 #size-cells = <1>;
214 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
215 dmas = <&sdma 4>;
216 dma-names = "rxtx";
217 gpmc,num-cs = <8>;
218 gpmc,num-waitpins = <4>;
219 clock-names = "fck";
220 interrupt-controller;
221 #interrupt-cells = <2>;
222 gpio-controller;
223 #gpio-cells = <2>;
224 };
225 };
226
227 target-module@55082000 {
228 compatible = "ti,sysc-omap2", "ti,sysc";
229 reg = <0x55082000 0x4>,
230 <0x55082010 0x4>,
231 <0x55082014 0x4>;
232 reg-names = "rev", "sysc", "syss";
233 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
234 <SYSC_IDLE_NO>,
235 <SYSC_IDLE_SMART>;
236 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
237 SYSC_OMAP2_SOFTRESET |
238 SYSC_OMAP2_AUTOIDLE)>;
239 clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
240 clock-names = "fck";
241 resets = <&prm_core 2>;
242 reset-names = "rstctrl";
243 ranges = <0x0 0x55082000 0x100>;
244 #size-cells = <1>;
245 #address-cells = <1>;
246
247 mmu_ipu: mmu@0 {
248 compatible = "ti,omap4-iommu";
249 reg = <0x0 0x100>;
250 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
251 #iommu-cells = <0>;
252 ti,iommu-bus-err-back;
253 };
254 };
255
256 dsp: dsp {
257 compatible = "ti,omap5-dsp";
258 ti,bootreg = <&scm_conf 0x304 0>;
259 iommus = <&mmu_dsp>;
260 resets = <&prm_dsp 0>;
261 clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
262 firmware-name = "omap5-dsp-fw.xe64T";
263 mboxes = <&mailbox &mbox_dsp>;
264 status = "disabled";
265 };
266
267 ipu: ipu@55020000 {
268 compatible = "ti,omap5-ipu";
269 reg = <0x55020000 0x10000>;
270 reg-names = "l2ram";
271 iommus = <&mmu_ipu>;
272 resets = <&prm_core 0>, <&prm_core 1>;
273 clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
274 firmware-name = "omap5-ipu-fw.xem4";
275 mboxes = <&mailbox &mbox_ipu>;
276 status = "disabled";
277 };
278
279 target-module@4e000000 {
280 compatible = "ti,sysc-omap2", "ti,sysc";
281 reg = <0x4e000000 0x4>,
282 <0x4e000010 0x4>;
283 reg-names = "rev", "sysc";
284 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
285 <SYSC_IDLE_NO>,
286 <SYSC_IDLE_SMART>;
287 ranges = <0x0 0x4e000000 0x2000000>;
288 #size-cells = <1>;
289 #address-cells = <1>;
290
291 dmm@0 {
292 compatible = "ti,omap5-dmm";
293 reg = <0 0x800>;
294 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
295 };
296 };
297
298 target-module@4c000000 {
299 compatible = "ti,sysc-omap4-simple", "ti,sysc";
300 reg = <0x4c000000 0x4>;
301 reg-names = "rev";
302 clocks = <&emif_clkctrl OMAP5_EMIF1_CLKCTRL 0>;
303 clock-names = "fck";
304 ti,no-idle;
305 #address-cells = <1>;
306 #size-cells = <1>;
307 ranges = <0x0 0x4c000000 0x1000000>;
308
309 emif1: emif@0 {
310 compatible = "ti,emif-4d5";
311 reg = <0 0x400>;
312 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
313 phy-type = <2>; /* DDR PHY type: Intelli PHY */
314 hw-caps-read-idle-ctrl;
315 hw-caps-ll-interface;
316 hw-caps-temp-alert;
317 };
318 };
319
320 target-module@4d000000 {
321 compatible = "ti,sysc-omap4-simple", "ti,sysc";
322 reg = <0x4d000000 0x4>;
323 reg-names = "rev";
324 clocks = <&emif_clkctrl OMAP5_EMIF2_CLKCTRL 0>;
325 clock-names = "fck";
326 ti,no-idle;
327 #address-cells = <1>;
328 #size-cells = <1>;
329 ranges = <0x0 0x4d000000 0x1000000>;
330
331 emif2: emif@0 {
332 compatible = "ti,emif-4d5";
333 reg = <0 0x400>;
334 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
335 phy-type = <2>; /* DDR PHY type: Intelli PHY */
336 hw-caps-read-idle-ctrl;
337 hw-caps-ll-interface;
338 hw-caps-temp-alert;
339 };
340 };
341
342 aes1_target: target-module@4b501000 {
343 compatible = "ti,sysc-omap2", "ti,sysc";
344 reg = <0x4b501080 0x4>,
345 <0x4b501084 0x4>,
346 <0x4b501088 0x4>;
347 reg-names = "rev", "sysc", "syss";
348 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
349 SYSC_OMAP2_AUTOIDLE)>;
350 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
351 <SYSC_IDLE_NO>,
352 <SYSC_IDLE_SMART>,
353 <SYSC_IDLE_SMART_WKUP>;
354 ti,syss-mask = <1>;
355 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
356 clocks = <&l4sec_clkctrl OMAP5_AES1_CLKCTRL 0>;
357 clock-names = "fck";
358 #address-cells = <1>;
359 #size-cells = <1>;
360 ranges = <0x0 0x4b501000 0x1000>;
361
362 aes1: aes@0 {
363 compatible = "ti,omap4-aes";
364 reg = <0 0xa0>;
365 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
366 dmas = <&sdma 111>, <&sdma 110>;
367 dma-names = "tx", "rx";
368 };
369 };
370
371 aes2_target: target-module@4b701000 {
372 compatible = "ti,sysc-omap2", "ti,sysc";
373 reg = <0x4b701080 0x4>,
374 <0x4b701084 0x4>,
375 <0x4b701088 0x4>;
376 reg-names = "rev", "sysc", "syss";
377 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
378 SYSC_OMAP2_AUTOIDLE)>;
379 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
380 <SYSC_IDLE_NO>,
381 <SYSC_IDLE_SMART>,
382 <SYSC_IDLE_SMART_WKUP>;
383 ti,syss-mask = <1>;
384 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
385 clocks = <&l4sec_clkctrl OMAP5_AES2_CLKCTRL 0>;
386 clock-names = "fck";
387 #address-cells = <1>;
388 #size-cells = <1>;
389 ranges = <0x0 0x4b701000 0x1000>;
390
391 aes2: aes@0 {
392 compatible = "ti,omap4-aes";
393 reg = <0 0xa0>;
394 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
395 dmas = <&sdma 114>, <&sdma 113>;
396 dma-names = "tx", "rx";
397 };
398 };
399
400 sham_target: target-module@4b100000 {
401 compatible = "ti,sysc-omap3-sham", "ti,sysc";
402 reg = <0x4b100100 0x4>,
403 <0x4b100110 0x4>,
404 <0x4b100114 0x4>;
405 reg-names = "rev", "sysc", "syss";
406 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
407 SYSC_OMAP2_AUTOIDLE)>;
408 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
409 <SYSC_IDLE_NO>,
410 <SYSC_IDLE_SMART>;
411 ti,syss-mask = <1>;
412 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
413 clocks = <&l4sec_clkctrl OMAP5_SHA2MD5_CLKCTRL 0>;
414 clock-names = "fck";
415 #address-cells = <1>;
416 #size-cells = <1>;
417 ranges = <0x0 0x4b100000 0x1000>;
418
419 sham: sham@0 {
420 compatible = "ti,omap4-sham";
421 reg = <0 0x300>;
422 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
423 dmas = <&sdma 119>;
424 dma-names = "rx";
425 };
426 };
427
428 bandgap: bandgap@4a0021e0 {
429 reg = <0x4a0021e0 0xc
430 0x4a00232c 0xc
431 0x4a002380 0x2c
432 0x4a0023C0 0x3c>;
433 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
434 compatible = "ti,omap5430-bandgap";
435
436 #thermal-sensor-cells = <1>;
437 };
438
439 target-module@56000000 {
440 compatible = "ti,sysc-omap4", "ti,sysc";
441 reg = <0x5600fe00 0x4>,
442 <0x5600fe10 0x4>;
443 reg-names = "rev", "sysc";
444 ti,sysc-midle = <SYSC_IDLE_FORCE>,
445 <SYSC_IDLE_NO>,
446 <SYSC_IDLE_SMART>;
447 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
448 <SYSC_IDLE_NO>,
449 <SYSC_IDLE_SMART>;
450 clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
451 clock-names = "fck";
452 #address-cells = <1>;
453 #size-cells = <1>;
454 ranges = <0 0x56000000 0x2000000>;
455
456 /*
457 * Closed source PowerVR driver, no child device
458 * binding or driver in mainline
459 */
460 };
461
462 target-module@58000000 {
463 compatible = "ti,sysc-omap2", "ti,sysc";
464 reg = <0x58000000 4>,
465 <0x58000014 4>;
466 reg-names = "rev", "syss";
467 ti,syss-mask = <1>;
468 power-domains = <&prm_dss>;
469 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>,
470 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
471 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>,
472 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>;
473 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
474 #address-cells = <1>;
475 #size-cells = <1>;
476 ranges = <0 0x58000000 0x1000000>;
477
478 dss: dss@0 {
479 compatible = "ti,omap5-dss";
480 reg = <0 0x80>;
481 status = "disabled";
482 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
483 clock-names = "fck";
484 #address-cells = <1>;
485 #size-cells = <1>;
486 ranges = <0 0 0x1000000>;
487
488 target-module@1000 {
489 compatible = "ti,sysc-omap2", "ti,sysc";
490 reg = <0x1000 0x4>,
491 <0x1010 0x4>,
492 <0x1014 0x4>;
493 reg-names = "rev", "sysc", "syss";
494 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
495 <SYSC_IDLE_NO>,
496 <SYSC_IDLE_SMART>;
497 ti,sysc-midle = <SYSC_IDLE_FORCE>,
498 <SYSC_IDLE_NO>,
499 <SYSC_IDLE_SMART>;
500 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
501 SYSC_OMAP2_ENAWAKEUP |
502 SYSC_OMAP2_SOFTRESET |
503 SYSC_OMAP2_AUTOIDLE)>;
504 ti,syss-mask = <1>;
505 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
506 clock-names = "fck";
507 #address-cells = <1>;
508 #size-cells = <1>;
509 ranges = <0 0x1000 0x1000>;
510
511 dispc@0 {
512 compatible = "ti,omap5-dispc";
513 reg = <0 0x1000>;
514 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
516 clock-names = "fck";
517 };
518 };
519
520 target-module@2000 {
521 compatible = "ti,sysc-omap2", "ti,sysc";
522 reg = <0x2000 0x4>,
523 <0x2010 0x4>,
524 <0x2014 0x4>;
525 reg-names = "rev", "sysc", "syss";
526 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
527 <SYSC_IDLE_NO>,
528 <SYSC_IDLE_SMART>;
529 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
530 SYSC_OMAP2_AUTOIDLE)>;
531 ti,syss-mask = <1>;
532 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
533 clock-names = "fck";
534 #address-cells = <1>;
535 #size-cells = <1>;
536 ranges = <0 0x2000 0x1000>;
537
538 rfbi: encoder@0 {
539 compatible = "ti,omap5-rfbi";
540 reg = <0 0x100>;
541 status = "disabled";
542 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
543 clock-names = "fck", "ick";
544 };
545 };
546
547 target-module@4000 {
548 compatible = "ti,sysc-omap2", "ti,sysc";
549 reg = <0x4000 0x4>,
550 <0x4010 0x4>,
551 <0x4014 0x4>;
552 reg-names = "rev", "sysc", "syss";
553 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
554 <SYSC_IDLE_NO>,
555 <SYSC_IDLE_SMART>;
556 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
557 SYSC_OMAP2_ENAWAKEUP |
558 SYSC_OMAP2_SOFTRESET |
559 SYSC_OMAP2_AUTOIDLE)>;
560 ti,syss-mask = <1>;
561 #address-cells = <1>;
562 #size-cells = <1>;
563 ranges = <0 0x4000 0x1000>;
564
565 dsi1: encoder@0 {
566 compatible = "ti,omap5-dsi";
567 reg = <0 0x200>,
568 <0x200 0x40>,
569 <0x300 0x40>;
570 reg-names = "proto", "phy", "pll";
571 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
572 status = "disabled";
573 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
574 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
575 clock-names = "fck", "sys_clk";
576
577 #address-cells = <1>;
578 #size-cells = <0>;
579 };
580 };
581
582 target-module@9000 {
583 compatible = "ti,sysc-omap2", "ti,sysc";
584 reg = <0x9000 0x4>,
585 <0x9010 0x4>,
586 <0x9014 0x4>;
587 reg-names = "rev", "sysc", "syss";
588 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
589 <SYSC_IDLE_NO>,
590 <SYSC_IDLE_SMART>;
591 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
592 SYSC_OMAP2_ENAWAKEUP |
593 SYSC_OMAP2_SOFTRESET |
594 SYSC_OMAP2_AUTOIDLE)>;
595 ti,syss-mask = <1>;
596 #address-cells = <1>;
597 #size-cells = <1>;
598 ranges = <0 0x9000 0x1000>;
599
600 dsi2: encoder@0 {
601 compatible = "ti,omap5-dsi";
602 reg = <0 0x200>,
603 <0x200 0x40>,
604 <0x300 0x40>;
605 reg-names = "proto", "phy", "pll";
606 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
607 status = "disabled";
608 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
609 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
610 clock-names = "fck", "sys_clk";
611
612 #address-cells = <1>;
613 #size-cells = <0>;
614 };
615 };
616
617 target-module@40000 {
618 compatible = "ti,sysc-omap4", "ti,sysc";
619 reg = <0x40000 0x4>,
620 <0x40010 0x4>;
621 reg-names = "rev", "sysc";
622 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
623 <SYSC_IDLE_NO>,
624 <SYSC_IDLE_SMART>,
625 <SYSC_IDLE_SMART_WKUP>;
626 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
627 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
628 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
629 clock-names = "fck", "dss_clk";
630 #address-cells = <1>;
631 #size-cells = <1>;
632 ranges = <0 0x40000 0x40000>;
633
634 hdmi: encoder@0 {
635 compatible = "ti,omap5-hdmi";
636 reg = <0 0x200>,
637 <0x200 0x80>,
638 <0x300 0x80>,
639 <0x20000 0x19000>;
640 reg-names = "wp", "pll", "phy", "core";
641 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
642 status = "disabled";
643 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
644 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
645 clock-names = "fck", "sys_clk";
646 dmas = <&sdma 76>;
647 dma-names = "audio_tx";
648 };
649 };
650 };
651 };
652
653 abb_mpu: regulator-abb-mpu {
654 compatible = "ti,abb-v2";
655 regulator-name = "abb_mpu";
656 #address-cells = <0>;
657 #size-cells = <0>;
658 clocks = <&sys_clkin>;
659 ti,settling-time = <50>;
660 ti,clock-cycles = <16>;
661
662 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
663 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
664 reg-names = "base-address", "int-address",
665 "efuse-address", "ldo-address";
666 ti,tranxdone-status-mask = <0x80>;
667 /* LDOVBBMPU_MUX_CTRL */
668 ti,ldovbb-override-mask = <0x400>;
669 /* LDOVBBMPU_VSET_OUT */
670 ti,ldovbb-vset-mask = <0x1F>;
671
672 /*
673 * NOTE: only FBB mode used but actual vset will
674 * determine final biasing
675 */
676 ti,abb_info = <
677 /*uV ABB efuse rbb_m fbb_m vset_m*/
678 1060000 0 0x0 0 0x02000000 0x01F00000
679 1250000 0 0x4 0 0x02000000 0x01F00000
680 >;
681 };
682
683 abb_mm: regulator-abb-mm {
684 compatible = "ti,abb-v2";
685 regulator-name = "abb_mm";
686 #address-cells = <0>;
687 #size-cells = <0>;
688 clocks = <&sys_clkin>;
689 ti,settling-time = <50>;
690 ti,clock-cycles = <16>;
691
692 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
693 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
694 reg-names = "base-address", "int-address",
695 "efuse-address", "ldo-address";
696 ti,tranxdone-status-mask = <0x80000000>;
697 /* LDOVBBMM_MUX_CTRL */
698 ti,ldovbb-override-mask = <0x400>;
699 /* LDOVBBMM_VSET_OUT */
700 ti,ldovbb-vset-mask = <0x1F>;
701
702 /*
703 * NOTE: only FBB mode used but actual vset will
704 * determine final biasing
705 */
706 ti,abb_info = <
707 /*uV ABB efuse rbb_m fbb_m vset_m*/
708 1025000 0 0x0 0 0x02000000 0x01F00000
709 1120000 0 0x4 0 0x02000000 0x01F00000
710 >;
711 };
712 };
713};
714
715&cpu_thermal {
716 polling-delay = <500>; /* milliseconds */
717 coefficients = <65 (-1791)>;
718};
719
720#include "omap5-l4.dtsi"
721#include "omap54xx-clocks.dtsi"
722
723&gpu_thermal {
724 coefficients = <117 (-2992)>;
725};
726
727&core_thermal {
728 coefficients = <0 2000>;
729};
730
731#include "omap5-l4-abe.dtsi"
732#include "omap54xx-clocks.dtsi"
733
734&prm {
735 prm_mpu: prm@300 {
736 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
737 reg = <0x300 0x100>;
738 #power-domain-cells = <0>;
739 };
740
741 prm_dsp: prm@400 {
742 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
743 reg = <0x400 0x100>;
744 #reset-cells = <1>;
745 #power-domain-cells = <0>;
746 };
747
748 prm_abe: prm@500 {
749 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
750 reg = <0x500 0x100>;
751 #power-domain-cells = <0>;
752 };
753
754 prm_coreaon: prm@600 {
755 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
756 reg = <0x600 0x100>;
757 #power-domain-cells = <0>;
758 };
759
760 prm_core: prm@700 {
761 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
762 reg = <0x700 0x100>;
763 #reset-cells = <1>;
764 #power-domain-cells = <0>;
765 };
766
767 prm_iva: prm@1200 {
768 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
769 reg = <0x1200 0x100>;
770 #reset-cells = <1>;
771 #power-domain-cells = <0>;
772 };
773
774 prm_cam: prm@1300 {
775 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
776 reg = <0x1300 0x100>;
777 #power-domain-cells = <0>;
778 };
779
780 prm_dss: prm@1400 {
781 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
782 reg = <0x1400 0x100>;
783 #power-domain-cells = <0>;
784 };
785
786 prm_gpu: prm@1500 {
787 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
788 reg = <0x1500 0x100>;
789 #power-domain-cells = <0>;
790 };
791
792 prm_l3init: prm@1600 {
793 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
794 reg = <0x1600 0x100>;
795 #power-domain-cells = <0>;
796 };
797
798 prm_custefuse: prm@1700 {
799 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
800 reg = <0x1700 0x100>;
801 #power-domain-cells = <0>;
802 };
803
804 prm_wkupaon: prm@1800 {
805 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
806 reg = <0x1800 0x100>;
807 #power-domain-cells = <0>;
808 };
809
810 prm_emu: prm@1a00 {
811 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
812 reg = <0x1a00 0x100>;
813 #power-domain-cells = <0>;
814 };
815
816 prm_device: prm@1c00 {
817 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
818 reg = <0x1c00 0x100>;
819 #reset-cells = <1>;
820 };
821};
822
823/* Preferred always-on timer for clockevent */
824&timer1_target {
825 ti,no-reset-on-init;
826 ti,no-idle;
827 timer@0 {
828 assigned-clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
829 assigned-clock-parents = <&sys_32k_ck>;
830 };
831};