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git01.mediatek.com / filogic / uboot / 5996090b241346970a1bdd3a95af398b7d394ccc / . / board / bf548-ezkit / bf548-ezkit.c
blob: 65fb81a9c5906ac00cae5eff90cc8f9910804692 [file] [log] [blame]
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]1/*
2 * U-boot - main board file
3 *
4 * Copyright (c) 2005-2008 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <common.h>
Ben Warrenfbfdd3a2009-07-20 22:01:11 -0700[diff] [blame]10#include <netdev.h>
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]11#include <config.h>
12#include <command.h>
13#include <asm/blackfin.h>
Cliff Caie4638922009-11-20 08:24:43 +0000[diff] [blame]14#include <asm/sdh.h>
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]15
16DECLARE_GLOBAL_DATA_PTR;
17
18int checkboard(void)
19{
20 printf("Board: ADI BF548 EZ-Kit board\n");
21 printf(" Support: http://blackfin.uclinux.org/\n");
22 return 0;
23}
24
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]25int board_early_init_f(void)
26{
27 /* Port H: PH8 - PH13 == A4 - A9
28 * address lines of the parallel asynchronous memory interface
29 */
30
31 /************************************************
32 * configure GPIO *
33 * set port H function enable register *
34 * configure PH8-PH13 as peripheral (not GPIO) *
35 *************************************************/
36 bfin_write_PORTH_FER(0x3F03);
37
38 /************************************************
39 * set port H MUX to configure PH8-PH13 *
40 * 1st Function (MUX = 00) (bits 16-27 == 0) *
41 * Set to address signals A4-A9 *
42 *************************************************/
43 bfin_write_PORTH_MUX(0);
44
45 /************************************************
46 * set port H direction register *
47 * enable PH8-PH13 as outputs *
48 *************************************************/
49 bfin_write_PORTH_DIR_SET(0x3F00);
50
51 /* Port I: PI0 - PH14 == A10 - A24
52 * address lines of the parallel asynchronous memory interface
53 */
54
55 /************************************************
56 * set port I function enable register *
57 * configure PI0-PI14 as peripheral (not GPIO) *
58 *************************************************/
59 bfin_write_PORTI_FER(0x7fff);
60
61 /**************************************************
62 * set PORT I MUX to configure PI14-PI0 as *
63 * 1st Function (MUX=00) - address signals A10-A24 *
64 ***************************************************/
65 bfin_write_PORTI_MUX(0);
66
67 /****************************************
68 * set PORT I direction register *
69 * enable PI0 - PI14 as outputs *
70 *****************************************/
71 bfin_write_PORTI_DIR_SET(0x7fff);
72
73 return 0;
74}
Ben Warrenfbfdd3a2009-07-20 22:01:11 -0700[diff] [blame]75
76#ifdef CONFIG_SMC911X
77int board_eth_init(bd_t *bis)
78{
79 return smc911x_initialize(0, CONFIG_SMC911X_BASE);
80}
81#endif
Cliff Caie4638922009-11-20 08:24:43 +0000[diff] [blame]82
83#ifdef CONFIG_BFIN_SDH
84int board_mmc_init(bd_t *bis)
85{
86 return bfin_mmc_init(bis);
87}
88#endif
Cliff Cai67d94f42009-12-08 07:25:57 +0000[diff] [blame]89
90#ifdef CONFIG_USB_BLACKFIN
91void board_musb_init(void)
92{
93 /*
94 * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both device
95 * and OTG host modes, while rev 1.1 and greater require PE7 to
96 * be low for device mode and high for host mode. We set it high
97 * here because we are in host mode.
98 */
99 bfin_write_PORTE_FER(bfin_read_PORTE_FER() & ~PE7);
100 bfin_write_PORTE_DIR_SET(PE7);
101 bfin_write_PORTE_SET(PE7);
102 SSYNC();
103}
104#endif