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Matthias Fuchs1df4d252009-07-22 13:56:21 +02001/*
2 * (C) Copyright 2009
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Matthias Fuchs1df4d252009-07-22 13:56:21 +02006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#define CONFIG_405EP 1 /* This is a PPC405 CPU */
12#define CONFIG_4xx 1 /* ...member of PPC4xx family */
13#define CONFIG_PMC405DE 1 /* ...on a PMC405DE board */
14
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020015#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
16
Matthias Fuchs1df4d252009-07-22 13:56:21 +020017#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
18#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
19#define CONFIG_BOARD_TYPES 1 /* support board types */
20
21#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
22
23#define CONFIG_BAUDRATE 115200
24#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
25
26#undef CONFIG_BOOTARGS
27#undef CONFIG_BOOTCOMMAND
28
29#define CONFIG_PREBOOT /* enable preboot variable */
30
31#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change*/
32
Matthias Fuchs1df4d252009-07-22 13:56:21 +020033#define CONFIG_HAS_ETH1
34
35#define CONFIG_PPC4xx_EMAC
36#define CONFIG_MII 1 /* MII PHY management */
37#define CONFIG_PHY_ADDR 1 /* PHY address */
38#define CONFIG_PHY1_ADDR 2 /* 2nd PHY address */
39
40#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
41
42/*
43 * BOOTP options
44 */
45#define CONFIG_BOOTP_SUBNETMASK
46#define CONFIG_BOOTP_GATEWAY
47#define CONFIG_BOOTP_HOSTNAME
48#define CONFIG_BOOTP_BOOTPATH
49#define CONFIG_BOOTP_DNS
50#define CONFIG_BOOTP_DNS2
51#define CONFIG_BOOTP_SEND_HOSTNAME
52
53/*
54 * Command line configuration.
55 */
56#include <config_cmd_default.h>
57
58#define CONFIG_CMD_BSP
59#define CONFIG_CMD_CHIP_CONFIG
60#define CONFIG_CMD_DATE
61#define CONFIG_CMD_DHCP
62#define CONFIG_CMD_EEPROM
63#define CONFIG_CMD_ELF
64#define CONFIG_CMD_I2C
65#define CONFIG_CMD_IRQ
66#define CONFIG_CMD_MII
67#define CONFIG_CMD_NFS
68#define CONFIG_CMD_PCI
69#define CONFIG_CMD_PING
70
71#define CONFIG_OF_LIBFDT
72#define CONFIG_OF_BOARD_SETUP
73
74#undef CONFIG_WATCHDOG /* watchdog disabled */
75#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
76#define CONFIG_PRAM 0
77
78/*
79 * Miscellaneous configurable options
80 */
81#define CONFIG_SYS_LONGHELP
82#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
83
84#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
85#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
86#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
87#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
88
89#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
90#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console info */
91
92#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
93#define CONFIG_SYS_MEMTEST_END 0x3000000 /* 1 ... 48 MB in DRAM */
94
Stefan Roese3ddce572010-09-20 16:05:31 +020095#define CONFIG_CONS_INDEX 2 /* Use UART1 */
96#define CONFIG_SYS_NS16550
97#define CONFIG_SYS_NS16550_SERIAL
98#define CONFIG_SYS_NS16550_REG_SIZE 1
99#define CONFIG_SYS_NS16550_CLK get_serial_clock()
100
Matthias Fuchs1df4d252009-07-22 13:56:21 +0200101#undef CONFIG_SYS_EXT_SERIAL_CLOCK
102#define CONFIG_SYS_BASE_BAUD 691200
Matthias Fuchs1df4d252009-07-22 13:56:21 +0200103
Matthias Fuchs1df4d252009-07-22 13:56:21 +0200104#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
105#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
106
107#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
108
109#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
110#define CONFIG_LOOPW 1 /* enable loopw command */
111#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
112#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
113#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
114
115#define CONFIG_AUTOBOOT_KEYED 1
116#define CONFIG_AUTOBOOT_PROMPT \
117 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
118#undef CONFIG_AUTOBOOT_DELAY_STR
119#define CONFIG_AUTOBOOT_STOP_STR " "
120
121/*
122 * PCI stuff
123 */
124#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
125#define PCI_HOST_FORCE 1 /* configure as pci host */
126#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
127
128#define CONFIG_PCI /* include pci support */
Gabor Juhosb4458732013-05-30 07:06:12 +0000129#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Matthias Fuchs1df4d252009-07-22 13:56:21 +0200130#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
131#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
132
133#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
134
135/*
136 * PCI identification
137 */
138#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH
139#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x040e /* Dev ID: Non-Monarch */
140#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x040f /* Dev ID: Monarch */
141#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC
142#define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST
143
144#define CONFIG_SYS_PCI_CLASSCODE CONFIG_SYS_PCI_CLASSCODE_MONARCH
145#define CONFIG_SYS_PCI_SUBSYS_DEVICEID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
146
147#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
148#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable=1 */
149#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
150#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to CPLD, GPIO */
151#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable=1 */
152#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
153
Matthias Fuchsa9d47992009-09-07 17:00:41 +0200154#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
155
Matthias Fuchs1df4d252009-07-22 13:56:21 +0200156/*
157 * For booting Linux, the board info and command line data
158 * have to be in the first 8 MB of memory, since this is
159 * the maximum mapped by the Linux kernel during initialization.
160 */
161#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
162/*
163 * FLASH organization
164 */
165#define CONFIG_SYS_FLASH_CFI 1 /* CFI compatible */
166#define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */
167
168#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
169
170#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max. no. memory banks */
171#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per chip */
172
173#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* erase timeout (in ms) */
174#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* write timeout (in ms) */
175
176#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* buffered writes (faster) */
177#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */
178
179#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* 'E' for empty sector (flinfo) */
180#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
181
182
183/*
184 * Start addresses for the final memory configuration
185 * (Set up by the startup code)
186 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
187 */
188#define CONFIG_SYS_SDRAM_BASE 0x00000000
189#define CONFIG_SYS_FLASH_BASE 0xfe000000
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200190#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
191#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
Matthias Fuchs1df4d252009-07-22 13:56:21 +0200192#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
193
194/*
195 * Environment in EEPROM setup
196 */
197#define CONFIG_ENV_IS_IN_EEPROM 1
198#define CONFIG_ENV_OFFSET 0x100
199#define CONFIG_ENV_SIZE 0x700
200
201/*
202 * I2C EEPROM (24W16) for environment
203 */
Dirk Eibach42b204f2013-04-25 02:40:01 +0000204#define CONFIG_SYS_I2C
205#define CONFIG_SYS_I2C_PPC4XX
206#define CONFIG_SYS_I2C_PPC4XX_CH0
207#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
208#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
Matthias Fuchs1df4d252009-07-22 13:56:21 +0200209
210#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24W16 */
211#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
212/* mask of address bits that overflow into the "EEPROM chip address" */
213#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
214#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
215 /* 16 byte page write mode using*/
216 /* last 4 bits of the address */
217#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
218#define CONFIG_SYS_EEPROM_WREN 1
219
220#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50
221#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0x40
222#define CONFIG_4xx_CONFIG_BLOCKSIZE 0x20
223
224/*
225 * RTC
226 */
227#define CONFIG_RTC_RX8025
228
229/*
230 * External Bus Controller (EBC) Setup
231 * (max. 55MHZ EBC clock)
232 */
233/* Memory Bank 0 (NOR flash) BAS=0xFE0,BS=32MB,BU=R/W,BW=16bit */
234#define CONFIG_SYS_EBC_PB0AP 0x03017200
235#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xba000)
236
237/* Memory Bank 1 (CPLD) BAS=0xEF0,BS=16MB,BU=R/W,BW=16bit */
238#define CONFIG_SYS_CPLD_BASE 0xef000000
239#define CONFIG_SYS_EBC_PB1AP 0x00800000
240#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_CPLD_BASE | 0x18000)
241
242/*
243 * Definitions for initial stack pointer and data area (in data cache)
244 */
245/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
246#define CONFIG_SYS_TEMP_STACK_OCM 1
247
248/* On Chip Memory location */
249#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
250#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
251/* inside SDRAM */
252#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
253/* End of used area in RAM */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200254#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
Matthias Fuchs1df4d252009-07-22 13:56:21 +0200255
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200256#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
Wolfgang Denk0191e472010-10-26 14:34:52 +0200257 GENERATED_GBL_DATA_SIZE)
Matthias Fuchs1df4d252009-07-22 13:56:21 +0200258#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
259
260/*
261 * GPIO Configuration
262 */
263#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alt1 */ \
264{ \
265/* GPIO Core 0 */ \
266{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
267{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
268{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
269{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
270{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
271{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
272{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO6 TS4 */ \
273{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
274{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
275{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO9 TrcClk */ \
276{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
277{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
278{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
279{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
280{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
281{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
282{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
283{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
284{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
285{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
286{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
287{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
288{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
289{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
290{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
291{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
292{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
293{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
294{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
295{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
296{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
297{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
298} \
299}
300
301#define CONFIG_SYS_GPIO_HWREV_MASK (0xf0000000 >> 1) /* GPIO1..4 */
302#define CONFIG_SYS_GPIO_HWREV_SHIFT 27
303#define CONFIG_SYS_GPIO_LEDRUN_N (0x80000000 >> 5) /* GPIO5 */
304#define CONFIG_SYS_GPIO_LEDA_N (0x80000000 >> 6) /* GPIO6 */
305#define CONFIG_SYS_GPIO_LEDB_N (0x80000000 >> 7) /* GPIO7 */
306#define CONFIG_SYS_GPIO_SELFRST_N (0x80000000 >> 8) /* GPIO8 */
307#define CONFIG_SYS_GPIO_EEPROM_WP (0x80000000 >> 9) /* GPIO9 */
308#define CONFIG_SYS_GPIO_MONARCH_N (0x80000000 >> 11) /* GPIO11 */
309#define CONFIG_SYS_GPIO_EREADY (0x80000000 >> 12) /* GPIO12 */
310#define CONFIG_SYS_GPIO_M66EN (0x80000000 >> 13) /* GPIO13 */
311
312/*
313 * Default speed selection (cpu_plb_opb_ebc) in mhz.
314 * This value will be set if iic boot eprom is disabled.
315 */
316#undef CONFIG_SYS_FCPU333MHZ
317#define CONFIG_SYS_FCPU266MHZ
318#undef CONFIG_SYS_FCPU133MHZ
319
320#if defined(CONFIG_SYS_FCPU333MHZ)
321/*
322 * CPU: 333MHz
323 * PLB/SDRAM/MAL: 111MHz
324 * OPB: 55MHz
325 * EBC: 55MHz
326 * PCI: 55MHz (111MHz on M66EN=1)
327 */
328#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
329 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
330 PLL_MALDIV_1 | PLL_PCIDIV_2)
331#define PLLMR1_DEFAULT (PLL_FBKDIV_10 | \
332 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
333 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
334#endif
335
336#if defined(CONFIG_SYS_FCPU266MHZ)
337/*
338 * CPU: 266MHz
339 * PLB/SDRAM/MAL: 133MHz
340 * OPB: 66MHz
341 * EBC: 44MHz
342 * PCI: 44MHz (66MHz on M66EN=1)
343 */
344#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
345 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
346 PLL_MALDIV_1 | PLL_PCIDIV_3)
347#define PLLMR1_DEFAULT (PLL_FBKDIV_8 | \
348 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
349 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
350#endif
351
352#if defined(CONFIG_SYS_FCPU133MHZ)
353/*
354 * CPU: 133MHz
355 * PLB/SDRAM/MAL: 133MHz
356 * OPB: 66MHz
357 * EBC: 44MHz
358 * PCI: 44MHz (66MHz on M66EN=1)
359 */
360#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
361 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
362 PLL_MALDIV_1 | PLL_PCIDIV_3)
363#define PLLMR1_DEFAULT (PLL_FBKDIV_4 | \
364 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
365 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
366#endif
367
368#endif /* __CONFIG_H */