blob: 174a8a7d78f132a9fc0d60b0cb3f2eacb072a618 [file] [log] [blame]
Poonam Aggrwalf857ed92009-08-21 07:29:58 +05301/*
2 * Copyright 2009 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24#include <command.h>
25#include <pci.h>
26#include <asm/immap_85xx.h>
27#include <asm/io.h>
28#include <asm/fsl_pci.h>
29#include <libfdt.h>
30#include <fdt_support.h>
31
32DECLARE_GLOBAL_DATA_PTR;
33
34#ifdef CONFIG_PCIE1
35static struct pci_controller pcie1_hose;
36#endif
37
38#ifdef CONFIG_PCIE2
39static struct pci_controller pcie2_hose;
40#endif
41
42void pci_init_board(void)
43{
44 struct fsl_pci_info pci_info[2];
45 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
46 uint devdisr = in_be32(&gur->devdisr);
47 uint io_sel = (in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_IO_SEL) >> 19;
48 uint host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
49 int num = 0;
50 int first_free_busno = 0;
51
52 int pcie_ep, pcie_configured;
53
54 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
55 devdisr, io_sel, host_agent);
56
57 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
58 printf (" eTSEC2 is in sgmii mode.\n");
59
60#ifdef CONFIG_PCIE2
61 SET_STD_PCIE_INFO(pci_info[num], 2);
62 pcie_ep = (host_agent == 2) || (host_agent == 4) ||
63 (host_agent == 6) || (host_agent == 0);
64 pcie_configured = (io_sel == 0xE);
65
66 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
67 puts ("\n PCIE2 connected to Slot 1 as ");
68 printf ("%s (base address %lx)",
69 pcie_ep ? "End Point": "Root Complex", pci_info[num].regs);
70 first_free_busno = fsl_pci_init_port(&pci_info[num],
71 &pcie2_hose, first_free_busno);
72 num++;
73 } else {
74 printf (" PCIE2: disabled\n");
75 }
76#else
77 set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
78#endif
79
80#ifdef CONFIG_PCIE1
81 SET_STD_PCIE_INFO(pci_info[num], 1);
82
83 pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
84 (host_agent == 5);
85 pcie_configured = (io_sel == 0xE);
86
87 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
88 puts ("\n PCIE1 connected to Slot 2 as ");
89 printf ("%s (base address %lx)",
90 pcie_ep ? "End Point" : "Root Complex",
91 pci_info[num].regs);
92 first_free_busno = fsl_pci_init_port(&pci_info[num],
93 &pcie1_hose, first_free_busno);
94 num++;
95 } else {
96 printf (" PCIE1: disabled\n");
97 }
98#else
99 set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
100#endif
101}
102
103void ft_pci_board_setup(void *blob)
104{
105/* According to h/w manual, PCIE2 is at lower address(0x9000)
106 * than PCIE1(0xa000).
107 * Hence PCIE2 is made to occupy the pci1 position in dts to
108 * keep the addresses sorted there.
109 * Generally the case with all FSL SOCs.
110 */
111#ifdef CONFIG_PCIE2
112 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
113#endif
114#ifdef CONFIG_PCIE1
115 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
116#endif
117}