| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Rockchip PCIe v3 phy |
| 8 | |
| 9 | maintainers: |
| 10 | - Heiko Stuebner <heiko@sntech.de> |
| 11 | |
| 12 | properties: |
| 13 | compatible: |
| 14 | enum: |
| 15 | - rockchip,rk3568-pcie3-phy |
| 16 | - rockchip,rk3588-pcie3-phy |
| 17 | |
| 18 | reg: |
| 19 | maxItems: 1 |
| 20 | |
| 21 | clocks: |
| 22 | minItems: 1 |
| 23 | maxItems: 3 |
| 24 | |
| 25 | clock-names: |
| 26 | minItems: 1 |
| 27 | maxItems: 3 |
| 28 | |
| 29 | data-lanes: |
| 30 | description: which lanes (by position) should be mapped to which |
| 31 | controller (value). 0 means lane disabled, higher value means used. |
| 32 | (controller-number +1 ) |
| 33 | $ref: /schemas/types.yaml#/definitions/uint32-array |
| 34 | minItems: 2 |
| 35 | maxItems: 16 |
| 36 | items: |
| 37 | minimum: 0 |
| 38 | maximum: 16 |
| 39 | |
| 40 | "#phy-cells": |
| 41 | const: 0 |
| 42 | |
| 43 | resets: |
| 44 | maxItems: 1 |
| 45 | |
| 46 | reset-names: |
| 47 | const: phy |
| 48 | |
| 49 | rockchip,phy-grf: |
| 50 | $ref: /schemas/types.yaml#/definitions/phandle |
| 51 | description: phandle to the syscon managing the phy "general register files" |
| 52 | |
| 53 | rockchip,pipe-grf: |
| 54 | $ref: /schemas/types.yaml#/definitions/phandle |
| 55 | description: phandle to the syscon managing the pipe "general register files" |
| 56 | |
| Tom Rini | 762f85b | 2024-07-20 11:15:10 -0600 | [diff] [blame] | 57 | rockchip,rx-common-refclk-mode: |
| 58 | description: which lanes (by position) should be configured to run in |
| 59 | RX common reference clock mode. 0 means disabled, 1 means enabled. |
| 60 | $ref: /schemas/types.yaml#/definitions/uint32-array |
| 61 | minItems: 1 |
| 62 | maxItems: 16 |
| 63 | items: |
| 64 | minimum: 0 |
| 65 | maximum: 1 |
| 66 | |
| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 67 | required: |
| 68 | - compatible |
| 69 | - reg |
| 70 | - rockchip,phy-grf |
| 71 | - "#phy-cells" |
| 72 | |
| 73 | allOf: |
| 74 | - if: |
| 75 | properties: |
| 76 | compatible: |
| 77 | enum: |
| 78 | - rockchip,rk3588-pcie3-phy |
| 79 | then: |
| 80 | properties: |
| 81 | clocks: |
| 82 | maxItems: 1 |
| 83 | clock-names: |
| 84 | items: |
| 85 | - const: pclk |
| 86 | else: |
| 87 | properties: |
| 88 | clocks: |
| 89 | minItems: 3 |
| 90 | |
| 91 | clock-names: |
| 92 | items: |
| 93 | - const: refclk_m |
| 94 | - const: refclk_n |
| 95 | - const: pclk |
| 96 | |
| 97 | additionalProperties: false |
| 98 | |
| 99 | examples: |
| 100 | - | |
| 101 | #include <dt-bindings/clock/rk3568-cru.h> |
| 102 | pcie30phy: phy@fe8c0000 { |
| 103 | compatible = "rockchip,rk3568-pcie3-phy"; |
| 104 | reg = <0xfe8c0000 0x20000>; |
| 105 | #phy-cells = <0>; |
| 106 | clocks = <&pmucru CLK_PCIE30PHY_REF_M>, |
| 107 | <&pmucru CLK_PCIE30PHY_REF_N>, |
| 108 | <&cru PCLK_PCIE30PHY>; |
| 109 | clock-names = "refclk_m", "refclk_n", "pclk"; |
| 110 | resets = <&cru SRST_PCIE30PHY>; |
| 111 | reset-names = "phy"; |
| 112 | rockchip,phy-grf = <&pcie30_phy_grf>; |
| 113 | }; |