blob: efa2408b204b421ad1c5a36b039d8c07c5b7237e [file] [log] [blame]
Jagan Teki28c0adf2022-12-14 23:20:57 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2020 Rockchip Electronics Co., Ltd
4 */
5
Jagan Teki28c0adf2022-12-14 23:20:57 +05306#include <dm.h>
7#include <log.h>
8#include <dm/pinctrl.h>
9#include <regmap.h>
10#include <syscon.h>
11#include <linux/bitops.h>
12#include <dt-bindings/pinctrl/rockchip.h>
13
14#include "pinctrl-rockchip.h"
15
16static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = {
17 {
18 .num = 0,
19 .pin = 20,
20 .reg = 0x10000,
21 .bit = 0,
22 .mask = 0xf
23 },
24 {
25 .num = 0,
26 .pin = 21,
27 .reg = 0x10000,
28 .bit = 4,
29 .mask = 0xf
30 },
31 {
32 .num = 0,
33 .pin = 22,
34 .reg = 0x10000,
35 .bit = 8,
36 .mask = 0xf
37 },
38 {
39 .num = 0,
40 .pin = 23,
41 .reg = 0x10000,
42 .bit = 12,
43 .mask = 0xf
44 },
45};
46
47static struct rockchip_mux_route_data rv1126_mux_route_data[] = {
48 MR_TOPGRF(RK_GPIO3, RK_PD2, 1, 0x10260, RK_GENMASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */
49 MR_TOPGRF(RK_GPIO3, RK_PB0, 3, 0x10260, RK_GENMASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */
50
51 MR_TOPGRF(RK_GPIO0, RK_PD4, 4, 0x10260, RK_GENMASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */
52 MR_TOPGRF(RK_GPIO1, RK_PD5, 2, 0x10260, RK_GENMASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */
53 MR_TOPGRF(RK_GPIO2, RK_PC7, 6, 0x10260, RK_GENMASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */
54
55 MR_TOPGRF(RK_GPIO1, RK_PD0, 1, 0x10260, RK_GENMASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */
56 MR_TOPGRF(RK_GPIO2, RK_PB3, 2, 0x10260, RK_GENMASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */
57
58 MR_TOPGRF(RK_GPIO3, RK_PD4, 2, 0x10260, RK_GENMASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */
59 MR_TOPGRF(RK_GPIO3, RK_PC0, 3, 0x10260, RK_GENMASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */
60
61 MR_TOPGRF(RK_GPIO3, RK_PC6, 1, 0x10264, RK_GENMASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */
62 MR_TOPGRF(RK_GPIO2, RK_PD1, 3, 0x10264, RK_GENMASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */
63
64 MR_TOPGRF(RK_GPIO3, RK_PA4, 5, 0x10264, RK_GENMASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */
65 MR_TOPGRF(RK_GPIO2, RK_PD4, 7, 0x10264, RK_GENMASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */
66 MR_TOPGRF(RK_GPIO1, RK_PD6, 3, 0x10264, RK_GENMASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */
67
68 MR_TOPGRF(RK_GPIO3, RK_PA0, 7, 0x10264, RK_GENMASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */
69 MR_TOPGRF(RK_GPIO4, RK_PA0, 4, 0x10264, RK_GENMASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */
70
71 MR_TOPGRF(RK_GPIO2, RK_PA5, 7, 0x10264, RK_GENMASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */
72 MR_TOPGRF(RK_GPIO3, RK_PB0, 5, 0x10264, RK_GENMASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */
73 MR_TOPGRF(RK_GPIO1, RK_PD0, 4, 0x10264, RK_GENMASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */
74
75 MR_TOPGRF(RK_GPIO3, RK_PC0, 5, 0x10264, RK_GENMASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */
76 MR_TOPGRF(RK_GPIO1, RK_PC6, 3, 0x10264, RK_GENMASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */
77 MR_TOPGRF(RK_GPIO2, RK_PD5, 6, 0x10264, RK_GENMASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */
78
79 MR_TOPGRF(RK_GPIO3, RK_PC0, 2, 0x10264, RK_GENMASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */
80 MR_TOPGRF(RK_GPIO2, RK_PB7, 2, 0x10264, RK_GENMASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */
81
82 MR_TOPGRF(RK_GPIO3, RK_PA1, 3, 0x10264, RK_GENMASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */
83 MR_TOPGRF(RK_GPIO3, RK_PA7, 5, 0x10264, RK_GENMASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */
84
85 MR_TOPGRF(RK_GPIO3, RK_PA4, 6, 0x10268, RK_GENMASK_VAL(0, 0, 0)), /* PWM8_M0 */
86 MR_TOPGRF(RK_GPIO2, RK_PD7, 5, 0x10268, RK_GENMASK_VAL(0, 0, 1)), /* PWM8_M1 */
87
88 MR_TOPGRF(RK_GPIO3, RK_PA5, 6, 0x10268, RK_GENMASK_VAL(2, 2, 0)), /* PWM9_M0 */
89 MR_TOPGRF(RK_GPIO2, RK_PD6, 5, 0x10268, RK_GENMASK_VAL(2, 2, 1)), /* PWM9_M1 */
90
91 MR_TOPGRF(RK_GPIO3, RK_PA6, 6, 0x10268, RK_GENMASK_VAL(4, 4, 0)), /* PWM10_M0 */
92 MR_TOPGRF(RK_GPIO2, RK_PD5, 5, 0x10268, RK_GENMASK_VAL(4, 4, 1)), /* PWM10_M1 */
93
94 MR_TOPGRF(RK_GPIO3, RK_PA7, 6, 0x10268, RK_GENMASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */
95 MR_TOPGRF(RK_GPIO3, RK_PA1, 5, 0x10268, RK_GENMASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */
96
97 MR_TOPGRF(RK_GPIO1, RK_PA5, 3, 0x10268, RK_GENMASK_VAL(8, 8, 0)), /* UART2_TX_M0 */
98 MR_TOPGRF(RK_GPIO3, RK_PA2, 1, 0x10268, RK_GENMASK_VAL(8, 8, 1)), /* UART2_TX_M1 */
99
100 MR_TOPGRF(RK_GPIO3, RK_PC6, 3, 0x10268, RK_GENMASK_VAL(11, 10, 0)), /* UART3_TX_M0 */
101 MR_TOPGRF(RK_GPIO1, RK_PA7, 2, 0x10268, RK_GENMASK_VAL(11, 10, 1)), /* UART3_TX_M1 */
102 MR_TOPGRF(RK_GPIO3, RK_PA0, 4, 0x10268, RK_GENMASK_VAL(11, 10, 2)), /* UART3_TX_M2 */
103
104 MR_TOPGRF(RK_GPIO3, RK_PA4, 4, 0x10268, RK_GENMASK_VAL(13, 12, 0)), /* UART4_TX_M0 */
105 MR_TOPGRF(RK_GPIO2, RK_PA6, 4, 0x10268, RK_GENMASK_VAL(13, 12, 1)), /* UART4_TX_M1 */
106 MR_TOPGRF(RK_GPIO1, RK_PD5, 3, 0x10268, RK_GENMASK_VAL(13, 12, 2)), /* UART4_TX_M2 */
107
108 MR_TOPGRF(RK_GPIO3, RK_PA6, 4, 0x10268, RK_GENMASK_VAL(15, 14, 0)), /* UART5_TX_M0 */
109 MR_TOPGRF(RK_GPIO2, RK_PB0, 4, 0x10268, RK_GENMASK_VAL(15, 14, 1)), /* UART5_TX_M1 */
110 MR_TOPGRF(RK_GPIO2, RK_PA0, 3, 0x10268, RK_GENMASK_VAL(15, 14, 2)), /* UART5_TX_M2 */
111
112 MR_PMUGRF(RK_GPIO0, RK_PB6, 3, 0x0114, RK_GENMASK_VAL(0, 0, 0)), /* PWM0_M0 */
113 MR_PMUGRF(RK_GPIO2, RK_PB3, 5, 0x0114, RK_GENMASK_VAL(0, 0, 1)), /* PWM0_M1 */
114
115 MR_PMUGRF(RK_GPIO0, RK_PB7, 3, 0x0114, RK_GENMASK_VAL(2, 2, 0)), /* PWM1_M0 */
116 MR_PMUGRF(RK_GPIO2, RK_PB2, 5, 0x0114, RK_GENMASK_VAL(2, 2, 1)), /* PWM1_M1 */
117
118 MR_PMUGRF(RK_GPIO0, RK_PC0, 3, 0x0114, RK_GENMASK_VAL(4, 4, 0)), /* PWM2_M0 */
119 MR_PMUGRF(RK_GPIO2, RK_PB1, 5, 0x0114, RK_GENMASK_VAL(4, 4, 1)), /* PWM2_M1 */
120
121 MR_PMUGRF(RK_GPIO0, RK_PC1, 3, 0x0114, RK_GENMASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */
122 MR_PMUGRF(RK_GPIO2, RK_PB0, 5, 0x0114, RK_GENMASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */
123
124 MR_PMUGRF(RK_GPIO0, RK_PC2, 3, 0x0114, RK_GENMASK_VAL(8, 8, 0)), /* PWM4_M0 */
125 MR_PMUGRF(RK_GPIO2, RK_PA7, 5, 0x0114, RK_GENMASK_VAL(8, 8, 1)), /* PWM4_M1 */
126
127 MR_PMUGRF(RK_GPIO0, RK_PC3, 3, 0x0114, RK_GENMASK_VAL(10, 10, 0)), /* PWM5_M0 */
128 MR_PMUGRF(RK_GPIO2, RK_PA6, 5, 0x0114, RK_GENMASK_VAL(10, 10, 1)), /* PWM5_M1 */
129
130 MR_PMUGRF(RK_GPIO0, RK_PB2, 3, 0x0114, RK_GENMASK_VAL(12, 12, 0)), /* PWM6_M0 */
131 MR_PMUGRF(RK_GPIO2, RK_PD4, 5, 0x0114, RK_GENMASK_VAL(12, 12, 1)), /* PWM6_M1 */
132
133 MR_PMUGRF(RK_GPIO0, RK_PB1, 3, 0x0114, RK_GENMASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */
134 MR_PMUGRF(RK_GPIO3, RK_PA0, 5, 0x0114, RK_GENMASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */
135
136 MR_PMUGRF(RK_GPIO0, RK_PB0, 1, 0x0118, RK_GENMASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */
137 MR_PMUGRF(RK_GPIO2, RK_PA1, 1, 0x0118, RK_GENMASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */
138 MR_PMUGRF(RK_GPIO2, RK_PB2, 6, 0x0118, RK_GENMASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */
139
140 MR_PMUGRF(RK_GPIO0, RK_PB6, 2, 0x0118, RK_GENMASK_VAL(2, 2, 0)), /* UART1_TX_M0 */
141 MR_PMUGRF(RK_GPIO1, RK_PD0, 5, 0x0118, RK_GENMASK_VAL(2, 2, 1)), /* UART1_TX_M1 */
142 MR_PMUGRF(RK_GPIO0, RK_PC3, 1, 0x0118, RK_GENMASK_VAL(4, 4, 1)), /* I2C2 */
143};
144
145static int rv1126_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
146{
147 struct rockchip_pinctrl_priv *priv = bank->priv;
148 int iomux_num = (pin / 8);
149 struct regmap *regmap;
150 int reg, ret, mask, mux_type;
151 u8 bit;
152 u32 data;
153
154 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
155
156 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
157 regmap = priv->regmap_pmu;
158 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
159 regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base;
160 else
161 regmap = priv->regmap_base;
162
163 /* get basic quadrupel of mux registers and the correct reg inside */
164 mux_type = bank->iomux[iomux_num].type;
165 reg = bank->iomux[iomux_num].offset;
166 if (mux_type & IOMUX_WIDTH_4BIT) {
167 if ((pin % 8) >= 4)
168 reg += 0x4;
169 bit = (pin % 4) * 4;
170 mask = 0xf;
171 } else {
172 bit = (pin % 8) * 2;
173 mask = 0x3;
174 }
175
176 if (bank->recalced_mask & BIT(pin))
177 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
178
179 data = (mask << (bit + 16));
180 data |= (mux & mask) << bit;
181 ret = regmap_write(regmap, reg, data);
182
183 return ret;
184}
185
186#define RV1126_PULL_PMU_OFFSET 0x40
187#define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108
188#define RV1126_PULL_PINS_PER_REG 8
189#define RV1126_PULL_BITS_PER_PIN 2
190#define RV1126_PULL_BANK_STRIDE 16
191#define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */
192
193static void rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
194 int pin_num, struct regmap **regmap,
195 int *reg, u8 *bit)
196{
197 struct rockchip_pinctrl_priv *priv = bank->priv;
198
199 /* The first 24 pins of the first bank are located in PMU */
200 if (bank->bank_num == 0) {
201 if (RV1126_GPIO_C4_D7(pin_num)) {
202 *regmap = priv->regmap_base;
203 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
204 *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4);
205 *bit = pin_num % RV1126_PULL_PINS_PER_REG;
206 *bit *= RV1126_PULL_BITS_PER_PIN;
207 return;
208 }
209 *regmap = priv->regmap_pmu;
210 *reg = RV1126_PULL_PMU_OFFSET;
211 } else {
212 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
213 *regmap = priv->regmap_base;
214 *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE;
215 }
216
217 *reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4);
218 *bit = (pin_num % RV1126_PULL_PINS_PER_REG);
219 *bit *= RV1126_PULL_BITS_PER_PIN;
220}
221
222static int rv1126_set_pull(struct rockchip_pin_bank *bank,
223 int pin_num, int pull)
224{
225 struct regmap *regmap;
226 int reg, ret;
227 u8 bit, type;
228 u32 data;
229
230 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
231 return -EOPNOTSUPP;
232
233 rv1126_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
234 type = bank->pull_type[pin_num / 8];
235 ret = rockchip_translate_pull_value(type, pull);
236 if (ret < 0) {
237 debug("unsupported pull setting %d\n", pull);
238 return ret;
239 }
240
241 /* enable the write to the equivalent lower bits */
242 data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
243
244 data |= (ret << bit);
245 ret = regmap_write(regmap, reg, data);
246
247 return ret;
248}
249
250#define RV1126_DRV_PMU_OFFSET 0x20
251#define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090
252#define RV1126_DRV_BITS_PER_PIN 4
253#define RV1126_DRV_PINS_PER_REG 4
254#define RV1126_DRV_BANK_STRIDE 32
255
256static void rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
257 int pin_num, struct regmap **regmap,
258 int *reg, u8 *bit)
259{
260 struct rockchip_pinctrl_priv *priv = bank->priv;
261
262 /* The first 24 pins of the first bank are located in PMU */
263 if (bank->bank_num == 0) {
264 if (RV1126_GPIO_C4_D7(pin_num)) {
265 *regmap = priv->regmap_base;
266 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
267 *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4);
268 *reg -= 0x4;
269 *bit = pin_num % RV1126_DRV_PINS_PER_REG;
270 *bit *= RV1126_DRV_BITS_PER_PIN;
271 return;
272 }
273 *regmap = priv->regmap_pmu;
274 *reg = RV1126_DRV_PMU_OFFSET;
275 } else {
276 *regmap = priv->regmap_base;
277 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
278 *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE;
279 }
280
281 *reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4);
282 *bit = pin_num % RV1126_DRV_PINS_PER_REG;
283 *bit *= RV1126_DRV_BITS_PER_PIN;
284}
285
286static int rv1126_set_drive(struct rockchip_pin_bank *bank,
287 int pin_num, int strength)
288{
289 struct regmap *regmap;
290 int reg;
291 u32 data;
292 u8 bit;
293
294 rv1126_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
295
296 /* enable the write to the equivalent lower bits */
297 data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
298 data |= (strength << bit);
299
300 return regmap_write(regmap, reg, data);
301}
302
303#define RV1126_SCHMITT_PMU_OFFSET 0x60
304#define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188
305#define RV1126_SCHMITT_BANK_STRIDE 16
306#define RV1126_SCHMITT_PINS_PER_GRF_REG 8
307#define RV1126_SCHMITT_PINS_PER_PMU_REG 8
308
309static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
310 int pin_num,
311 struct regmap **regmap,
312 int *reg, u8 *bit)
313{
314 struct rockchip_pinctrl_priv *priv = bank->priv;
315 int pins_per_reg;
316
317 if (bank->bank_num == 0) {
318 if (RV1126_GPIO_C4_D7(pin_num)) {
319 *regmap = priv->regmap_base;
320 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
321 *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4);
322 *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG;
323 return 0;
324 }
325 *regmap = priv->regmap_pmu;
326 *reg = RV1126_SCHMITT_PMU_OFFSET;
327 pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG;
328 } else {
329 *regmap = priv->regmap_base;
330 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
331 pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG;
332 *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE;
333 }
334 *reg += ((pin_num / pins_per_reg) * 4);
335 *bit = pin_num % pins_per_reg;
336
337 return 0;
338}
339
340static int rv1126_set_schmitt(struct rockchip_pin_bank *bank,
341 int pin_num, int enable)
342{
343 struct regmap *regmap;
344 int reg;
345 u8 bit;
346 u32 data;
347
348 rv1126_calc_schmitt_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
349 /* enable the write to the equivalent lower bits */
350 data = BIT(bit + 16) | (enable << bit);
351
352 return regmap_write(regmap, reg, data);
353}
354
355static struct rockchip_pin_bank rv1126_pin_banks[] = {
356 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
357 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
358 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
359 IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU,
360 IOMUX_WIDTH_4BIT),
361 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
362 IOMUX_WIDTH_4BIT,
363 IOMUX_WIDTH_4BIT,
364 IOMUX_WIDTH_4BIT,
365 IOMUX_WIDTH_4BIT,
366 0x10010, 0x10018, 0x10020, 0x10028),
367 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2",
368 IOMUX_WIDTH_4BIT,
369 IOMUX_WIDTH_4BIT,
370 IOMUX_WIDTH_4BIT,
371 IOMUX_WIDTH_4BIT),
372 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
373 IOMUX_WIDTH_4BIT,
374 IOMUX_WIDTH_4BIT,
375 IOMUX_WIDTH_4BIT,
376 IOMUX_WIDTH_4BIT),
377 PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4",
378 IOMUX_WIDTH_4BIT, 0, 0, 0),
379};
380
381static const struct rockchip_pin_ctrl rv1126_pin_ctrl = {
382 .pin_banks = rv1126_pin_banks,
383 .nr_banks = ARRAY_SIZE(rv1126_pin_banks),
384 .nr_pins = 130,
385 .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */
386 .pmu_mux_offset = 0x0,
387 .iomux_routes = rv1126_mux_route_data,
388 .niomux_routes = ARRAY_SIZE(rv1126_mux_route_data),
389 .iomux_recalced = rv1126_mux_recalced_data,
390 .niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data),
391 .set_mux = rv1126_set_mux,
392 .set_pull = rv1126_set_pull,
393 .set_drive = rv1126_set_drive,
394 .set_schmitt = rv1126_set_schmitt,
395};
396
397static const struct udevice_id rv1126_pinctrl_ids[] = {
398 {
399 .compatible = "rockchip,rv1126-pinctrl",
400 .data = (ulong)&rv1126_pin_ctrl
401 },
402 { }
403};
404
405U_BOOT_DRIVER(pinctrl_rv1126) = {
406 .name = "rockchip_rv1126_pinctrl",
407 .id = UCLASS_PINCTRL,
408 .of_match = rv1126_pinctrl_ids,
409 .priv_auto = sizeof(struct rockchip_pinctrl_priv),
410 .ops = &rockchip_pinctrl_ops,
411#if !CONFIG_IS_ENABLED(OF_PLATDATA)
412 .bind = dm_scan_fdt_dev,
413#endif
414 .probe = rockchip_pinctrl_probe,
415};