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git01.mediatek.com / filogic / uboot / 591a9634501eb27f32087018e815e11160a81133 / . / drivers / clk / imx / clk-imx8mq.c
blob: ed4acd79ef741d63035907ef7820747a696d27f8 [file] [log] [blame]
Angus Ainslie7ab22a82022-03-29 07:02:39 -0700[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2019 NXP
4 * Copyright 2022 Purism
5 * Peng Fan <peng.fan@nxp.com>
6 */
7
Angus Ainslie7ab22a82022-03-29 07:02:39 -0700[diff] [blame]8#include <clk.h>
9#include <clk-uclass.h>
10#include <dm.h>
11#include <log.h>
12#include <asm/arch/clock.h>
13#include <asm/arch/imx-regs.h>
14#include <dt-bindings/clock/imx8mq-clock.h>
15
16#include "clk.h"
17
Angus Ainslie7ab22a82022-03-29 07:02:39 -0700[diff] [blame]18static const char *const pll_ref_sels[] = { "clock-osc-25m", "clock-osc-27m", "clock-phy-27m", "dummy", };
19static const char *const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
20static const char *const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
21static const char *const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
22static const char *const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
23static const char *const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
24static const char *const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
25
26static const char *const imx8mq_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", };
27static const char *const imx8mq_a53_sels[] = {"clock-osc-25m", "arm_pll_out", "sys_pll2_500m",
28 "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
29 "audio_pll1_out", "sys_pll3_out", };
30
31static const char *const imx8mq_ahb_sels[] = {"clock-osc-25m", "sys_pll1_133m", "sys_pll1_800m",
32 "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
33 "audio_pll1_out", "video_pll1_out", };
34
35static const char *const imx8mq_dram_alt_sels[] = {"osc_25m", "sys_pll1_800m", "sys_pll1_100m",
36 "sys_pll2_500m", "sys_pll2_250m",
37 "sys_pll1_400m", "audio_pll1_out", "sys_pll1_266m", } ;
38
39static const char * const imx8mq_dram_apb_sels[] = {"osc_25m", "sys_pll2_200m", "sys_pll1_40m",
40 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
41 "sys_pll2_250m", "audio_pll2_out", };
42
43static const char *const imx8mq_enet_axi_sels[] = {"clock-osc-25m", "sys_pll1_266m", "sys_pll1_800m",
44 "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
45 "video_pll1_out", "sys_pll3_out", };
46
47static const char *const imx8mq_enet_ref_sels[] = {"clock-osc-25m", "sys_pll2_125m", "sys_pll2_50m",
48 "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
49 "video_pll1_out", "clk_ext4", };
50
51static const char *const imx8mq_enet_timer_sels[] = {"clock-osc-25m", "sys_pll2_100m", "audio_pll1_out",
52 "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4",
53 "video_pll1_out", };
54
55static const char *const imx8mq_enet_phy_sels[] = {"clock-osc-25m", "sys_pll2_50m", "sys_pll2_125m",
56 "sys_pll2_200m", "sys_pll2_500m", "video_pll1_out",
57 "audio_pll2_out", };
58
59static const char *const imx8mq_nand_usdhc_sels[] = {"clock-osc-25m", "sys_pll1_266m", "sys_pll1_800m",
60 "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
61 "sys_pll2_250m", "audio_pll1_out", };
62
63static const char *const imx8mq_usb_bus_sels[] = {"clock-osc-25m", "sys_pll2_500m", "sys_pll1_800m",
64 "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
65 "clk_ext4", "audio_pll2_out", };
66
67static const char *const imx8mq_usdhc1_sels[] = {"clock-osc-25m", "sys_pll1_400m", "sys_pll1_800m",
68 "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
69 "audio_pll2_out", "sys_pll1_100m", };
70
71static const char *const imx8mq_usdhc2_sels[] = {"clock-osc-25m", "sys_pll1_400m", "sys_pll1_800m",
72 "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
73 "audio_pll2_out", "sys_pll1_100m", };
74
75static const char *const imx8mq_i2c1_sels[] = {"clock-osc-25m", "sys_pll1_160m", "sys_pll2_50m",
76 "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
77 "audio_pll2_out", "sys_pll1_133m", };
78
79static const char *const imx8mq_i2c2_sels[] = {"clock-osc-25m", "sys_pll1_160m", "sys_pll2_50m",
80 "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
81 "audio_pll2_out", "sys_pll1_133m", };
82
83static const char *const imx8mq_i2c3_sels[] = {"clock-osc-25m", "sys_pll1_160m", "sys_pll2_50m",
84 "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
85 "audio_pll2_out", "sys_pll1_133m", };
86
87static const char *const imx8mq_i2c4_sels[] = {"clock-osc-25m", "sys_pll1_160m", "sys_pll2_50m",
88 "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
89 "audio_pll2_out", "sys_pll1_133m", };
90
91static const char *const imx8mq_uart1_sels[] = {"clock-osc-25m", "sys_pll1_80m", "sys_pll2_200m",
92 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
93 "clk_ext4", "audio_pll2_out", };
94
95static const char *const imx8mq_uart2_sels[] = {"clock-osc-25m", "sys_pll1_80m", "sys_pll2_200m",
96 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
97 "clk_ext3", "audio_pll2_out", };
98
99static const char *const imx8mq_uart3_sels[] = {"clock-osc-25m", "sys_pll1_80m", "sys_pll2_200m",
100 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
101 "clk_ext4", "audio_pll2_out", };
102
103static const char *const imx8mq_uart4_sels[] = {"clock-osc-25m", "sys_pll1_80m", "sys_pll2_200m",
104 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
105 "clk_ext3", "audio_pll2_out", };
106
107static const char *const imx8mq_wdog_sels[] = {"clock-osc-25m", "sys_pll1_133m", "sys_pll1_160m",
108 "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out",
109 "sys_pll1_80m", "sys_pll2_166m", };
110
111static const char *const imx8mq_qspi_sels[] = {"clock-osc-25m", "sys_pll1_400m", "sys_pll2_333m",
112 "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m",
113 "sys_pll3_out", "sys_pll1_100m", };
114
115static const char *const imx8mq_usb_core_sels[] = {"clock-osc-25m", "sys_pll1_100m", "sys_pll1_40m",
116 "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
117 "clk_ext3", "audio_pll2_out", };
118
119static const char *const imx8mq_usb_phy_sels[] = {"clock-osc-25m", "sys_pll1_100m", "sys_pll1_40m",
120 "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
121 "clk_ext3", "audio_pll2_out", };
122
123static const char *const imx8mq_ecspi1_sels[] = {"clock-osc-25m", "sys_pll2_200m", "sys_pll1_40m",
124 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
125 "sys_pll2_250m", "audio_pll2_out", };
126
127static const char *const imx8mq_ecspi2_sels[] = {"clock-osc-25m", "sys_pll2_200m", "sys_pll1_40m",
128 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
129 "sys_pll2_250m", "audio_pll2_out", };
130
131static const char *const imx8mq_ecspi3_sels[] = {"clock-osc-25m", "sys_pll2_200m", "sys_pll1_40m",
132 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
133 "sys_pll2_250m", "audio_pll2_out", };
134
135static const char *const imx8mq_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
136
137static const char *const pllout_monitor_sels[] = {"clock-osc-25m", "clock-osc-27m", "clock-phy-27m",
138 "dummy", "clock-ckil", "audio_pll1_out_monitor",
139 "audio_pll2_out_monitor", "gpu_pll_out_monitor",
140 "vpu_pll_out_monitor", "video_pll1_out_monitor",
141 "arm_pll_out_monitor", "sys_pll1_out_monitor",
142 "sys_pll2_out_monitor", "sys_pll3_out_monitor",
143 "video_pll2_out_monitor", "dram_pll_out_monitor", };
144
145static int imx8mq_clk_probe(struct udevice *dev)
146{
147 void __iomem *base;
148
149 base = (void *)ANATOP_BASE_ADDR;
150
151 clk_dm(IMX8MQ_CLK_32K, clk_register_fixed_rate(NULL, "ckil", 32768));
152 clk_dm(IMX8MQ_CLK_27M, clk_register_fixed_rate(NULL, "clock-osc-27m", 27000000));
153
154 clk_dm(IMX8MQ_DRAM_PLL1_REF_SEL,
155 imx_clk_mux("dram_pll_ref_sel", base + 0x60, 0, 2,
156 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
157 clk_dm(IMX8MQ_ARM_PLL_REF_SEL,
158 imx_clk_mux("arm_pll_ref_sel", base + 0x28, 0, 2,
159 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
160 clk_dm(IMX8MQ_GPU_PLL_REF_SEL,
161 imx_clk_mux("gpu_pll_ref_sel", base + 0x18, 0, 2,
162 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
163 clk_dm(IMX8MQ_VPU_PLL_REF_SEL,
164 imx_clk_mux("vpu_pll_ref_sel", base + 0x20, 0, 2,
165 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
166 clk_dm(IMX8MQ_SYS3_PLL1_REF_SEL,
167 imx_clk_mux("sys3_pll_ref_sel", base + 0x48, 0, 2,
168 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
169 clk_dm(IMX8MQ_AUDIO_PLL1_REF_SEL,
170 imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 0, 2,
171 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
172 clk_dm(IMX8MQ_AUDIO_PLL2_REF_SEL,
173 imx_clk_mux("audio_pll2_ref_sel", base + 0x8, 0, 2,
174 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
175 clk_dm(IMX8MQ_VIDEO_PLL1_REF_SEL,
176 imx_clk_mux("video_pll1_ref_sel", base + 0x10, 0, 2,
177 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
178 clk_dm(IMX8MQ_VIDEO2_PLL1_REF_SEL,
179 imx_clk_mux("video_pll2_ref_sel", base + 0x54, 0, 2,
180 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
181
182 clk_dm(IMX8MQ_ARM_PLL,
183 imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
Angus Ainslie73d75ec2022-03-29 07:02:40 -0700[diff] [blame]184 base + 0x28, &imx_1416x_pll));
Angus Ainslie7ab22a82022-03-29 07:02:39 -0700[diff] [blame]185 clk_dm(IMX8MQ_GPU_PLL,
186 imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel",
Angus Ainslie73d75ec2022-03-29 07:02:40 -0700[diff] [blame]187 base + 0x18, &imx_1416x_pll));
Angus Ainslie7ab22a82022-03-29 07:02:39 -0700[diff] [blame]188 clk_dm(IMX8MQ_VPU_PLL,
189 imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel",
Angus Ainslie73d75ec2022-03-29 07:02:40 -0700[diff] [blame]190 base + 0x20, &imx_1416x_pll));
Angus Ainslie7ab22a82022-03-29 07:02:39 -0700[diff] [blame]191
192 clk_dm(IMX8MQ_SYS1_PLL1,
193 clk_register_fixed_rate(NULL, "sys1_pll", 800000000));
194 clk_dm(IMX8MQ_SYS2_PLL1,
195 clk_register_fixed_rate(NULL, "sys2_pll", 1000000000));
196 clk_dm(IMX8MQ_SYS2_PLL1,
197 clk_register_fixed_rate(NULL, "sys3_pll", 1000000000));
198 clk_dm(IMX8MQ_AUDIO_PLL1,
199 imx_clk_pll14xx("audio_pll1", "audio_pll1_ref_sel",
Angus Ainslie73d75ec2022-03-29 07:02:40 -0700[diff] [blame]200 base + 0x0, &imx_1443x_pll));
Angus Ainslie7ab22a82022-03-29 07:02:39 -0700[diff] [blame]201 clk_dm(IMX8MQ_AUDIO_PLL2,
202 imx_clk_pll14xx("audio_pll2", "audio_pll2_ref_sel",
Angus Ainslie73d75ec2022-03-29 07:02:40 -0700[diff] [blame]203 base + 0x8, &imx_1443x_pll));
Angus Ainslie7ab22a82022-03-29 07:02:39 -0700[diff] [blame]204 clk_dm(IMX8MQ_VIDEO_PLL1,
205 imx_clk_pll14xx("video_pll1", "video_pll1_ref_sel",
Angus Ainslie73d75ec2022-03-29 07:02:40 -0700[diff] [blame]206 base + 0x10, &imx_1443x_pll));
Angus Ainslie7ab22a82022-03-29 07:02:39 -0700[diff] [blame]207
208 /* PLL bypass out */
209 clk_dm(IMX8MQ_ARM_PLL_BYPASS,
210 imx_clk_mux_flags("arm_pll_bypass", base + 0x28, 4, 1,
211 arm_pll_bypass_sels,
212 ARRAY_SIZE(arm_pll_bypass_sels),
213 CLK_SET_RATE_PARENT));
214 clk_dm(IMX8MQ_GPU_PLL_BYPASS,
215 imx_clk_mux_flags("gpu_pll_bypass", base + 0x18, 4, 1,
216 gpu_pll_bypass_sels,
217 ARRAY_SIZE(gpu_pll_bypass_sels),
218 CLK_SET_RATE_PARENT));
219 clk_dm(IMX8MQ_VPU_PLL_BYPASS,
220 imx_clk_mux_flags("vpu_pll_bypass", base + 0x20, 4, 1,
221 vpu_pll_bypass_sels,
222 ARRAY_SIZE(vpu_pll_bypass_sels),
223 CLK_SET_RATE_PARENT));
224 clk_dm(IMX8MQ_AUDIO_PLL1_BYPASS,
225 imx_clk_mux_flags("audio_pll1_bypass", base + 0x0, 4, 1,
226 audio_pll1_bypass_sels,
227 ARRAY_SIZE(audio_pll1_bypass_sels),
228 CLK_SET_RATE_PARENT));
229 clk_dm(IMX8MQ_AUDIO_PLL2_BYPASS,
230 imx_clk_mux_flags("audio_pll2_bypass", base + 0x8, 4, 1,
231 audio_pll2_bypass_sels,
232 ARRAY_SIZE(audio_pll2_bypass_sels),
233 CLK_SET_RATE_PARENT));
234 clk_dm(IMX8MQ_VIDEO_PLL1_BYPASS,
235 imx_clk_mux_flags("video_pll1_bypass", base + 0x10, 4, 1,
236 video_pll1_bypass_sels,
237 ARRAY_SIZE(video_pll1_bypass_sels),
238 CLK_SET_RATE_PARENT));
239
240 /* PLL out gate */
241 clk_dm(IMX8MQ_DRAM_PLL_OUT,
242 imx_clk_gate("dram_pll_out", "dram_pll_ref_sel",
243 base + 0x60, 13));
244 clk_dm(IMX8MQ_ARM_PLL_OUT,
245 imx_clk_gate("arm_pll_out", "arm_pll_bypass",
246 base + 0x28, 11));
247 clk_dm(IMX8MQ_GPU_PLL_OUT,
248 imx_clk_gate("gpu_pll_out", "gpu_pll_bypass",
249 base + 0x18, 11));
250 clk_dm(IMX8MQ_VPU_PLL_OUT,
251 imx_clk_gate("vpu_pll_out", "vpu_pll_bypass",
252 base + 0x20, 11));
253 clk_dm(IMX8MQ_AUDIO_PLL1_OUT,
254 imx_clk_gate("audio_pll1_out", "audio_pll1_bypass",
255 base + 0x0, 11));
256 clk_dm(IMX8MQ_AUDIO_PLL2_OUT,
257 imx_clk_gate("audio_pll2_out", "audio_pll2_bypass",
258 base + 0x8, 11));
259 clk_dm(IMX8MQ_VIDEO_PLL1_OUT,
260 imx_clk_gate("video_pll1_out", "video_pll1_bypass",
261 base + 0x10, 11));
262
263 clk_dm(IMX8MQ_SYS1_PLL_OUT,
264 imx_clk_gate("sys_pll1_out", "sys1_pll",
265 base + 0x30, 11));
266 clk_dm(IMX8MQ_SYS2_PLL_OUT,
267 imx_clk_gate("sys_pll2_out", "sys2_pll",
268 base + 0x3c, 11));
269 clk_dm(IMX8MQ_SYS3_PLL_OUT,
270 imx_clk_gate("sys_pll3_out", "sys3_pll",
271 base + 0x48, 11));
272 clk_dm(IMX8MQ_VIDEO2_PLL_OUT,
273 imx_clk_gate("video_pll2_out", "video_pll2_ref_sel",
274 base + 0x54, 11));
275
276 /* SYS PLL fixed output */
277 clk_dm(IMX8MQ_SYS1_PLL_40M,
278 imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
279 clk_dm(IMX8MQ_SYS1_PLL_80M,
280 imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
281 clk_dm(IMX8MQ_SYS1_PLL_100M,
282 imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
283 clk_dm(IMX8MQ_SYS1_PLL_133M,
284 imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
285 clk_dm(IMX8MQ_SYS1_PLL_160M,
286 imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
287 clk_dm(IMX8MQ_SYS1_PLL_200M,
288 imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
289 clk_dm(IMX8MQ_SYS1_PLL_266M,
290 imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
291 clk_dm(IMX8MQ_SYS1_PLL_400M,
292 imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
293 clk_dm(IMX8MQ_SYS1_PLL_800M,
294 imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
295
296 clk_dm(IMX8MQ_SYS2_PLL_50M,
297 imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
298 clk_dm(IMX8MQ_SYS2_PLL_100M,
299 imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
300 clk_dm(IMX8MQ_SYS2_PLL_125M,
301 imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
302 clk_dm(IMX8MQ_SYS2_PLL_166M,
303 imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
304 clk_dm(IMX8MQ_SYS2_PLL_200M,
305 imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
306 clk_dm(IMX8MQ_SYS2_PLL_250M,
307 imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
308 clk_dm(IMX8MQ_SYS2_PLL_333M,
309 imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
310 clk_dm(IMX8MQ_SYS2_PLL_500M,
311 imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
312 clk_dm(IMX8MQ_SYS2_PLL_1000M,
313 imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
314
315 clk_dm(IMX8MQ_CLK_MON_AUDIO_PLL1_DIV,
316 imx_clk_divider("audio_pll1_out_monitor", "audio_pll1_bypass", base + 0x78, 0, 3));
317 clk_dm(IMX8MQ_CLK_MON_AUDIO_PLL2_DIV,
318 imx_clk_divider("audio_pll2_out_monitor", "audio_pll2_bypass", base + 0x78, 4, 3));
319 clk_dm(IMX8MQ_CLK_MON_VIDEO_PLL1_DIV,
320 imx_clk_divider("video_pll1_out_monitor", "video_pll1_bypass", base + 0x78, 8, 3));
321 clk_dm(IMX8MQ_CLK_MON_GPU_PLL_DIV,
322 imx_clk_divider("gpu_pll_out_monitor", "gpu_pll_bypass", base + 0x78, 12, 3));
323 clk_dm(IMX8MQ_CLK_MON_VPU_PLL_DIV,
324 imx_clk_divider("vpu_pll_out_monitor", "vpu_pll_bypass", base + 0x78, 16, 3));
325 clk_dm(IMX8MQ_CLK_MON_ARM_PLL_DIV,
326 imx_clk_divider("arm_pll_out_monitor", "arm_pll_bypass", base + 0x78, 20, 3));
327 clk_dm(IMX8MQ_CLK_MON_SYS_PLL1_DIV,
328 imx_clk_divider("sys_pll1_out_monitor", "sys_pll1_out", base + 0x7c, 0, 3));
329 clk_dm(IMX8MQ_CLK_MON_SYS_PLL2_DIV,
330 imx_clk_divider("sys_pll2_out_monitor", "sys_pll2_out", base + 0x7c, 4, 3));
331 clk_dm(IMX8MQ_CLK_MON_SYS_PLL3_DIV,
332 imx_clk_divider("sys_pll3_out_monitor", "sys_pll3_out", base + 0x7c, 8, 3));
333 clk_dm(IMX8MQ_CLK_MON_DRAM_PLL_DIV,
334 imx_clk_divider("dram_pll_out_monitor", "dram_pll_out", base + 0x7c, 12, 3));
335 clk_dm(IMX8MQ_CLK_MON_VIDEO_PLL2_DIV,
336 imx_clk_divider("video_pll2_out_monitor", "video_pll2_out", base + 0x7c, 16, 3));
337 clk_dm(IMX8MQ_CLK_MON_SEL,
338 imx_clk_mux_flags("pllout_monitor_sel", base + 0x74, 0, 4,
339 pllout_monitor_sels,
340 ARRAY_SIZE(pllout_monitor_sels),
341 CLK_SET_RATE_PARENT));
342 clk_dm(IMX8MQ_CLK_MON_CLK2_OUT,
343 imx_clk_gate4("pllout_monitor_clk2", "pllout_monitor_sel", base + 0x74, 4));
344
345 base = dev_read_addr_ptr(dev);
346 if (!base) {
347 printf("%s : base failed\n", __func__);
348 return -EINVAL;
349 }
350
351 clk_dm(IMX8MQ_CLK_A53_SRC,
352 imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
353 imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels)));
354 clk_dm(IMX8MQ_CLK_A53_CG,
355 imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
356 clk_dm(IMX8MQ_CLK_A53_DIV,
357 imx_clk_divider2("arm_a53_div", "arm_a53_cg",
358 base + 0x8000, 0, 3));
359 clk_dm(IMX8MQ_CLK_A53_CORE,
360 imx_clk_mux2("arm_a53_src", base + 0x9880, 24, 1,
361 imx8mq_a53_core_sels, ARRAY_SIZE(imx8mq_a53_core_sels)));
362
363 clk_dm(IMX8MQ_CLK_AHB,
364 imx8m_clk_composite_critical("ahb", imx8mq_ahb_sels,
365 base + 0x9000));
366 clk_dm(IMX8MQ_CLK_IPG_ROOT,
367 imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
368
369 clk_dm(IMX8MQ_CLK_ENET_AXI,
370 imx8m_clk_composite("enet_axi", imx8mq_enet_axi_sels,
371 base + 0x8880));
372 clk_dm(IMX8MQ_CLK_NAND_USDHC_BUS,
373 imx8m_clk_composite_critical("nand_usdhc_bus",
374 imx8mq_nand_usdhc_sels,
375 base + 0x8900));
376 clk_dm(IMX8MQ_CLK_USB_BUS,
377 imx8m_clk_composite("usb_bus", imx8mq_usb_bus_sels, base + 0x8b80));
378
379 /* DRAM */
380 clk_dm(IMX8MQ_CLK_DRAM_CORE,
381 imx_clk_mux2("dram_core_clk", base + 0x9800, 24, 1,
382 imx8mq_dram_core_sels, ARRAY_SIZE(imx8mq_dram_core_sels)));
383 clk_dm(IMX8MQ_CLK_DRAM_ALT,
384 imx8m_clk_composite("dram_alt", imx8mq_dram_alt_sels, base + 0xa000));
385 clk_dm(IMX8MQ_CLK_DRAM_APB,
386 imx8m_clk_composite_critical("dram_apb", imx8mq_dram_apb_sels, base + 0xa080));
387
388 /* IP */
389 clk_dm(IMX8MQ_CLK_USDHC1,
390 imx8m_clk_composite("usdhc1", imx8mq_usdhc1_sels,
391 base + 0xac00));
392 clk_dm(IMX8MQ_CLK_USDHC2,
393 imx8m_clk_composite("usdhc2", imx8mq_usdhc2_sels,
394 base + 0xac80));
395 clk_dm(IMX8MQ_CLK_I2C1,
396 imx8m_clk_composite("i2c1", imx8mq_i2c1_sels, base + 0xad00));
397 clk_dm(IMX8MQ_CLK_I2C2,
398 imx8m_clk_composite("i2c2", imx8mq_i2c2_sels, base + 0xad80));
399 clk_dm(IMX8MQ_CLK_I2C3,
400 imx8m_clk_composite("i2c3", imx8mq_i2c3_sels, base + 0xae00));
401 clk_dm(IMX8MQ_CLK_I2C4,
402 imx8m_clk_composite("i2c4", imx8mq_i2c4_sels, base + 0xae80));
403 clk_dm(IMX8MQ_CLK_WDOG,
404 imx8m_clk_composite("wdog", imx8mq_wdog_sels, base + 0xb900));
405 clk_dm(IMX8MQ_CLK_UART1,
406 imx8m_clk_composite("uart1", imx8mq_uart1_sels, base + 0xaf00));
407 clk_dm(IMX8MQ_CLK_UART2,
408 imx8m_clk_composite("uart2", imx8mq_uart2_sels, base + 0xaf80));
409 clk_dm(IMX8MQ_CLK_UART3,
410 imx8m_clk_composite("uart3", imx8mq_uart3_sels, base + 0xb000));
411 clk_dm(IMX8MQ_CLK_UART4,
412 imx8m_clk_composite("uart4", imx8mq_uart4_sels, base + 0xb080));
413 clk_dm(IMX8MQ_CLK_QSPI,
414 imx8m_clk_composite("qspi", imx8mq_qspi_sels, base + 0xab80));
415 clk_dm(IMX8MQ_CLK_USB_CORE_REF,
416 imx8m_clk_composite("usb_core_ref", imx8mq_usb_core_sels, base + 0xb100));
417 clk_dm(IMX8MQ_CLK_USB_PHY_REF,
418 imx8m_clk_composite("usb_phy_ref", imx8mq_usb_phy_sels, base + 0xb180));
419 clk_dm(IMX8MQ_CLK_ECSPI1,
420 imx8m_clk_composite("ecspi1", imx8mq_ecspi1_sels, base + 0xb280));
421 clk_dm(IMX8MQ_CLK_ECSPI2,
422 imx8m_clk_composite("ecspi2", imx8mq_ecspi2_sels, base + 0xb300));
423 clk_dm(IMX8MQ_CLK_ECSPI3,
424 imx8m_clk_composite("ecspi3", imx8mq_ecspi3_sels, base + 0xc180));
425
426 clk_dm(IMX8MQ_CLK_ECSPI1_ROOT,
427 imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
428 clk_dm(IMX8MQ_CLK_ECSPI2_ROOT,
429 imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
430 clk_dm(IMX8MQ_CLK_ECSPI3_ROOT,
431 imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
432 clk_dm(IMX8MQ_CLK_I2C1_ROOT,
433 imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
434 clk_dm(IMX8MQ_CLK_I2C2_ROOT,
435 imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
436 clk_dm(IMX8MQ_CLK_I2C3_ROOT,
437 imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
438 clk_dm(IMX8MQ_CLK_I2C4_ROOT,
439 imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
440 clk_dm(IMX8MQ_CLK_UART1_ROOT,
441 imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0));
442 clk_dm(IMX8MQ_CLK_UART2_ROOT,
443 imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0));
444 clk_dm(IMX8MQ_CLK_UART3_ROOT,
445 imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0));
446 clk_dm(IMX8MQ_CLK_UART4_ROOT,
447 imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
448 clk_dm(IMX8MQ_CLK_OCOTP_ROOT,
449 imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
450 clk_dm(IMX8MQ_CLK_USDHC1_ROOT,
451 imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
452 clk_dm(IMX8MQ_CLK_USDHC2_ROOT,
453 imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
454 clk_dm(IMX8MQ_CLK_WDOG1_ROOT,
455 imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
456 clk_dm(IMX8MQ_CLK_WDOG2_ROOT,
457 imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
458 clk_dm(IMX8MQ_CLK_WDOG3_ROOT,
459 imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
460 clk_dm(IMX8MQ_CLK_QSPI_ROOT,
461 imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
462 clk_dm(IMX8MQ_CLK_USB1_CTRL_ROOT,
463 imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
464 clk_dm(IMX8MQ_CLK_USB2_CTRL_ROOT,
465 imx_clk_gate4("usb2_ctrl_root_clk", "usb_bus", base + 0x44e0, 0));
466 clk_dm(IMX8MQ_CLK_USB1_PHY_ROOT,
467 imx_clk_gate4("usb1_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
468 clk_dm(IMX8MQ_CLK_USB2_PHY_ROOT,
469 imx_clk_gate4("usb2_phy_root_clk", "usb_phy_ref", base + 0x4500, 0));
470
471 clk_dm(IMX8MQ_CLK_ENET_REF,
472 imx8m_clk_composite("enet_ref", imx8mq_enet_ref_sels,
473 base + 0xa980));
474 clk_dm(IMX8MQ_CLK_ENET_TIMER,
475 imx8m_clk_composite("enet_timer", imx8mq_enet_timer_sels,
476 base + 0xaa00));
477 clk_dm(IMX8MQ_CLK_ENET_PHY_REF,
478 imx8m_clk_composite("enet_phy", imx8mq_enet_phy_sels,
479 base + 0xaa80));
480 clk_dm(IMX8MQ_CLK_ENET1_ROOT,
481 imx_clk_gate4("enet1_root_clk", "enet_axi",
482 base + 0x40a0, 0));
483
484 clk_dm(IMX8MQ_CLK_DRAM_ALT_ROOT,
485 imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4));
486
487 return 0;
488}
489
490static const struct udevice_id imx8mq_clk_ids[] = {
491 { .compatible = "fsl,imx8mq-ccm" },
492 { },
493};
494
495U_BOOT_DRIVER(imx8mq_clk) = {
496 .name = "clk_imx8mq",
497 .id = UCLASS_CLK,
498 .of_match = imx8mq_clk_ids,
499 .ops = &ccf_clk_ops,
500 .probe = imx8mq_clk_probe,
501 .flags = DM_FLAG_PRE_RELOC,
502};