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wdenke97d3d92004-02-23 22:22:28 +00001/*
2 * (C) Copyright 2004
3 * Texas Instruments.
4 * Kshitij Gupta <kshitij@ti.com>
5 * Configuration settings for the TI OMAP 1610 H2 board.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/*
wdenke97d3d92004-02-23 22:22:28 +000030 * High Level Configuration Options
31 * (easy to change)
32 */
33#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
34#define CONFIG_OMAP 1 /* in a TI OMAP core */
35#define CONFIG_OMAP1610 1 /* which is in a 1610 */
36#define CONFIG_H2_OMAP1610 1 /* on an H2 Board */
wdenk82db02f2004-07-11 22:19:26 +000037#define CONFIG_MACH_OMAP_H2 /* Select board mach-type */
wdenke97d3d92004-02-23 22:22:28 +000038
39/* input clock of PLL */
40/* the OMAP1610 H2 has 12MHz input clock */
41#define CONFIG_SYS_CLK_FREQ 12000000
42
43#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
44
45#define CONFIG_MISC_INIT_R
46
47#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
48#define CONFIG_SETUP_MEMORY_TAGS 1
wdenk8596ffd2004-10-10 18:49:14 +000049#define CONFIG_INITRD_TAG 1
wdenke97d3d92004-02-23 22:22:28 +000050
51/*
52 * Size of malloc() pool
53 */
54#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
55#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
56
57/*
58 * Hardware drivers
59 */
60#define CONFIG_DRIVER_LAN91C96
61#define CONFIG_LAN91C96_BASE 0x04000300
62#define CONFIG_LAN91C96_EXT_PHY
63
64/*
65 * NS16550 Configuration
66 */
67#define CFG_NS16550
68#define CFG_NS16550_SERIAL
69#define CFG_NS16550_REG_SIZE (-4)
70#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
71#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart */
wdenke537b3b2004-02-23 23:54:43 +000072
wdenke97d3d92004-02-23 22:22:28 +000073/*
74 * select serial console configuration
75 */
76#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1610 H2 */
77
78/* allow to overwrite serial and ethaddr */
79#define CONFIG_ENV_OVERWRITE
80#define CONFIG_CONS_INDEX 1
81#define CONFIG_BAUDRATE 115200
82#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
83
84#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP)
85#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
86
87/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
88#include <cmd_confdefs.h>
89#include <configs/omap1510.h>
90
91#define CONFIG_BOOTDELAY 3
wdenk8596ffd2004-10-10 18:49:14 +000092#define CONFIG_BOOTARGS "console=ttyS0,115200n8 noinitrd root=/dev/nfs ip=dhcp"
wdenked2ac4b2004-03-14 18:23:55 +000093#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm"
94#define CFG_AUTOLOAD "n" /* No autoload */
wdenke97d3d92004-02-23 22:22:28 +000095
96#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
97#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
98#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
99#endif
100
101/*
102 * Miscellaneous configurable options
103 */
104#define CFG_LONGHELP /* undef to save memory */
105#define CFG_PROMPT "OMAP1610 H2 # " /* Monitor Command Prompt */
106#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
107/* Print Buffer Size */
108#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
109#define CFG_MAXARGS 16 /* max number of command args */
110#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
111
112#define CFG_MEMTEST_START 0x10000000 /* memtest works on */
113#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
114
115#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
116
117#define CFG_LOAD_ADDR 0x10000000 /* default load address */
118
119/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
120 * DPLL1. This time is further subdivided by a local divisor.
121 */
122#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */
123#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */
124#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
125
126/*-----------------------------------------------------------------------
127 * Stack sizes
128 *
129 * The stack sizes are set up in start.S using the settings below
130 */
131#define CONFIG_STACKSIZE (128*1024) /* regular stack */
132#ifdef CONFIG_USE_IRQ
133#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
134#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
135#endif
136
137/*-----------------------------------------------------------------------
138 * Physical Memory Map
139 */
wdenk920e91b2004-06-09 15:25:53 +0000140#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
141#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
wdenke97d3d92004-02-23 22:22:28 +0000142#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
143
wdenk920e91b2004-06-09 15:25:53 +0000144#define PHYS_FLASH_1_BM1 0x00000000 /* Flash Bank #1 if booting from flash */
145#define PHYS_FLASH_1_BM0 0x0C000000 /* Flash Bank #1 if booting from RAM */
146
147#ifdef CONFIG_CS_AUTOBOOT /* Determine CS assignment in runtime */
wdenk51108172004-06-09 15:37:23 +0000148
wdenk920e91b2004-06-09 15:25:53 +0000149#ifndef __ASSEMBLY__
150extern unsigned long omap_flash_base; /* set in flash__init */
wdenke97d3d92004-02-23 22:22:28 +0000151#endif
wdenk920e91b2004-06-09 15:25:53 +0000152#define CFG_FLASH_BASE omap_flash_base
wdenke97d3d92004-02-23 22:22:28 +0000153
wdenk920e91b2004-06-09 15:25:53 +0000154#elif defined(CONFIG_CS0_BOOT)
155
156#define CFG_FLASH_BASE PHYS_FLASH_1_BM0
157
158#else
159
160#define CFG_FLASH_BASE PHYS_FLASH_1_BM1
161
162#endif
wdenke97d3d92004-02-23 22:22:28 +0000163
164/*-----------------------------------------------------------------------
165 * FLASH and environment organization
166 */
167#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
168#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */
169#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
170/* addr of environment */
171#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x020000)
172
173/* timeout values are in ticks */
174#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */
175#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */
176
177#define CFG_ENV_IS_IN_FLASH 1
178#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
179#define CFG_ENV_OFFSET 0x20000 /* environment starts here */
180
181#endif /* __CONFIG_H */