blob: e0c2284a901a9e89898b9a049806c7f0ee4cb821 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Simon Glassb2978d32014-11-14 20:56:32 -07002/*
3 * From Coreboot
4 *
5 * Copyright (C) 2001 Ronald G. Minnich
6 * Copyright (C) 2005 Nick.Barker9@btinternet.com
7 * Copyright (C) 2007-2009 coresystems GmbH
Simon Glassb2978d32014-11-14 20:56:32 -07008 */
9
Simon Glassba23a612025-03-15 14:25:28 +000010#define LOG_CATEGRORY LOGC_ARCH
11
Simon Glass0f2af882020-05-10 11:40:05 -060012#include <log.h>
Simon Glassb2978d32014-11-14 20:56:32 -070013#include <asm/pci.h>
14#include "bios_emul.h"
15
16/* errors go in AH. Just set these up so that word assigns will work */
17enum {
18 PCIBIOS_SUCCESSFUL = 0x0000,
19 PCIBIOS_UNSUPPORTED = 0x8100,
20 PCIBIOS_BADVENDOR = 0x8300,
21 PCIBIOS_NODEV = 0x8600,
22 PCIBIOS_BADREG = 0x8700
23};
24
25int int10_handler(void)
26{
27 static u8 cursor_row, cursor_col;
28 int res = 0;
29
30 switch ((M.x86.R_EAX & 0xff00) >> 8) {
31 case 0x01: /* Set cursor shape */
32 res = 1;
33 break;
34 case 0x02: /* Set cursor position */
35 if (cursor_row != ((M.x86.R_EDX >> 8) & 0xff) ||
36 cursor_col >= (M.x86.R_EDX & 0xff)) {
37 debug("\n");
38 }
39 cursor_row = (M.x86.R_EDX >> 8) & 0xff;
40 cursor_col = M.x86.R_EDX & 0xff;
41 res = 1;
42 break;
43 case 0x03: /* Get cursor position */
44 M.x86.R_EAX &= 0x00ff;
45 M.x86.R_ECX = 0x0607;
46 M.x86.R_EDX = (cursor_row << 8) | cursor_col;
47 res = 1;
48 break;
49 case 0x06: /* Scroll up */
50 debug("\n");
51 res = 1;
52 break;
53 case 0x08: /* Get Character and Mode at Cursor Position */
54 M.x86.R_EAX = 0x0f00 | 'A'; /* White on black 'A' */
55 res = 1;
56 break;
57 case 0x09: /* Write Character and attribute */
58 case 0x0e: /* Write Character */
59 debug("%c", M.x86.R_EAX & 0xff);
60 res = 1;
61 break;
62 case 0x0f: /* Get video mode */
63 M.x86.R_EAX = 0x5002; /*80 x 25 */
64 M.x86.R_EBX &= 0x00ff;
65 res = 1;
66 break;
67 default:
68 printf("Unknown INT10 function %04x\n", M.x86.R_EAX & 0xffff);
69 break;
70 }
71 return res;
72}
73
74int int12_handler(void)
75{
76 M.x86.R_EAX = 64 * 1024;
77 return 1;
78}
79
80int int16_handler(void)
81{
82 int res = 0;
83
84 switch ((M.x86.R_EAX & 0xff00) >> 8) {
85 case 0x00: /* Check for Keystroke */
86 M.x86.R_EAX = 0x6120; /* Space Bar, Space */
87 res = 1;
88 break;
89 case 0x01: /* Check for Keystroke */
90 M.x86.R_EFLG |= 1 << 6; /* Zero Flag set (no key available) */
91 res = 1;
92 break;
93 default:
94 printf("Unknown INT16 function %04x\n", M.x86.R_EAX & 0xffff);
95
96break;
97 }
98 return res;
99}
100
101#define PCI_CONFIG_SPACE_TYPE1 (1 << 0)
102#define PCI_SPECIAL_CYCLE_TYPE1 (1 << 4)
103
104int int1a_handler(void)
105{
106 unsigned short func = (unsigned short)M.x86.R_EAX;
107 int retval = 1;
108 unsigned short devid, vendorid, devfn;
Simon Glass26ec2872015-11-29 13:17:56 -0700109 struct udevice *dev;
Simon Glassb2978d32014-11-14 20:56:32 -0700110 /* Use short to get rid of gabage in upper half of 32-bit register */
111 short devindex;
112 unsigned char bus;
Simon Glass26ec2872015-11-29 13:17:56 -0700113 pci_dev_t bdf;
Simon Glassb2978d32014-11-14 20:56:32 -0700114 u32 dword;
115 u16 word;
116 u8 byte, reg;
Simon Glass26ec2872015-11-29 13:17:56 -0700117 int ret;
Simon Glassb2978d32014-11-14 20:56:32 -0700118
119 switch (func) {
120 case 0xb101: /* PCIBIOS Check */
121 M.x86.R_EDX = 0x20494350; /* ' ICP' */
122 M.x86.R_EAX &= 0xffff0000; /* Clear AH / AL */
123 M.x86.R_EAX |= PCI_CONFIG_SPACE_TYPE1 |
124 PCI_SPECIAL_CYCLE_TYPE1;
125 /*
126 * last bus in the system. Hard code to 255 for now.
127 * dev_enumerate() does not seem to tell us (publically)
128 */
129 M.x86.R_ECX = 0xff;
130 M.x86.R_EDI = 0x00000000; /* protected mode entry */
131 retval = 1;
132 break;
133 case 0xb102: /* Find Device */
134 devid = M.x86.R_ECX;
135 vendorid = M.x86.R_EDX;
136 devindex = M.x86.R_ESI;
Simon Glass26ec2872015-11-29 13:17:56 -0700137 bdf = -1;
138 ret = dm_pci_find_device(vendorid, devid, devindex, &dev);
139 if (!ret) {
Simon Glassb2978d32014-11-14 20:56:32 -0700140 unsigned short busdevfn;
Simon Glass26ec2872015-11-29 13:17:56 -0700141
142 bdf = dm_pci_get_bdf(dev);
Simon Glassb2978d32014-11-14 20:56:32 -0700143 M.x86.R_EAX &= 0xffff00ff; /* Clear AH */
144 M.x86.R_EAX |= PCIBIOS_SUCCESSFUL;
145 /*
146 * busnum is an unsigned char;
147 * devfn is an int, so we mask it off.
148 */
Simon Glass26ec2872015-11-29 13:17:56 -0700149 busdevfn = (PCI_BUS(bdf) << 8) | PCI_DEV(bdf) << 3 |
150 PCI_FUNC(bdf);
Simon Glassb2978d32014-11-14 20:56:32 -0700151 debug("0x%x: return 0x%x\n", func, busdevfn);
152 M.x86.R_EBX = busdevfn;
153 retval = 1;
154 } else {
155 M.x86.R_EAX &= 0xffff00ff; /* Clear AH */
156 M.x86.R_EAX |= PCIBIOS_NODEV;
157 retval = 0;
158 }
159 break;
160 case 0xb10a: /* Read Config Dword */
161 case 0xb109: /* Read Config Word */
162 case 0xb108: /* Read Config Byte */
163 case 0xb10d: /* Write Config Dword */
164 case 0xb10c: /* Write Config Word */
165 case 0xb10b: /* Write Config Byte */
166 devfn = M.x86.R_EBX & 0xff;
167 bus = M.x86.R_EBX >> 8;
168 reg = M.x86.R_EDI;
Simon Glass26ec2872015-11-29 13:17:56 -0700169 bdf = PCI_BDF(bus, devfn >> 3, devfn & 7);
170
171 ret = dm_pci_bus_find_bdf(bdf, &dev);
172 if (ret) {
173 debug("%s: Device %x not found\n", __func__, bdf);
174 break;
175 }
Jian Luo589ff322015-07-06 16:31:28 +0800176
Simon Glassb2978d32014-11-14 20:56:32 -0700177 switch (func) {
178 case 0xb108: /* Read Config Byte */
Simon Glass26ec2872015-11-29 13:17:56 -0700179 dm_pci_read_config8(dev, reg, &byte);
Simon Glassb2978d32014-11-14 20:56:32 -0700180 M.x86.R_ECX = byte;
181 break;
182 case 0xb109: /* Read Config Word */
Simon Glass26ec2872015-11-29 13:17:56 -0700183 dm_pci_read_config16(dev, reg, &word);
Simon Glassb2978d32014-11-14 20:56:32 -0700184 M.x86.R_ECX = word;
185 break;
186 case 0xb10a: /* Read Config Dword */
Simon Glass26ec2872015-11-29 13:17:56 -0700187 dm_pci_read_config32(dev, reg, &dword);
Simon Glassb2978d32014-11-14 20:56:32 -0700188 M.x86.R_ECX = dword;
189 break;
190 case 0xb10b: /* Write Config Byte */
191 byte = M.x86.R_ECX;
Simon Glass26ec2872015-11-29 13:17:56 -0700192 dm_pci_write_config8(dev, reg, byte);
Simon Glassb2978d32014-11-14 20:56:32 -0700193 break;
194 case 0xb10c: /* Write Config Word */
195 word = M.x86.R_ECX;
Simon Glass26ec2872015-11-29 13:17:56 -0700196 dm_pci_write_config16(dev, reg, word);
Simon Glassb2978d32014-11-14 20:56:32 -0700197 break;
198 case 0xb10d: /* Write Config Dword */
199 dword = M.x86.R_ECX;
Simon Glass26ec2872015-11-29 13:17:56 -0700200 dm_pci_write_config32(dev, reg, dword);
Simon Glassb2978d32014-11-14 20:56:32 -0700201 break;
202 }
Simon Glass58de6c62025-03-15 14:25:29 +0000203 log_debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%x\n", func,
204 bus, devfn, reg, M.x86.R_ECX);
Simon Glassb2978d32014-11-14 20:56:32 -0700205 M.x86.R_EAX &= 0xffff00ff; /* Clear AH */
206 M.x86.R_EAX |= PCIBIOS_SUCCESSFUL;
207 retval = 1;
208 break;
209 default:
210 printf("UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func);
211 M.x86.R_EAX &= 0xffff00ff; /* Clear AH */
212 M.x86.R_EAX |= PCIBIOS_UNSUPPORTED;
213 retval = 0;
214 break;
215 }
216
217 return retval;
218}