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git01.mediatek.com / filogic / uboot / 58a3c1b2c5ae5d39391ee89040532b2ccf776223 / . / arch / m68k / include / asm / immap_5282.h
blob: a36e065c7595783d791e33f237ff95f9e4db894f [file] [log] [blame]
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]1/*
2 * MCF5282 Internal Memory Map
3 *
4 * Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
5 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +0200[diff] [blame]6 * SPDX-License-Identifier: GPL-2.0+
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]7 */
8
9#ifndef __IMMAP_5282__
10#define __IMMAP_5282__
11
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]12#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000)
13#define MMAP_SDRAMC (CONFIG_SYS_MBAR + 0x00000040)
14#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
15#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100)
16#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000140)
17#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000180)
18#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x000001C0)
19#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200)
20#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240)
21#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280)
22#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300)
23#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340)
24#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400)
25#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440)
26#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480)
27#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0)
28#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00)
29#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00)
30#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00)
31#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000)
32#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400)
33#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000)
34#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000)
35#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000)
36#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000)
37#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000)
38#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000)
39#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000)
40#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000)
41#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000)
42#define MMAP_QADC (CONFIG_SYS_MBAR + 0x00190000)
43#define MMAP_GPTMRA (CONFIG_SYS_MBAR + 0x001A0000)
44#define MMAP_GPTMRB (CONFIG_SYS_MBAR + 0x001B0000)
45#define MMAP_CAN (CONFIG_SYS_MBAR + 0x001C0000)
46#define MMAP_CFMC (CONFIG_SYS_MBAR + 0x001D0000)
47#define MMAP_CFMMEM (CONFIG_SYS_MBAR + 0x04000000)
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]48
TsiChung Liew7f1a0462008-10-21 10:03:07 +0000[diff] [blame]49#include <asm/coldfire/eport.h>
50#include <asm/coldfire/flexbus.h>
51#include <asm/coldfire/flexcan.h>
52#include <asm/coldfire/intctrl.h>
53#include <asm/coldfire/qspi.h>
54
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]55/* System Control Module */
56typedef struct scm_ctrl {
57 u32 ipsbar;
58 u32 res1;
59 u32 rambar;
60 u32 res2;
61 u8 crsr;
62 u8 cwcr;
63 u8 lpicr;
64 u8 cwsr;
65 u32 res3;
66 u8 mpark;
67 u8 res4[3];
68 u8 pacr0;
69 u8 pacr1;
70 u8 pacr2;
71 u8 pacr3;
72 u8 pacr4;
73 u8 res5;
74 u8 pacr5;
75 u8 pacr6;
76 u8 pacr7;
77 u8 res6;
78 u8 pacr8;
79 u8 res7;
80 u8 gpacr0;
81 u8 gpacr1;
82 u16 res8;
83} scm_t;
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]84
TsiChung Liew7f1a0462008-10-21 10:03:07 +0000[diff] [blame]85typedef struct canex_ctrl {
86 can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
87} canex_t;
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]88
89/* Clock Module registers */
90typedef struct pll_ctrl {
91 u16 syncr; /* 0x00 synthesizer control register */
92 u16 synsr; /* 0x02 synthesizer status register */
93} pll_t;
94
95/* Watchdog registers */
96typedef struct wdog_ctrl {
97 ushort wcr;
98 ushort wmr;
99 ushort wcntr;
100 ushort wsr;
101} wdog_t;
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]102
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]103#endif /* __IMMAP_5282__ */