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Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
Kever Yangfc281b72017-02-23 15:37:50 +08002/*
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08003 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
Kever Yangfc281b72017-02-23 15:37:50 +08004 */
5
6#include <dt-bindings/clock/rk3328-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/pinctrl/rockchip.h>
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +080011#include <dt-bindings/power/rk3328-power.h>
12#include <dt-bindings/soc/rockchip,boot-mode.h>
13#include <dt-bindings/thermal/thermal.h>
Kever Yangfc281b72017-02-23 15:37:50 +080014
15/ {
16 compatible = "rockchip,rk3328";
17
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 aliases {
23 serial0 = &uart0;
24 serial1 = &uart1;
25 serial2 = &uart2;
26 i2c0 = &i2c0;
27 i2c1 = &i2c1;
28 i2c2 = &i2c2;
29 i2c3 = &i2c3;
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +080030 ethernet0 = &gmac2io;
31 ethernet1 = &gmac2phy;
Kever Yangfc281b72017-02-23 15:37:50 +080032 };
33
34 cpus {
35 #address-cells = <2>;
36 #size-cells = <0>;
37
38 cpu0: cpu@0 {
39 device_type = "cpu";
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +080040 compatible = "arm,cortex-a53";
Kever Yangfc281b72017-02-23 15:37:50 +080041 reg = <0x0 0x0>;
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +080042 clocks = <&cru ARMCLK>;
43 #cooling-cells = <2>;
44 cpu-idle-states = <&CPU_SLEEP>;
45 dynamic-power-coefficient = <120>;
Kever Yangfc281b72017-02-23 15:37:50 +080046 enable-method = "psci";
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +080047 next-level-cache = <&l2>;
Kever Yangfc281b72017-02-23 15:37:50 +080048 operating-points-v2 = <&cpu0_opp_table>;
49 };
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +080050
Kever Yangfc281b72017-02-23 15:37:50 +080051 cpu1: cpu@1 {
52 device_type = "cpu";
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +080053 compatible = "arm,cortex-a53";
Kever Yangfc281b72017-02-23 15:37:50 +080054 reg = <0x0 0x1>;
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +080055 clocks = <&cru ARMCLK>;
56 #cooling-cells = <2>;
57 cpu-idle-states = <&CPU_SLEEP>;
58 dynamic-power-coefficient = <120>;
Kever Yangfc281b72017-02-23 15:37:50 +080059 enable-method = "psci";
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +080060 next-level-cache = <&l2>;
61 operating-points-v2 = <&cpu0_opp_table>;
Kever Yangfc281b72017-02-23 15:37:50 +080062 };
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +080063
Kever Yangfc281b72017-02-23 15:37:50 +080064 cpu2: cpu@2 {
65 device_type = "cpu";
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +080066 compatible = "arm,cortex-a53";
Kever Yangfc281b72017-02-23 15:37:50 +080067 reg = <0x0 0x2>;
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +080068 clocks = <&cru ARMCLK>;
69 #cooling-cells = <2>;
70 cpu-idle-states = <&CPU_SLEEP>;
71 dynamic-power-coefficient = <120>;
Kever Yangfc281b72017-02-23 15:37:50 +080072 enable-method = "psci";
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +080073 next-level-cache = <&l2>;
74 operating-points-v2 = <&cpu0_opp_table>;
Kever Yangfc281b72017-02-23 15:37:50 +080075 };
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +080076
Kever Yangfc281b72017-02-23 15:37:50 +080077 cpu3: cpu@3 {
78 device_type = "cpu";
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +080079 compatible = "arm,cortex-a53";
Kever Yangfc281b72017-02-23 15:37:50 +080080 reg = <0x0 0x3>;
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +080081 clocks = <&cru ARMCLK>;
82 #cooling-cells = <2>;
83 cpu-idle-states = <&CPU_SLEEP>;
84 dynamic-power-coefficient = <120>;
Kever Yangfc281b72017-02-23 15:37:50 +080085 enable-method = "psci";
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +080086 next-level-cache = <&l2>;
87 operating-points-v2 = <&cpu0_opp_table>;
88 };
89
90 idle-states {
91 entry-method = "psci";
92
93 CPU_SLEEP: cpu-sleep {
94 compatible = "arm,idle-state";
95 local-timer-stop;
96 arm,psci-suspend-param = <0x0010000>;
97 entry-latency-us = <120>;
98 exit-latency-us = <250>;
99 min-residency-us = <900>;
100 };
101 };
102
103 l2: l2-cache0 {
104 compatible = "cache";
Kever Yangfc281b72017-02-23 15:37:50 +0800105 };
106 };
107
108 cpu0_opp_table: opp_table0 {
109 compatible = "operating-points-v2";
110 opp-shared;
111
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800112 opp-408000000 {
Kever Yangfc281b72017-02-23 15:37:50 +0800113 opp-hz = /bits/ 64 <408000000>;
114 opp-microvolt = <950000>;
115 clock-latency-ns = <40000>;
116 opp-suspend;
117 };
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800118 opp-600000000 {
Kever Yangfc281b72017-02-23 15:37:50 +0800119 opp-hz = /bits/ 64 <600000000>;
120 opp-microvolt = <950000>;
121 clock-latency-ns = <40000>;
122 };
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800123 opp-816000000 {
Kever Yangfc281b72017-02-23 15:37:50 +0800124 opp-hz = /bits/ 64 <816000000>;
125 opp-microvolt = <1000000>;
126 clock-latency-ns = <40000>;
127 };
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800128 opp-1008000000 {
Kever Yangfc281b72017-02-23 15:37:50 +0800129 opp-hz = /bits/ 64 <1008000000>;
130 opp-microvolt = <1100000>;
131 clock-latency-ns = <40000>;
132 };
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800133 opp-1200000000 {
Kever Yangfc281b72017-02-23 15:37:50 +0800134 opp-hz = /bits/ 64 <1200000000>;
135 opp-microvolt = <1225000>;
136 clock-latency-ns = <40000>;
137 };
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800138 opp-1296000000 {
Kever Yangfc281b72017-02-23 15:37:50 +0800139 opp-hz = /bits/ 64 <1296000000>;
140 opp-microvolt = <1300000>;
141 clock-latency-ns = <40000>;
142 };
143 };
144
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800145 analog_sound: analog-sound {
146 compatible = "simple-audio-card";
147 simple-audio-card,format = "i2s";
148 simple-audio-card,mclk-fs = <256>;
149 simple-audio-card,name = "Analog";
150 status = "disabled";
151
152 simple-audio-card,cpu {
153 sound-dai = <&i2s1>;
154 };
155
156 simple-audio-card,codec {
157 sound-dai = <&codec>;
158 };
159 };
160
Kever Yangfc281b72017-02-23 15:37:50 +0800161 arm-pmu {
162 compatible = "arm,cortex-a53-pmu";
163 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
167 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
168 };
169
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800170 display_subsystem: display-subsystem {
171 compatible = "rockchip,display-subsystem";
172 ports = <&vop_out>;
173 };
174
175 hdmi_sound: hdmi-sound {
176 compatible = "simple-audio-card";
177 simple-audio-card,format = "i2s";
178 simple-audio-card,mclk-fs = <128>;
179 simple-audio-card,name = "HDMI";
180 status = "disabled";
181
182 simple-audio-card,cpu {
183 sound-dai = <&i2s0>;
184 };
185
186 simple-audio-card,codec {
187 sound-dai = <&hdmi>;
188 };
189 };
190
Kever Yangfc281b72017-02-23 15:37:50 +0800191 psci {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800192 compatible = "arm,psci-1.0", "arm,psci-0.2";
Kever Yangfc281b72017-02-23 15:37:50 +0800193 method = "smc";
194 };
195
196 timer {
197 compatible = "arm,armv8-timer";
198 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
199 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
200 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
201 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
202 };
203
204 xin24m: xin24m {
205 compatible = "fixed-clock";
206 #clock-cells = <0>;
207 clock-frequency = <24000000>;
208 clock-output-names = "xin24m";
209 };
210
211 i2s0: i2s@ff000000 {
212 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
213 reg = <0x0 0xff000000 0x0 0x1000>;
214 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
216 clock-names = "i2s_clk", "i2s_hclk";
217 dmas = <&dmac 11>, <&dmac 12>;
Kever Yangfc281b72017-02-23 15:37:50 +0800218 dma-names = "tx", "rx";
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800219 #sound-dai-cells = <0>;
Kever Yangfc281b72017-02-23 15:37:50 +0800220 status = "disabled";
221 };
222
223 i2s1: i2s@ff010000 {
224 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
225 reg = <0x0 0xff010000 0x0 0x1000>;
226 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
228 clock-names = "i2s_clk", "i2s_hclk";
229 dmas = <&dmac 14>, <&dmac 15>;
Kever Yangfc281b72017-02-23 15:37:50 +0800230 dma-names = "tx", "rx";
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800231 #sound-dai-cells = <0>;
Kever Yangfc281b72017-02-23 15:37:50 +0800232 status = "disabled";
233 };
234
235 i2s2: i2s@ff020000 {
236 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
237 reg = <0x0 0xff020000 0x0 0x1000>;
238 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
240 clock-names = "i2s_clk", "i2s_hclk";
241 dmas = <&dmac 0>, <&dmac 1>;
Kever Yangfc281b72017-02-23 15:37:50 +0800242 dma-names = "tx", "rx";
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800243 #sound-dai-cells = <0>;
Kever Yangfc281b72017-02-23 15:37:50 +0800244 status = "disabled";
245 };
246
247 spdif: spdif@ff030000 {
248 compatible = "rockchip,rk3328-spdif";
249 reg = <0x0 0xff030000 0x0 0x1000>;
250 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
251 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
252 clock-names = "mclk", "hclk";
253 dmas = <&dmac 10>;
Kever Yangfc281b72017-02-23 15:37:50 +0800254 dma-names = "tx";
255 pinctrl-names = "default";
256 pinctrl-0 = <&spdifm2_tx>;
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800257 #sound-dai-cells = <0>;
258 status = "disabled";
259 };
260
261 pdm: pdm@ff040000 {
262 compatible = "rockchip,pdm";
263 reg = <0x0 0xff040000 0x0 0x1000>;
264 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
265 clock-names = "pdm_clk", "pdm_hclk";
266 dmas = <&dmac 16>;
267 dma-names = "rx";
268 pinctrl-names = "default", "sleep";
269 pinctrl-0 = <&pdmm0_clk
270 &pdmm0_sdi0
271 &pdmm0_sdi1
272 &pdmm0_sdi2
273 &pdmm0_sdi3>;
274 pinctrl-1 = <&pdmm0_clk_sleep
275 &pdmm0_sdi0_sleep
276 &pdmm0_sdi1_sleep
277 &pdmm0_sdi2_sleep
278 &pdmm0_sdi3_sleep>;
Kever Yangfc281b72017-02-23 15:37:50 +0800279 status = "disabled";
280 };
281
282 grf: syscon@ff100000 {
283 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
284 reg = <0x0 0xff100000 0x0 0x1000>;
Kever Yangfc281b72017-02-23 15:37:50 +0800285
286 io_domains: io-domains {
287 compatible = "rockchip,rk3328-io-voltage-domain";
288 status = "disabled";
289 };
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800290
Peter Robinson7715db32021-07-22 16:20:43 +0100291 grf_gpio: gpio {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800292 compatible = "rockchip,rk3328-grf-gpio";
293 gpio-controller;
294 #gpio-cells = <2>;
295 };
296
297 power: power-controller {
298 compatible = "rockchip,rk3328-power-controller";
299 #power-domain-cells = <1>;
300 #address-cells = <1>;
301 #size-cells = <0>;
302
Peter Robinson7715db32021-07-22 16:20:43 +0100303 power-domain@RK3328_PD_HEVC {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800304 reg = <RK3328_PD_HEVC>;
Peter Robinson7715db32021-07-22 16:20:43 +0100305 #power-domain-cells = <0>;
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800306 };
Peter Robinson7715db32021-07-22 16:20:43 +0100307 power-domain@RK3328_PD_VIDEO {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800308 reg = <RK3328_PD_VIDEO>;
Peter Robinson7715db32021-07-22 16:20:43 +0100309 #power-domain-cells = <0>;
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800310 };
Peter Robinson7715db32021-07-22 16:20:43 +0100311 power-domain@RK3328_PD_VPU {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800312 reg = <RK3328_PD_VPU>;
313 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
Peter Robinson7715db32021-07-22 16:20:43 +0100314 #power-domain-cells = <0>;
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800315 };
316 };
317
318 reboot-mode {
319 compatible = "syscon-reboot-mode";
320 offset = <0x5c8>;
321 mode-normal = <BOOT_NORMAL>;
322 mode-recovery = <BOOT_RECOVERY>;
323 mode-bootloader = <BOOT_FASTBOOT>;
324 mode-loader = <BOOT_BL_DOWNLOAD>;
325 };
Kever Yangfc281b72017-02-23 15:37:50 +0800326 };
327
328 uart0: serial@ff110000 {
329 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
330 reg = <0x0 0xff110000 0x0 0x100>;
331 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
333 clock-names = "baudclk", "apb_pclk";
Kever Yangfc281b72017-02-23 15:37:50 +0800334 dmas = <&dmac 2>, <&dmac 3>;
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800335 dma-names = "tx", "rx";
Kever Yangfc281b72017-02-23 15:37:50 +0800336 pinctrl-names = "default";
337 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800338 reg-io-width = <4>;
339 reg-shift = <2>;
Kever Yangfc281b72017-02-23 15:37:50 +0800340 status = "disabled";
341 };
342
343 uart1: serial@ff120000 {
344 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
345 reg = <0x0 0xff120000 0x0 0x100>;
346 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800348 clock-names = "baudclk", "apb_pclk";
Kever Yangfc281b72017-02-23 15:37:50 +0800349 dmas = <&dmac 4>, <&dmac 5>;
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800350 dma-names = "tx", "rx";
Kever Yangfc281b72017-02-23 15:37:50 +0800351 pinctrl-names = "default";
352 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800353 reg-io-width = <4>;
354 reg-shift = <2>;
Kever Yangfc281b72017-02-23 15:37:50 +0800355 status = "disabled";
356 };
357
358 uart2: serial@ff130000 {
359 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
360 reg = <0x0 0xff130000 0x0 0x100>;
361 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
363 clock-names = "baudclk", "apb_pclk";
Kever Yangfc281b72017-02-23 15:37:50 +0800364 dmas = <&dmac 6>, <&dmac 7>;
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800365 dma-names = "tx", "rx";
Kever Yangfc281b72017-02-23 15:37:50 +0800366 pinctrl-names = "default";
367 pinctrl-0 = <&uart2m1_xfer>;
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800368 reg-io-width = <4>;
369 reg-shift = <2>;
Kever Yangfc281b72017-02-23 15:37:50 +0800370 status = "disabled";
371 };
372
Kever Yangfc281b72017-02-23 15:37:50 +0800373 i2c0: i2c@ff150000 {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800374 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
Kever Yangfc281b72017-02-23 15:37:50 +0800375 reg = <0x0 0xff150000 0x0 0x1000>;
376 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
377 #address-cells = <1>;
378 #size-cells = <0>;
379 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
380 clock-names = "i2c", "pclk";
381 pinctrl-names = "default";
382 pinctrl-0 = <&i2c0_xfer>;
383 status = "disabled";
384 };
385
386 i2c1: i2c@ff160000 {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800387 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
Kever Yangfc281b72017-02-23 15:37:50 +0800388 reg = <0x0 0xff160000 0x0 0x1000>;
389 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
390 #address-cells = <1>;
391 #size-cells = <0>;
392 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
393 clock-names = "i2c", "pclk";
394 pinctrl-names = "default";
395 pinctrl-0 = <&i2c1_xfer>;
396 status = "disabled";
397 };
398
399 i2c2: i2c@ff170000 {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800400 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
Kever Yangfc281b72017-02-23 15:37:50 +0800401 reg = <0x0 0xff170000 0x0 0x1000>;
402 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
403 #address-cells = <1>;
404 #size-cells = <0>;
405 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
406 clock-names = "i2c", "pclk";
407 pinctrl-names = "default";
408 pinctrl-0 = <&i2c2_xfer>;
409 status = "disabled";
410 };
411
412 i2c3: i2c@ff180000 {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800413 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
Kever Yangfc281b72017-02-23 15:37:50 +0800414 reg = <0x0 0xff180000 0x0 0x1000>;
415 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
416 #address-cells = <1>;
417 #size-cells = <0>;
418 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
419 clock-names = "i2c", "pclk";
420 pinctrl-names = "default";
421 pinctrl-0 = <&i2c3_xfer>;
422 status = "disabled";
423 };
424
425 spi0: spi@ff190000 {
426 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
427 reg = <0x0 0xff190000 0x0 0x1000>;
428 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
429 #address-cells = <1>;
430 #size-cells = <0>;
431 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
432 clock-names = "spiclk", "apb_pclk";
433 dmas = <&dmac 8>, <&dmac 9>;
Kever Yangfc281b72017-02-23 15:37:50 +0800434 dma-names = "tx", "rx";
435 pinctrl-names = "default";
436 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
437 status = "disabled";
438 };
439
440 wdt: watchdog@ff1a0000 {
Peter Robinson7715db32021-07-22 16:20:43 +0100441 compatible = "rockchip,rk3328-wdt", "snps,dw-wdt";
Kever Yangfc281b72017-02-23 15:37:50 +0800442 reg = <0x0 0xff1a0000 0x0 0x100>;
443 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800444 clocks = <&cru PCLK_WDT>;
445 };
446
447 pwm0: pwm@ff1b0000 {
448 compatible = "rockchip,rk3328-pwm";
449 reg = <0x0 0xff1b0000 0x0 0x10>;
450 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
451 clock-names = "pwm", "pclk";
452 pinctrl-names = "default";
453 pinctrl-0 = <&pwm0_pin>;
454 #pwm-cells = <3>;
Kever Yangfc281b72017-02-23 15:37:50 +0800455 status = "disabled";
456 };
457
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800458 pwm1: pwm@ff1b0010 {
459 compatible = "rockchip,rk3328-pwm";
460 reg = <0x0 0xff1b0010 0x0 0x10>;
461 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
462 clock-names = "pwm", "pclk";
463 pinctrl-names = "default";
464 pinctrl-0 = <&pwm1_pin>;
465 #pwm-cells = <3>;
466 status = "disabled";
467 };
Kever Yangfc281b72017-02-23 15:37:50 +0800468
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800469 pwm2: pwm@ff1b0020 {
470 compatible = "rockchip,rk3328-pwm";
471 reg = <0x0 0xff1b0020 0x0 0x10>;
472 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
473 clock-names = "pwm", "pclk";
474 pinctrl-names = "default";
475 pinctrl-0 = <&pwm2_pin>;
476 #pwm-cells = <3>;
477 status = "disabled";
478 };
479
480 pwm3: pwm@ff1b0030 {
481 compatible = "rockchip,rk3328-pwm";
482 reg = <0x0 0xff1b0030 0x0 0x10>;
483 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
485 clock-names = "pwm", "pclk";
486 pinctrl-names = "default";
487 pinctrl-0 = <&pwmir_pin>;
488 #pwm-cells = <3>;
489 status = "disabled";
490 };
491
Peter Robinson7715db32021-07-22 16:20:43 +0100492 dmac: dmac@ff1f0000 {
493 compatible = "arm,pl330", "arm,primecell";
494 reg = <0x0 0xff1f0000 0x0 0x4000>;
495 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
497 arm,pl330-periph-burst;
498 clocks = <&cru ACLK_DMAC>;
499 clock-names = "apb_pclk";
500 #dma-cells = <1>;
501 };
502
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800503 thermal-zones {
504 soc_thermal: soc-thermal {
505 polling-delay-passive = <20>;
506 polling-delay = <1000>;
507 sustainable-power = <1000>;
508
509 thermal-sensors = <&tsadc 0>;
510
511 trips {
512 threshold: trip-point0 {
513 temperature = <70000>;
514 hysteresis = <2000>;
515 type = "passive";
516 };
517 target: trip-point1 {
518 temperature = <85000>;
519 hysteresis = <2000>;
520 type = "passive";
521 };
522 soc_crit: soc-crit {
523 temperature = <95000>;
524 hysteresis = <2000>;
525 type = "critical";
526 };
527 };
528
529 cooling-maps {
530 map0 {
531 trip = <&target>;
532 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
533 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
534 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
535 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
536 contribution = <4096>;
537 };
538 };
539 };
540
541 };
542
543 tsadc: tsadc@ff250000 {
544 compatible = "rockchip,rk3328-tsadc";
545 reg = <0x0 0xff250000 0x0 0x100>;
546 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
547 assigned-clocks = <&cru SCLK_TSADC>;
548 assigned-clock-rates = <50000>;
549 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
550 clock-names = "tsadc", "apb_pclk";
551 pinctrl-names = "init", "default", "sleep";
Peter Robinson7715db32021-07-22 16:20:43 +0100552 pinctrl-0 = <&otp_pin>;
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800553 pinctrl-1 = <&otp_out>;
Peter Robinson7715db32021-07-22 16:20:43 +0100554 pinctrl-2 = <&otp_pin>;
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800555 resets = <&cru SRST_TSADC>;
556 reset-names = "tsadc-apb";
557 rockchip,grf = <&grf>;
558 rockchip,hw-tshut-temp = <100000>;
559 #thermal-sensor-cells = <1>;
560 status = "disabled";
561 };
562
563 efuse: efuse@ff260000 {
564 compatible = "rockchip,rk3328-efuse";
565 reg = <0x0 0xff260000 0x0 0x50>;
566 #address-cells = <1>;
567 #size-cells = <1>;
568 clocks = <&cru SCLK_EFUSE>;
569 clock-names = "pclk_efuse";
570 rockchip,efuse-size = <0x20>;
571
572 /* Data cells */
573 efuse_id: id@7 {
574 reg = <0x07 0x10>;
575 };
576 cpu_leakage: cpu-leakage@17 {
577 reg = <0x17 0x1>;
578 };
579 logic_leakage: logic-leakage@19 {
580 reg = <0x19 0x1>;
581 };
582 efuse_cpu_version: cpu-version@1a {
583 reg = <0x1a 0x1>;
584 bits = <3 3>;
Kever Yangfc281b72017-02-23 15:37:50 +0800585 };
586 };
587
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800588 saradc: adc@ff280000 {
589 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
Kever Yangfc281b72017-02-23 15:37:50 +0800590 reg = <0x0 0xff280000 0x0 0x100>;
591 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
592 #io-channel-cells = <1>;
593 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
594 clock-names = "saradc", "apb_pclk";
595 resets = <&cru SRST_SARADC_P>;
596 reset-names = "saradc-apb";
597 status = "disabled";
598 };
599
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800600 gpu: gpu@ff300000 {
601 compatible = "rockchip,rk3328-mali", "arm,mali-450";
602 reg = <0x0 0xff300000 0x0 0x40000>;
603 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
607 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
610 interrupt-names = "gp",
611 "gpmmu",
612 "pp",
613 "pp0",
614 "ppmmu0",
615 "pp1",
616 "ppmmu1";
617 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
618 clock-names = "bus", "core";
619 resets = <&cru SRST_GPU_A>;
620 };
621
622 h265e_mmu: iommu@ff330200 {
623 compatible = "rockchip,iommu";
624 reg = <0x0 0xff330200 0 0x100>;
625 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
626 interrupt-names = "h265e_mmu";
627 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
628 clock-names = "aclk", "iface";
629 #iommu-cells = <0>;
630 status = "disabled";
631 };
632
633 vepu_mmu: iommu@ff340800 {
634 compatible = "rockchip,iommu";
635 reg = <0x0 0xff340800 0x0 0x40>;
636 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
637 interrupt-names = "vepu_mmu";
638 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
639 clock-names = "aclk", "iface";
640 #iommu-cells = <0>;
641 status = "disabled";
642 };
643
644 vpu: video-codec@ff350000 {
645 compatible = "rockchip,rk3328-vpu";
646 reg = <0x0 0xff350000 0x0 0x800>;
647 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
648 interrupt-names = "vdpu";
649 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
650 clock-names = "aclk", "hclk";
651 iommus = <&vpu_mmu>;
652 power-domains = <&power RK3328_PD_VPU>;
653 };
654
655 vpu_mmu: iommu@ff350800 {
656 compatible = "rockchip,iommu";
657 reg = <0x0 0xff350800 0x0 0x40>;
658 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
659 interrupt-names = "vpu_mmu";
660 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
661 clock-names = "aclk", "iface";
662 #iommu-cells = <0>;
663 power-domains = <&power RK3328_PD_VPU>;
664 };
665
666 rkvdec_mmu: iommu@ff360480 {
667 compatible = "rockchip,iommu";
668 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
669 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
670 interrupt-names = "rkvdec_mmu";
671 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
672 clock-names = "aclk", "iface";
673 #iommu-cells = <0>;
674 status = "disabled";
675 };
676
677 vop: vop@ff370000 {
678 compatible = "rockchip,rk3328-vop";
679 reg = <0x0 0xff370000 0x0 0x3efc>;
680 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
682 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
683 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
684 reset-names = "axi", "ahb", "dclk";
685 iommus = <&vop_mmu>;
686 status = "disabled";
687
688 vop_out: port {
689 #address-cells = <1>;
690 #size-cells = <0>;
691
692 vop_out_hdmi: endpoint@0 {
693 reg = <0>;
694 remote-endpoint = <&hdmi_in_vop>;
695 };
696 };
697 };
698
699 vop_mmu: iommu@ff373f00 {
700 compatible = "rockchip,iommu";
701 reg = <0x0 0xff373f00 0x0 0x100>;
702 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
703 interrupt-names = "vop_mmu";
704 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
705 clock-names = "aclk", "iface";
706 #iommu-cells = <0>;
707 status = "disabled";
708 };
709
710 hdmi: hdmi@ff3c0000 {
711 compatible = "rockchip,rk3328-dw-hdmi";
712 reg = <0x0 0xff3c0000 0x0 0x20000>;
713 reg-io-width = <4>;
714 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
715 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
716 clocks = <&cru PCLK_HDMI>,
717 <&cru SCLK_HDMI_SFC>,
718 <&cru SCLK_RTC32K>;
719 clock-names = "iahb",
720 "isfr",
721 "cec";
722 phys = <&hdmiphy>;
723 phy-names = "hdmi";
724 pinctrl-names = "default";
725 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
726 rockchip,grf = <&grf>;
727 #sound-dai-cells = <0>;
728 status = "disabled";
729
730 ports {
731 hdmi_in: port {
732 hdmi_in_vop: endpoint {
733 remote-endpoint = <&vop_out_hdmi>;
734 };
735 };
736 };
737 };
738
739 codec: codec@ff410000 {
740 compatible = "rockchip,rk3328-codec";
741 reg = <0x0 0xff410000 0x0 0x1000>;
742 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
743 clock-names = "pclk", "mclk";
744 rockchip,grf = <&grf>;
745 #sound-dai-cells = <0>;
746 status = "disabled";
747 };
748
749 hdmiphy: phy@ff430000 {
750 compatible = "rockchip,rk3328-hdmi-phy";
751 reg = <0x0 0xff430000 0x0 0x10000>;
752 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
754 clock-names = "sysclk", "refoclk", "refpclk";
755 clock-output-names = "hdmi_phy";
756 #clock-cells = <0>;
757 nvmem-cells = <&efuse_cpu_version>;
758 nvmem-cell-names = "cpu-version";
759 #phy-cells = <0>;
760 status = "disabled";
761 };
762
Kever Yangfc281b72017-02-23 15:37:50 +0800763 cru: clock-controller@ff440000 {
764 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
765 reg = <0x0 0xff440000 0x0 0x1000>;
766 rockchip,grf = <&grf>;
767 #clock-cells = <1>;
768 #reset-cells = <1>;
769 assigned-clocks =
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800770 /*
771 * CPLL should run at 1200, but that is to high for
772 * the initial dividers of most of its children.
773 * We need set cpll child clk div first,
774 * and then set the cpll frequency.
775 */
Kever Yangfc281b72017-02-23 15:37:50 +0800776 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
777 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
778 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
779 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
780 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
781 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
782 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
783 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
784 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
785 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
786 <&cru SCLK_WIFI>, <&cru ARMCLK>,
787 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
788 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
789 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
790 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800791 <&cru SCLK_RTC32K>;
Kever Yangfc281b72017-02-23 15:37:50 +0800792 assigned-clock-parents =
793 <&cru HDMIPHY>, <&cru PLL_APLL>,
794 <&cru PLL_GPLL>, <&xin24m>,
795 <&xin24m>, <&xin24m>;
796 assigned-clock-rates =
797 <0>, <61440000>,
798 <0>, <24000000>,
799 <24000000>, <24000000>,
800 <15000000>, <15000000>,
801 <100000000>, <100000000>,
802 <100000000>, <100000000>,
803 <50000000>, <100000000>,
804 <100000000>, <100000000>,
805 <50000000>, <50000000>,
806 <50000000>, <50000000>,
807 <24000000>, <600000000>,
808 <491520000>, <1200000000>,
809 <150000000>, <75000000>,
810 <75000000>, <150000000>,
811 <75000000>, <75000000>,
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800812 <32768>;
813 };
814
815 usb2phy_grf: syscon@ff450000 {
816 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
817 "simple-mfd";
818 reg = <0x0 0xff450000 0x0 0x10000>;
819 #address-cells = <1>;
820 #size-cells = <1>;
821
Peter Robinson7715db32021-07-22 16:20:43 +0100822 u2phy: usb2phy@100 {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800823 compatible = "rockchip,rk3328-usb2phy";
824 reg = <0x100 0x10>;
825 clocks = <&xin24m>;
826 clock-names = "phyclk";
827 clock-output-names = "usb480m_phy";
828 #clock-cells = <0>;
829 assigned-clocks = <&cru USB480M>;
830 assigned-clock-parents = <&u2phy>;
831 status = "disabled";
832
833 u2phy_otg: otg-port {
834 #phy-cells = <0>;
835 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
836 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
837 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
838 interrupt-names = "otg-bvalid", "otg-id",
839 "linestate";
840 status = "disabled";
841 };
842
843 u2phy_host: host-port {
844 #phy-cells = <0>;
845 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
846 interrupt-names = "linestate";
847 status = "disabled";
848 };
849 };
Kever Yangfc281b72017-02-23 15:37:50 +0800850 };
851
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800852 sdmmc: mmc@ff500000 {
Kever Yangfc281b72017-02-23 15:37:50 +0800853 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
854 reg = <0x0 0xff500000 0x0 0x4000>;
Kever Yangfc281b72017-02-23 15:37:50 +0800855 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800856 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
857 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
858 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
859 fifo-depth = <0x100>;
860 max-frequency = <150000000>;
Kever Yangfc281b72017-02-23 15:37:50 +0800861 status = "disabled";
862 };
863
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800864 sdio: mmc@ff510000 {
Kever Yangfc281b72017-02-23 15:37:50 +0800865 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
866 reg = <0x0 0xff510000 0x0 0x4000>;
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800867 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
Kever Yangfc281b72017-02-23 15:37:50 +0800868 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
869 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800870 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
Kever Yangfc281b72017-02-23 15:37:50 +0800871 fifo-depth = <0x100>;
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800872 max-frequency = <150000000>;
Kever Yangfc281b72017-02-23 15:37:50 +0800873 status = "disabled";
874 };
875
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800876 emmc: mmc@ff520000 {
Kever Yangfc281b72017-02-23 15:37:50 +0800877 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
878 reg = <0x0 0xff520000 0x0 0x4000>;
Kever Yangfc281b72017-02-23 15:37:50 +0800879 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800880 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
881 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
882 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
883 fifo-depth = <0x100>;
884 max-frequency = <150000000>;
Kever Yangfc281b72017-02-23 15:37:50 +0800885 status = "disabled";
886 };
887
David Wu29b0bfd2018-01-13 14:03:56 +0800888 gmac2io: ethernet@ff540000 {
889 compatible = "rockchip,rk3328-gmac";
890 reg = <0x0 0xff540000 0x0 0x10000>;
David Wu29b0bfd2018-01-13 14:03:56 +0800891 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
892 interrupt-names = "macirq";
893 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
894 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
895 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
896 <&cru PCLK_MAC2IO>;
897 clock-names = "stmmaceth", "mac_clk_rx",
898 "mac_clk_tx", "clk_mac_ref",
899 "clk_mac_refout", "aclk_mac",
900 "pclk_mac";
901 resets = <&cru SRST_GMAC2IO_A>;
902 reset-names = "stmmaceth";
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800903 rockchip,grf = <&grf>;
904 snps,txpbl = <0x4>;
905 status = "disabled";
906 };
907
908 gmac2phy: ethernet@ff550000 {
909 compatible = "rockchip,rk3328-gmac";
910 reg = <0x0 0xff550000 0x0 0x10000>;
911 rockchip,grf = <&grf>;
912 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
913 interrupt-names = "macirq";
914 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
915 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
916 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
917 <&cru SCLK_MAC2PHY_OUT>;
918 clock-names = "stmmaceth", "mac_clk_rx",
919 "mac_clk_tx", "clk_mac_ref",
920 "aclk_mac", "pclk_mac",
921 "clk_macphy";
Peter Robinson7715db32021-07-22 16:20:43 +0100922 resets = <&cru SRST_GMAC2PHY_A>;
923 reset-names = "stmmaceth";
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800924 phy-mode = "rmii";
925 phy-handle = <&phy>;
926 snps,txpbl = <0x4>;
Peter Robinson7715db32021-07-22 16:20:43 +0100927 clock_in_out = "output";
David Wu29b0bfd2018-01-13 14:03:56 +0800928 status = "disabled";
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800929
930 mdio {
931 compatible = "snps,dwmac-mdio";
932 #address-cells = <1>;
933 #size-cells = <0>;
934
Peter Robinson7715db32021-07-22 16:20:43 +0100935 phy: ethernet-phy@0 {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800936 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
937 reg = <0>;
938 clocks = <&cru SCLK_MAC2PHY_OUT>;
939 resets = <&cru SRST_MACPHY>;
940 pinctrl-names = "default";
941 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
942 phy-is-integrated;
943 };
944 };
David Wu29b0bfd2018-01-13 14:03:56 +0800945 };
946
Meng Dongyang4fd2d8f2017-05-17 18:21:46 +0800947 usb_host0_ehci: usb@ff5c0000 {
948 compatible = "generic-ehci";
949 reg = <0x0 0xff5c0000 0x0 0x10000>;
950 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800951 clocks = <&cru HCLK_HOST0>, <&u2phy>;
952 phys = <&u2phy_host>;
953 phy-names = "usb";
Meng Dongyang4fd2d8f2017-05-17 18:21:46 +0800954 status = "disabled";
955 };
956
957 usb_host0_ohci: usb@ff5d0000 {
958 compatible = "generic-ohci";
959 reg = <0x0 0xff5d0000 0x0 0x10000>;
960 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800961 clocks = <&cru HCLK_HOST0>, <&u2phy>;
962 phys = <&u2phy_host>;
963 phy-names = "usb";
Meng Dongyang4fd2d8f2017-05-17 18:21:46 +0800964 status = "disabled";
965 };
966
Peter Robinson7715db32021-07-22 16:20:43 +0100967 usbdrd3: usb@ff600000 {
968 compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
969 reg = <0x0 0xff600000 0x0 0x100000>;
970 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
971 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
972 <&cru ACLK_USB3OTG>;
973 clock-names = "ref_clk", "suspend_clk",
974 "bus_clk";
975 dr_mode = "otg";
976 phy_type = "utmi_wide";
977 snps,dis-del-phy-power-chg-quirk;
978 snps,dis_enblslpm_quirk;
979 snps,dis-tx-ipgap-linecheck-quirk;
980 snps,dis-u2-freeclk-exists-quirk;
981 snps,dis_u2_susphy_quirk;
982 snps,dis_u3_susphy_quirk;
983 status = "disabled";
984 };
985
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800986 /*
Michal Simek50fa1182023-05-17 09:17:16 +0200987 * U-Boot Specific Change
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +0800988 *
989 * The OTG controller must come after the USB host pair for it
990 * to work. This is likely due to lack of support for the USB
991 * PHYs. This must be manually changed after each device tree
992 * sync. There is no clean way to handle this in -u-boot.dtsi
993 * files.
994 */
Meng Dongyangc27dcf92017-06-28 19:22:45 +0800995 usb20_otg: usb@ff580000 {
996 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
997 "snps,dwc2";
998 reg = <0x0 0xff580000 0x0 0x40000>;
999 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001000 clocks = <&cru HCLK_OTG>;
1001 clock-names = "otg";
Meng Dongyangc27dcf92017-06-28 19:22:45 +08001002 dr_mode = "otg";
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001003 g-np-tx-fifo-size = <16>;
1004 g-rx-fifo-size = <280>;
1005 g-tx-fifo-size = <256 128 128 64 32 16>;
1006 phys = <&u2phy_otg>;
1007 phy-names = "usb2-phy";
Kever Yangfc281b72017-02-23 15:37:50 +08001008 status = "disabled";
1009 };
1010
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001011 gic: interrupt-controller@ff811000 {
Kever Yangfc281b72017-02-23 15:37:50 +08001012 compatible = "arm,gic-400";
1013 #interrupt-cells = <3>;
1014 #address-cells = <0>;
1015 interrupt-controller;
1016 reg = <0x0 0xff811000 0 0x1000>,
1017 <0x0 0xff812000 0 0x2000>,
1018 <0x0 0xff814000 0 0x2000>,
1019 <0x0 0xff816000 0 0x2000>;
1020 interrupts = <GIC_PPI 9
1021 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1022 };
1023
1024 pinctrl: pinctrl {
1025 compatible = "rockchip,rk3328-pinctrl";
1026 rockchip,grf = <&grf>;
1027 #address-cells = <2>;
1028 #size-cells = <2>;
1029 ranges;
1030
1031 gpio0: gpio0@ff210000 {
1032 compatible = "rockchip,gpio-bank";
1033 reg = <0x0 0xff210000 0x0 0x100>;
1034 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1035 clocks = <&cru PCLK_GPIO0>;
1036
1037 gpio-controller;
1038 #gpio-cells = <2>;
1039
1040 interrupt-controller;
1041 #interrupt-cells = <2>;
1042 };
1043
1044 gpio1: gpio1@ff220000 {
1045 compatible = "rockchip,gpio-bank";
1046 reg = <0x0 0xff220000 0x0 0x100>;
1047 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1048 clocks = <&cru PCLK_GPIO1>;
1049
1050 gpio-controller;
1051 #gpio-cells = <2>;
1052
1053 interrupt-controller;
1054 #interrupt-cells = <2>;
1055 };
1056
1057 gpio2: gpio2@ff230000 {
1058 compatible = "rockchip,gpio-bank";
1059 reg = <0x0 0xff230000 0x0 0x100>;
1060 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1061 clocks = <&cru PCLK_GPIO2>;
1062
1063 gpio-controller;
1064 #gpio-cells = <2>;
1065
1066 interrupt-controller;
1067 #interrupt-cells = <2>;
1068 };
1069
1070 gpio3: gpio3@ff240000 {
1071 compatible = "rockchip,gpio-bank";
1072 reg = <0x0 0xff240000 0x0 0x100>;
1073 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1074 clocks = <&cru PCLK_GPIO3>;
1075
1076 gpio-controller;
1077 #gpio-cells = <2>;
1078
1079 interrupt-controller;
1080 #interrupt-cells = <2>;
1081 };
1082
1083 pcfg_pull_up: pcfg-pull-up {
1084 bias-pull-up;
1085 };
1086
1087 pcfg_pull_down: pcfg-pull-down {
1088 bias-pull-down;
1089 };
1090
1091 pcfg_pull_none: pcfg-pull-none {
1092 bias-disable;
1093 };
1094
1095 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1096 bias-disable;
1097 drive-strength = <2>;
1098 };
1099
1100 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1101 bias-pull-up;
1102 drive-strength = <2>;
1103 };
1104
1105 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1106 bias-pull-up;
1107 drive-strength = <4>;
1108 };
1109
1110 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1111 bias-disable;
1112 drive-strength = <4>;
1113 };
1114
1115 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1116 bias-pull-down;
1117 drive-strength = <4>;
1118 };
1119
1120 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1121 bias-disable;
1122 drive-strength = <8>;
1123 };
1124
1125 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1126 bias-pull-up;
1127 drive-strength = <8>;
1128 };
1129
1130 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1131 bias-disable;
1132 drive-strength = <12>;
1133 };
1134
1135 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1136 bias-pull-up;
1137 drive-strength = <12>;
1138 };
1139
1140 pcfg_output_high: pcfg-output-high {
1141 output-high;
1142 };
1143
1144 pcfg_output_low: pcfg-output-low {
1145 output-low;
1146 };
1147
1148 pcfg_input_high: pcfg-input-high {
1149 bias-pull-up;
1150 input-enable;
1151 };
1152
1153 pcfg_input: pcfg-input {
1154 input-enable;
1155 };
1156
1157 i2c0 {
1158 i2c0_xfer: i2c0-xfer {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001159 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
1160 <2 RK_PD1 1 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001161 };
1162 };
1163
1164 i2c1 {
1165 i2c1_xfer: i2c1-xfer {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001166 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
1167 <2 RK_PA5 2 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001168 };
1169 };
1170
1171 i2c2 {
1172 i2c2_xfer: i2c2-xfer {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001173 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
1174 <2 RK_PB6 1 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001175 };
1176 };
1177
1178 i2c3 {
1179 i2c3_xfer: i2c3-xfer {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001180 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1181 <0 RK_PA6 2 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001182 };
Peter Robinson7715db32021-07-22 16:20:43 +01001183 i2c3_pins: i2c3-pins {
Kever Yangfc281b72017-02-23 15:37:50 +08001184 rockchip,pins =
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001185 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1186 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001187 };
1188 };
1189
1190 hdmi_i2c {
1191 hdmii2c_xfer: hdmii2c-xfer {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001192 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
1193 <0 RK_PA6 1 &pcfg_pull_none>;
1194 };
1195 };
1196
1197 pdm-0 {
1198 pdmm0_clk: pdmm0-clk {
1199 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
1200 };
1201
1202 pdmm0_fsync: pdmm0-fsync {
1203 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
1204 };
1205
1206 pdmm0_sdi0: pdmm0-sdi0 {
1207 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
1208 };
1209
1210 pdmm0_sdi1: pdmm0-sdi1 {
1211 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
1212 };
1213
1214 pdmm0_sdi2: pdmm0-sdi2 {
1215 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
1216 };
1217
1218 pdmm0_sdi3: pdmm0-sdi3 {
1219 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
1220 };
1221
1222 pdmm0_clk_sleep: pdmm0-clk-sleep {
1223 rockchip,pins =
1224 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
1225 };
1226
1227 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1228 rockchip,pins =
1229 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
1230 };
1231
1232 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1233 rockchip,pins =
1234 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
1235 };
1236
1237 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
Kever Yangfc281b72017-02-23 15:37:50 +08001238 rockchip,pins =
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001239 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1240 };
1241
1242 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1243 rockchip,pins =
1244 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1245 };
1246
1247 pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1248 rockchip,pins =
1249 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
Kever Yangfc281b72017-02-23 15:37:50 +08001250 };
1251 };
1252
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001253 tsadc {
Peter Robinson7715db32021-07-22 16:20:43 +01001254 otp_pin: otp-pin {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001255 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1256 };
1257
1258 otp_out: otp-out {
1259 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
1260 };
1261 };
1262
Kever Yangfc281b72017-02-23 15:37:50 +08001263 uart0 {
1264 uart0_xfer: uart0-xfer {
Peter Robinson7715db32021-07-22 16:20:43 +01001265 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
1266 <1 RK_PB0 1 &pcfg_pull_up>;
Kever Yangfc281b72017-02-23 15:37:50 +08001267 };
1268
1269 uart0_cts: uart0-cts {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001270 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001271 };
1272
1273 uart0_rts: uart0-rts {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001274 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001275 };
1276
Peter Robinson7715db32021-07-22 16:20:43 +01001277 uart0_rts_pin: uart0-rts-pin {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001278 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001279 };
1280 };
1281
1282 uart1 {
1283 uart1_xfer: uart1-xfer {
Peter Robinson7715db32021-07-22 16:20:43 +01001284 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>,
1285 <3 RK_PA6 4 &pcfg_pull_up>;
Kever Yangfc281b72017-02-23 15:37:50 +08001286 };
1287
1288 uart1_cts: uart1-cts {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001289 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001290 };
1291
1292 uart1_rts: uart1-rts {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001293 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001294 };
1295
Peter Robinson7715db32021-07-22 16:20:43 +01001296 uart1_rts_pin: uart1-rts-pin {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001297 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001298 };
1299 };
1300
1301 uart2-0 {
1302 uart2m0_xfer: uart2m0-xfer {
Peter Robinson7715db32021-07-22 16:20:43 +01001303 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>,
1304 <1 RK_PA1 2 &pcfg_pull_up>;
Kever Yangfc281b72017-02-23 15:37:50 +08001305 };
1306 };
1307
1308 uart2-1 {
1309 uart2m1_xfer: uart2m1-xfer {
Peter Robinson7715db32021-07-22 16:20:43 +01001310 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
1311 <2 RK_PA1 1 &pcfg_pull_up>;
Kever Yangfc281b72017-02-23 15:37:50 +08001312 };
1313 };
1314
1315 spi0-0 {
1316 spi0m0_clk: spi0m0-clk {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001317 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
Kever Yangfc281b72017-02-23 15:37:50 +08001318 };
1319
1320 spi0m0_cs0: spi0m0-cs0 {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001321 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
Kever Yangfc281b72017-02-23 15:37:50 +08001322 };
1323
1324 spi0m0_tx: spi0m0-tx {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001325 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
Kever Yangfc281b72017-02-23 15:37:50 +08001326 };
1327
1328 spi0m0_rx: spi0m0-rx {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001329 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
Kever Yangfc281b72017-02-23 15:37:50 +08001330 };
1331
1332 spi0m0_cs1: spi0m0-cs1 {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001333 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
Kever Yangfc281b72017-02-23 15:37:50 +08001334 };
1335 };
1336
1337 spi0-1 {
1338 spi0m1_clk: spi0m1-clk {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001339 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
Kever Yangfc281b72017-02-23 15:37:50 +08001340 };
1341
1342 spi0m1_cs0: spi0m1-cs0 {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001343 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
Kever Yangfc281b72017-02-23 15:37:50 +08001344 };
1345
1346 spi0m1_tx: spi0m1-tx {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001347 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
Kever Yangfc281b72017-02-23 15:37:50 +08001348 };
1349
1350 spi0m1_rx: spi0m1-rx {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001351 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
Kever Yangfc281b72017-02-23 15:37:50 +08001352 };
1353
1354 spi0m1_cs1: spi0m1-cs1 {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001355 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
Kever Yangfc281b72017-02-23 15:37:50 +08001356 };
1357 };
1358
1359 spi0-2 {
1360 spi0m2_clk: spi0m2-clk {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001361 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
Kever Yangfc281b72017-02-23 15:37:50 +08001362 };
1363
1364 spi0m2_cs0: spi0m2-cs0 {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001365 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
Kever Yangfc281b72017-02-23 15:37:50 +08001366 };
1367
1368 spi0m2_tx: spi0m2-tx {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001369 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
Kever Yangfc281b72017-02-23 15:37:50 +08001370 };
1371
1372 spi0m2_rx: spi0m2-rx {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001373 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
Kever Yangfc281b72017-02-23 15:37:50 +08001374 };
1375 };
1376
1377 i2s1 {
1378 i2s1_mclk: i2s1-mclk {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001379 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001380 };
1381
1382 i2s1_sclk: i2s1-sclk {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001383 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001384 };
1385
1386 i2s1_lrckrx: i2s1-lrckrx {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001387 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001388 };
1389
1390 i2s1_lrcktx: i2s1-lrcktx {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001391 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001392 };
1393
1394 i2s1_sdi: i2s1-sdi {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001395 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001396 };
1397
1398 i2s1_sdo: i2s1-sdo {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001399 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001400 };
1401
1402 i2s1_sdio1: i2s1-sdio1 {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001403 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001404 };
1405
1406 i2s1_sdio2: i2s1-sdio2 {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001407 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001408 };
1409
1410 i2s1_sdio3: i2s1-sdio3 {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001411 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001412 };
1413
1414 i2s1_sleep: i2s1-sleep {
1415 rockchip,pins =
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001416 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1417 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1418 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1419 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1420 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1421 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1422 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1423 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1424 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
Kever Yangfc281b72017-02-23 15:37:50 +08001425 };
1426 };
1427
1428 i2s2-0 {
1429 i2s2m0_mclk: i2s2m0-mclk {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001430 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001431 };
1432
1433 i2s2m0_sclk: i2s2m0-sclk {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001434 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001435 };
1436
1437 i2s2m0_lrckrx: i2s2m0-lrckrx {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001438 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001439 };
1440
1441 i2s2m0_lrcktx: i2s2m0-lrcktx {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001442 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001443 };
1444
1445 i2s2m0_sdi: i2s2m0-sdi {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001446 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001447 };
1448
1449 i2s2m0_sdo: i2s2m0-sdo {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001450 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001451 };
1452
1453 i2s2m0_sleep: i2s2m0-sleep {
1454 rockchip,pins =
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001455 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1456 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1457 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1458 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1459 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1460 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
Kever Yangfc281b72017-02-23 15:37:50 +08001461 };
1462 };
1463
1464 i2s2-1 {
1465 i2s2m1_mclk: i2s2m1-mclk {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001466 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001467 };
1468
1469 i2s2m1_sclk: i2s2m1-sclk {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001470 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001471 };
1472
1473 i2s2m1_lrckrx: i2sm1-lrckrx {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001474 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001475 };
1476
1477 i2s2m1_lrcktx: i2s2m1-lrcktx {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001478 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001479 };
1480
1481 i2s2m1_sdi: i2s2m1-sdi {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001482 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001483 };
1484
1485 i2s2m1_sdo: i2s2m1-sdo {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001486 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001487 };
1488
1489 i2s2m1_sleep: i2s2m1-sleep {
1490 rockchip,pins =
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001491 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1492 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1493 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1494 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1495 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
Kever Yangfc281b72017-02-23 15:37:50 +08001496 };
1497 };
1498
1499 spdif-0 {
1500 spdifm0_tx: spdifm0-tx {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001501 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001502 };
1503 };
1504
1505 spdif-1 {
1506 spdifm1_tx: spdifm1-tx {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001507 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001508 };
1509 };
1510
1511 spdif-2 {
1512 spdifm2_tx: spdifm2-tx {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001513 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001514 };
1515 };
1516
1517 sdmmc0-0 {
1518 sdmmc0m0_pwren: sdmmc0m0-pwren {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001519 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001520 };
1521
Peter Robinson7715db32021-07-22 16:20:43 +01001522 sdmmc0m0_pin: sdmmc0m0-pin {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001523 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001524 };
1525 };
1526
1527 sdmmc0-1 {
1528 sdmmc0m1_pwren: sdmmc0m1-pwren {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001529 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001530 };
1531
Peter Robinson7715db32021-07-22 16:20:43 +01001532 sdmmc0m1_pin: sdmmc0m1-pin {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001533 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001534 };
1535 };
1536
1537 sdmmc0 {
1538 sdmmc0_clk: sdmmc0-clk {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001539 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001540 };
1541
1542 sdmmc0_cmd: sdmmc0-cmd {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001543 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001544 };
1545
1546 sdmmc0_dectn: sdmmc0-dectn {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001547 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001548 };
1549
1550 sdmmc0_wrprt: sdmmc0-wrprt {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001551 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001552 };
1553
1554 sdmmc0_bus1: sdmmc0-bus1 {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001555 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001556 };
1557
1558 sdmmc0_bus4: sdmmc0-bus4 {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001559 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>,
1560 <1 RK_PA1 1 &pcfg_pull_up_8ma>,
1561 <1 RK_PA2 1 &pcfg_pull_up_8ma>,
1562 <1 RK_PA3 1 &pcfg_pull_up_8ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001563 };
1564
Peter Robinson7715db32021-07-22 16:20:43 +01001565 sdmmc0_pins: sdmmc0-pins {
Kever Yangfc281b72017-02-23 15:37:50 +08001566 rockchip,pins =
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001567 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1568 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1569 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1570 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1571 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1572 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1573 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1574 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001575 };
1576 };
1577
1578 sdmmc0ext {
1579 sdmmc0ext_clk: sdmmc0ext-clk {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001580 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001581 };
1582
1583 sdmmc0ext_cmd: sdmmc0ext-cmd {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001584 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001585 };
1586
1587 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001588 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001589 };
1590
1591 sdmmc0ext_dectn: sdmmc0ext-dectn {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001592 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001593 };
1594
1595 sdmmc0ext_bus1: sdmmc0ext-bus1 {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001596 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001597 };
1598
1599 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1600 rockchip,pins =
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001601 <3 RK_PA4 3 &pcfg_pull_up_4ma>,
1602 <3 RK_PA5 3 &pcfg_pull_up_4ma>,
1603 <3 RK_PA6 3 &pcfg_pull_up_4ma>,
1604 <3 RK_PA7 3 &pcfg_pull_up_4ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001605 };
1606
Peter Robinson7715db32021-07-22 16:20:43 +01001607 sdmmc0ext_pins: sdmmc0ext-pins {
Kever Yangfc281b72017-02-23 15:37:50 +08001608 rockchip,pins =
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001609 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1610 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1611 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1612 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1613 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1614 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1615 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1616 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001617 };
1618 };
1619
1620 sdmmc1 {
1621 sdmmc1_clk: sdmmc1-clk {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001622 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001623 };
1624
1625 sdmmc1_cmd: sdmmc1-cmd {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001626 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001627 };
1628
1629 sdmmc1_pwren: sdmmc1-pwren {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001630 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001631 };
1632
1633 sdmmc1_wrprt: sdmmc1-wrprt {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001634 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001635 };
1636
1637 sdmmc1_dectn: sdmmc1-dectn {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001638 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001639 };
1640
1641 sdmmc1_bus1: sdmmc1-bus1 {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001642 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001643 };
1644
1645 sdmmc1_bus4: sdmmc1-bus4 {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001646 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
1647 <1 RK_PB7 1 &pcfg_pull_up_8ma>,
1648 <1 RK_PC0 1 &pcfg_pull_up_8ma>,
1649 <1 RK_PC1 1 &pcfg_pull_up_8ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001650 };
1651
Peter Robinson7715db32021-07-22 16:20:43 +01001652 sdmmc1_pins: sdmmc1-pins {
Kever Yangfc281b72017-02-23 15:37:50 +08001653 rockchip,pins =
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001654 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1655 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1656 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1657 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1658 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1659 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1660 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1661 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1662 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001663 };
1664 };
1665
1666 emmc {
1667 emmc_clk: emmc-clk {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001668 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001669 };
1670
1671 emmc_cmd: emmc-cmd {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001672 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001673 };
1674
1675 emmc_pwren: emmc-pwren {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001676 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001677 };
1678
1679 emmc_rstnout: emmc-rstnout {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001680 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001681 };
1682
1683 emmc_bus1: emmc-bus1 {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001684 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001685 };
1686
1687 emmc_bus4: emmc-bus4 {
1688 rockchip,pins =
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001689 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1690 <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1691 <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1692 <2 RK_PD6 2 &pcfg_pull_up_12ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001693 };
1694
1695 emmc_bus8: emmc-bus8 {
1696 rockchip,pins =
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001697 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1698 <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1699 <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1700 <2 RK_PD6 2 &pcfg_pull_up_12ma>,
1701 <2 RK_PD7 2 &pcfg_pull_up_12ma>,
1702 <3 RK_PC0 2 &pcfg_pull_up_12ma>,
1703 <3 RK_PC1 2 &pcfg_pull_up_12ma>,
1704 <3 RK_PC2 2 &pcfg_pull_up_12ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001705 };
1706 };
1707
1708 pwm0 {
1709 pwm0_pin: pwm0-pin {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001710 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001711 };
1712 };
1713
1714 pwm1 {
1715 pwm1_pin: pwm1-pin {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001716 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001717 };
1718 };
1719
1720 pwm2 {
1721 pwm2_pin: pwm2-pin {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001722 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001723 };
1724 };
1725
1726 pwmir {
1727 pwmir_pin: pwmir-pin {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001728 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001729 };
1730 };
1731
Kever Yangfc281b72017-02-23 15:37:50 +08001732 gmac-1 {
1733 rgmiim1_pins: rgmiim1-pins {
1734 rockchip,pins =
1735 /* mac_txclk */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001736 <1 RK_PB4 2 &pcfg_pull_none_8ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001737 /* mac_rxclk */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001738 <1 RK_PB5 2 &pcfg_pull_none_4ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001739 /* mac_mdio */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001740 <1 RK_PC3 2 &pcfg_pull_none_4ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001741 /* mac_txen */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001742 <1 RK_PD1 2 &pcfg_pull_none_8ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001743 /* mac_clk */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001744 <1 RK_PC5 2 &pcfg_pull_none_4ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001745 /* mac_rxdv */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001746 <1 RK_PC6 2 &pcfg_pull_none_4ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001747 /* mac_mdc */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001748 <1 RK_PC7 2 &pcfg_pull_none_4ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001749 /* mac_rxd1 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001750 <1 RK_PB2 2 &pcfg_pull_none_4ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001751 /* mac_rxd0 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001752 <1 RK_PB3 2 &pcfg_pull_none_4ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001753 /* mac_txd1 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001754 <1 RK_PB0 2 &pcfg_pull_none_8ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001755 /* mac_txd0 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001756 <1 RK_PB1 2 &pcfg_pull_none_8ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001757 /* mac_rxd3 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001758 <1 RK_PB6 2 &pcfg_pull_none_4ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001759 /* mac_rxd2 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001760 <1 RK_PB7 2 &pcfg_pull_none_4ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001761 /* mac_txd3 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001762 <1 RK_PC0 2 &pcfg_pull_none_8ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001763 /* mac_txd2 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001764 <1 RK_PC1 2 &pcfg_pull_none_8ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001765
1766 /* mac_txclk */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001767 <0 RK_PB0 1 &pcfg_pull_none_8ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001768 /* mac_txen */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001769 <0 RK_PB4 1 &pcfg_pull_none_8ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001770 /* mac_clk */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001771 <0 RK_PD0 1 &pcfg_pull_none_4ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001772 /* mac_txd1 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001773 <0 RK_PC0 1 &pcfg_pull_none_8ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001774 /* mac_txd0 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001775 <0 RK_PC1 1 &pcfg_pull_none_8ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001776 /* mac_txd3 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001777 <0 RK_PC7 1 &pcfg_pull_none_8ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001778 /* mac_txd2 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001779 <0 RK_PC6 1 &pcfg_pull_none_8ma>;
Kever Yangfc281b72017-02-23 15:37:50 +08001780 };
1781
1782 rmiim1_pins: rmiim1-pins {
1783 rockchip,pins =
1784 /* mac_mdio */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001785 <1 RK_PC3 2 &pcfg_pull_none_2ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001786 /* mac_txen */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001787 <1 RK_PD1 2 &pcfg_pull_none_12ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001788 /* mac_clk */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001789 <1 RK_PC5 2 &pcfg_pull_none_2ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001790 /* mac_rxer */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001791 <1 RK_PD0 2 &pcfg_pull_none_2ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001792 /* mac_rxdv */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001793 <1 RK_PC6 2 &pcfg_pull_none_2ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001794 /* mac_mdc */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001795 <1 RK_PC7 2 &pcfg_pull_none_2ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001796 /* mac_rxd1 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001797 <1 RK_PB2 2 &pcfg_pull_none_2ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001798 /* mac_rxd0 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001799 <1 RK_PB3 2 &pcfg_pull_none_2ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001800 /* mac_txd1 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001801 <1 RK_PB0 2 &pcfg_pull_none_12ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001802 /* mac_txd0 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001803 <1 RK_PB1 2 &pcfg_pull_none_12ma>,
Kever Yangfc281b72017-02-23 15:37:50 +08001804
1805 /* mac_mdio */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001806 <0 RK_PB3 1 &pcfg_pull_none>,
Kever Yangfc281b72017-02-23 15:37:50 +08001807 /* mac_txen */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001808 <0 RK_PB4 1 &pcfg_pull_none>,
Kever Yangfc281b72017-02-23 15:37:50 +08001809 /* mac_clk */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001810 <0 RK_PD0 1 &pcfg_pull_none>,
Kever Yangfc281b72017-02-23 15:37:50 +08001811 /* mac_mdc */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001812 <0 RK_PC3 1 &pcfg_pull_none>,
Kever Yangfc281b72017-02-23 15:37:50 +08001813 /* mac_txd1 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001814 <0 RK_PC0 1 &pcfg_pull_none>,
Kever Yangfc281b72017-02-23 15:37:50 +08001815 /* mac_txd0 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001816 <0 RK_PC1 1 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001817 };
1818 };
1819
1820 gmac2phy {
Kever Yangfc281b72017-02-23 15:37:50 +08001821 fephyled_speed10: fephyled-speed10 {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001822 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001823 };
1824
1825 fephyled_duplex: fephyled-duplex {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001826 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001827 };
1828
Kever Yangfc281b72017-02-23 15:37:50 +08001829 fephyled_rxm1: fephyled-rxm1 {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001830 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001831 };
1832
1833 fephyled_txm1: fephyled-txm1 {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001834 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001835 };
1836
1837 fephyled_linkm1: fephyled-linkm1 {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001838 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001839 };
1840 };
1841
1842 tsadc_pin {
1843 tsadc_int: tsadc-int {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001844 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001845 };
Peter Robinson7715db32021-07-22 16:20:43 +01001846 tsadc_pin: tsadc-pin {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001847 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001848 };
1849 };
1850
1851 hdmi_pin {
1852 hdmi_cec: hdmi-cec {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001853 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001854 };
1855
1856 hdmi_hpd: hdmi-hpd {
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001857 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
Kever Yangfc281b72017-02-23 15:37:50 +08001858 };
1859 };
1860
1861 cif-0 {
1862 dvp_d2d9_m0:dvp-d2d9-m0 {
1863 rockchip,pins =
1864 /* cif_d0 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001865 <3 RK_PA4 2 &pcfg_pull_none>,
Kever Yangfc281b72017-02-23 15:37:50 +08001866 /* cif_d1 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001867 <3 RK_PA5 2 &pcfg_pull_none>,
Kever Yangfc281b72017-02-23 15:37:50 +08001868 /* cif_d2 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001869 <3 RK_PA6 2 &pcfg_pull_none>,
Kever Yangfc281b72017-02-23 15:37:50 +08001870 /* cif_d3 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001871 <3 RK_PA7 2 &pcfg_pull_none>,
Kever Yangfc281b72017-02-23 15:37:50 +08001872 /* cif_d4 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001873 <3 RK_PB0 2 &pcfg_pull_none>,
Kever Yangfc281b72017-02-23 15:37:50 +08001874 /* cif_d5m0 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001875 <3 RK_PB1 2 &pcfg_pull_none>,
Kever Yangfc281b72017-02-23 15:37:50 +08001876 /* cif_d6m0 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001877 <3 RK_PB2 2 &pcfg_pull_none>,
Kever Yangfc281b72017-02-23 15:37:50 +08001878 /* cif_d7m0 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001879 <3 RK_PB3 2 &pcfg_pull_none>,
Kever Yangfc281b72017-02-23 15:37:50 +08001880 /* cif_href */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001881 <3 RK_PA1 2 &pcfg_pull_none>,
Kever Yangfc281b72017-02-23 15:37:50 +08001882 /* cif_vsync */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001883 <3 RK_PA0 2 &pcfg_pull_none>,
Kever Yangfc281b72017-02-23 15:37:50 +08001884 /* cif_clkoutm0 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001885 <3 RK_PA3 2 &pcfg_pull_none>,
Kever Yangfc281b72017-02-23 15:37:50 +08001886 /* cif_clkin */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001887 <3 RK_PA2 2 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001888 };
1889 };
1890
1891 cif-1 {
1892 dvp_d2d9_m1:dvp-d2d9-m1 {
1893 rockchip,pins =
1894 /* cif_d0 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001895 <3 RK_PA4 2 &pcfg_pull_none>,
Kever Yangfc281b72017-02-23 15:37:50 +08001896 /* cif_d1 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001897 <3 RK_PA5 2 &pcfg_pull_none>,
Kever Yangfc281b72017-02-23 15:37:50 +08001898 /* cif_d2 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001899 <3 RK_PA6 2 &pcfg_pull_none>,
Kever Yangfc281b72017-02-23 15:37:50 +08001900 /* cif_d3 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001901 <3 RK_PA7 2 &pcfg_pull_none>,
Kever Yangfc281b72017-02-23 15:37:50 +08001902 /* cif_d4 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001903 <3 RK_PB0 2 &pcfg_pull_none>,
Kever Yangfc281b72017-02-23 15:37:50 +08001904 /* cif_d5m1 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001905 <2 RK_PC0 4 &pcfg_pull_none>,
Kever Yangfc281b72017-02-23 15:37:50 +08001906 /* cif_d6m1 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001907 <2 RK_PC1 4 &pcfg_pull_none>,
Kever Yangfc281b72017-02-23 15:37:50 +08001908 /* cif_d7m1 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001909 <2 RK_PC2 4 &pcfg_pull_none>,
Kever Yangfc281b72017-02-23 15:37:50 +08001910 /* cif_href */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001911 <3 RK_PA1 2 &pcfg_pull_none>,
Kever Yangfc281b72017-02-23 15:37:50 +08001912 /* cif_vsync */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001913 <3 RK_PA0 2 &pcfg_pull_none>,
Kever Yangfc281b72017-02-23 15:37:50 +08001914 /* cif_clkoutm1 */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001915 <2 RK_PB7 4 &pcfg_pull_none>,
Kever Yangfc281b72017-02-23 15:37:50 +08001916 /* cif_clkin */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +08001917 <3 RK_PA2 2 &pcfg_pull_none>;
Kever Yangfc281b72017-02-23 15:37:50 +08001918 };
1919 };
1920 };
1921};