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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk1fe2c702003-03-06 21:55:29 +00002/*
3 * (C) Copyright 2001, 2002, 2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Keith Outwater, keith_outwater@mvis.com`
6 * Steven Scholz, steven.scholz@imc-berlin.de
wdenk1fe2c702003-03-06 21:55:29 +00007 */
8
9/*
10 * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
Markus Niebel90491f22014-07-21 11:06:16 +020011 * DS1307 and DS1338/9 Real Time Clock (RTC).
wdenk1fe2c702003-03-06 21:55:29 +000012 *
13 * based on ds1337.c
14 */
15
16#include <common.h>
17#include <command.h>
Chris Packham97a3e912017-04-29 15:20:29 +120018#include <dm.h>
wdenk1fe2c702003-03-06 21:55:29 +000019#include <rtc.h>
20#include <i2c.h>
21
Chris Packham97a3e912017-04-29 15:20:29 +120022enum ds_type {
23 ds_1307,
24 ds_1337,
25 ds_1340,
26 mcp794xx,
27};
wdenk1fe2c702003-03-06 21:55:29 +000028
29/*
30 * RTC register addresses
31 */
32#define RTC_SEC_REG_ADDR 0x00
33#define RTC_MIN_REG_ADDR 0x01
34#define RTC_HR_REG_ADDR 0x02
35#define RTC_DAY_REG_ADDR 0x03
36#define RTC_DATE_REG_ADDR 0x04
37#define RTC_MON_REG_ADDR 0x05
38#define RTC_YR_REG_ADDR 0x06
39#define RTC_CTL_REG_ADDR 0x07
40
41#define RTC_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */
42
43#define RTC_CTL_BIT_RS0 0x01 /* Rate select 0 */
44#define RTC_CTL_BIT_RS1 0x02 /* Rate select 1 */
45#define RTC_CTL_BIT_SQWE 0x10 /* Square Wave Enable */
46#define RTC_CTL_BIT_OUT 0x80 /* Output Control */
47
Andy Flemingb9b8c2f2015-10-21 18:59:06 -050048/* MCP7941X-specific bits */
49#define MCP7941X_BIT_ST 0x80
50#define MCP7941X_BIT_VBATEN 0x08
51
Chris Packham97a3e912017-04-29 15:20:29 +120052#ifndef CONFIG_DM_RTC
53
Chris Packham97a3e912017-04-29 15:20:29 +120054/*---------------------------------------------------------------------*/
55#undef DEBUG_RTC
56
57#ifdef DEBUG_RTC
58#define DEBUGR(fmt, args...) printf(fmt, ##args)
59#else
60#define DEBUGR(fmt, args...)
61#endif
62/*---------------------------------------------------------------------*/
63
64#ifndef CONFIG_SYS_I2C_RTC_ADDR
65# define CONFIG_SYS_I2C_RTC_ADDR 0x68
66#endif
67
68#if defined(CONFIG_RTC_DS1307) && (CONFIG_SYS_I2C_SPEED > 100000)
69# error The DS1307 is specified only up to 100kHz!
70#endif
71
wdenk1fe2c702003-03-06 21:55:29 +000072static uchar rtc_read (uchar reg);
73static void rtc_write (uchar reg, uchar val);
wdenk1fe2c702003-03-06 21:55:29 +000074
75/*
76 * Get the current time from the RTC
77 */
Yuri Tikhonov9bacd942008-03-20 17:56:04 +030078int rtc_get (struct rtc_time *tmp)
wdenk1fe2c702003-03-06 21:55:29 +000079{
Yuri Tikhonov9bacd942008-03-20 17:56:04 +030080 int rel = 0;
wdenk1fe2c702003-03-06 21:55:29 +000081 uchar sec, min, hour, mday, wday, mon, year;
82
Andy Flemingb9b8c2f2015-10-21 18:59:06 -050083#ifdef CONFIG_RTC_MCP79411
84read_rtc:
85#endif
wdenk1fe2c702003-03-06 21:55:29 +000086 sec = rtc_read (RTC_SEC_REG_ADDR);
87 min = rtc_read (RTC_MIN_REG_ADDR);
88 hour = rtc_read (RTC_HR_REG_ADDR);
89 wday = rtc_read (RTC_DAY_REG_ADDR);
90 mday = rtc_read (RTC_DATE_REG_ADDR);
91 mon = rtc_read (RTC_MON_REG_ADDR);
92 year = rtc_read (RTC_YR_REG_ADDR);
93
94 DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
95 "hr: %02x min: %02x sec: %02x\n",
96 year, mon, mday, wday, hour, min, sec);
97
Andy Flemingb9b8c2f2015-10-21 18:59:06 -050098#ifdef CONFIG_RTC_DS1307
wdenk1fe2c702003-03-06 21:55:29 +000099 if (sec & RTC_SEC_BIT_CH) {
100 printf ("### Warning: RTC oscillator has stopped\n");
101 /* clear the CH flag */
102 rtc_write (RTC_SEC_REG_ADDR,
103 rtc_read (RTC_SEC_REG_ADDR) & ~RTC_SEC_BIT_CH);
Yuri Tikhonov9bacd942008-03-20 17:56:04 +0300104 rel = -1;
wdenk1fe2c702003-03-06 21:55:29 +0000105 }
Andy Flemingb9b8c2f2015-10-21 18:59:06 -0500106#endif
107
108#ifdef CONFIG_RTC_MCP79411
109 /* make sure that the backup battery is enabled */
110 if (!(wday & MCP7941X_BIT_VBATEN)) {
111 rtc_write(RTC_DAY_REG_ADDR,
112 wday | MCP7941X_BIT_VBATEN);
113 }
wdenk57b2d802003-06-27 21:31:46 +0000114
Andy Flemingb9b8c2f2015-10-21 18:59:06 -0500115 /* clock halted? turn it on, so clock can tick. */
116 if (!(sec & MCP7941X_BIT_ST)) {
117 rtc_write(RTC_SEC_REG_ADDR, MCP7941X_BIT_ST);
118 printf("Started RTC\n");
119 goto read_rtc;
120 }
121#endif
122
123
wdenk1fe2c702003-03-06 21:55:29 +0000124 tmp->tm_sec = bcd2bin (sec & 0x7F);
125 tmp->tm_min = bcd2bin (min & 0x7F);
126 tmp->tm_hour = bcd2bin (hour & 0x3F);
127 tmp->tm_mday = bcd2bin (mday & 0x3F);
128 tmp->tm_mon = bcd2bin (mon & 0x1F);
129 tmp->tm_year = bcd2bin (year) + ( bcd2bin (year) >= 70 ? 1900 : 2000);
130 tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
131 tmp->tm_yday = 0;
132 tmp->tm_isdst= 0;
133
134 DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
135 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
136 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
Yuri Tikhonov9bacd942008-03-20 17:56:04 +0300137
138 return rel;
wdenk1fe2c702003-03-06 21:55:29 +0000139}
140
141
142/*
143 * Set the RTC
144 */
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +0200145int rtc_set (struct rtc_time *tmp)
wdenk1fe2c702003-03-06 21:55:29 +0000146{
147 DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
148 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
149 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
150
151 if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
152 printf("WARNING: year should be between 1970 and 2069!\n");
wdenk57b2d802003-06-27 21:31:46 +0000153
wdenk1fe2c702003-03-06 21:55:29 +0000154 rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
155 rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon));
Andy Flemingb9b8c2f2015-10-21 18:59:06 -0500156#ifdef CONFIG_RTC_MCP79411
157 rtc_write (RTC_DAY_REG_ADDR,
158 bin2bcd (tmp->tm_wday + 1) | MCP7941X_BIT_VBATEN);
159#else
wdenk1fe2c702003-03-06 21:55:29 +0000160 rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
Andy Flemingb9b8c2f2015-10-21 18:59:06 -0500161#endif
wdenk1fe2c702003-03-06 21:55:29 +0000162 rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
163 rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
164 rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
Andy Flemingb9b8c2f2015-10-21 18:59:06 -0500165#ifdef CONFIG_RTC_MCP79411
166 rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec) | MCP7941X_BIT_ST);
167#else
wdenk1fe2c702003-03-06 21:55:29 +0000168 rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
Andy Flemingb9b8c2f2015-10-21 18:59:06 -0500169#endif
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +0200170
171 return 0;
wdenk1fe2c702003-03-06 21:55:29 +0000172}
173
174
175/*
wdenk57b2d802003-06-27 21:31:46 +0000176 * Reset the RTC. We setting the date back to 1970-01-01.
177 * We also enable the oscillator output on the SQW/OUT pin and program
wdenk1fe2c702003-03-06 21:55:29 +0000178 * it for 32,768 Hz output. Note that according to the datasheet, turning
179 * on the square wave output increases the current drain on the backup
180 * battery to something between 480nA and 800nA.
181 */
182void rtc_reset (void)
183{
wdenk1fe2c702003-03-06 21:55:29 +0000184 rtc_write (RTC_SEC_REG_ADDR, 0x00); /* clearing Clock Halt */
185 rtc_write (RTC_CTL_REG_ADDR, RTC_CTL_BIT_SQWE | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS0);
wdenk1fe2c702003-03-06 21:55:29 +0000186}
187
188
189/*
190 * Helper functions
191 */
192
193static
194uchar rtc_read (uchar reg)
195{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200196 return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
wdenk1fe2c702003-03-06 21:55:29 +0000197}
198
199
200static void rtc_write (uchar reg, uchar val)
201{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200202 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
wdenk1fe2c702003-03-06 21:55:29 +0000203}
Chris Packham97a3e912017-04-29 15:20:29 +1200204
Chris Packham97a3e912017-04-29 15:20:29 +1200205#endif /* !CONFIG_DM_RTC */
206
207#ifdef CONFIG_DM_RTC
208static int ds1307_rtc_set(struct udevice *dev, const struct rtc_time *tm)
209{
210 int ret;
211 uchar buf[7];
212 enum ds_type type = dev_get_driver_data(dev);
213
214 debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
215 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
216 tm->tm_hour, tm->tm_min, tm->tm_sec);
217
218 if (tm->tm_year < 1970 || tm->tm_year > 2069)
219 printf("WARNING: year should be between 1970 and 2069!\n");
220
221 buf[RTC_YR_REG_ADDR] = bin2bcd(tm->tm_year % 100);
222 buf[RTC_MON_REG_ADDR] = bin2bcd(tm->tm_mon);
223 buf[RTC_DAY_REG_ADDR] = bin2bcd(tm->tm_wday + 1);
224 buf[RTC_DATE_REG_ADDR] = bin2bcd(tm->tm_mday);
225 buf[RTC_HR_REG_ADDR] = bin2bcd(tm->tm_hour);
226 buf[RTC_MIN_REG_ADDR] = bin2bcd(tm->tm_min);
227 buf[RTC_SEC_REG_ADDR] = bin2bcd(tm->tm_sec);
228
229 if (type == mcp794xx) {
230 buf[RTC_DAY_REG_ADDR] |= MCP7941X_BIT_VBATEN;
231 buf[RTC_SEC_REG_ADDR] |= MCP7941X_BIT_ST;
232 }
233
234 ret = dm_i2c_write(dev, 0, buf, sizeof(buf));
235 if (ret < 0)
236 return ret;
237
238 return 0;
239}
240
241static int ds1307_rtc_get(struct udevice *dev, struct rtc_time *tm)
242{
243 int ret;
244 uchar buf[7];
245 enum ds_type type = dev_get_driver_data(dev);
246
247read_rtc:
248 ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
249 if (ret < 0)
250 return ret;
251
252 if (type == ds_1307) {
253 if (buf[RTC_SEC_REG_ADDR] & RTC_SEC_BIT_CH) {
254 printf("### Warning: RTC oscillator has stopped\n");
255 /* clear the CH flag */
256 buf[RTC_SEC_REG_ADDR] &= ~RTC_SEC_BIT_CH;
257 dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR,
258 buf[RTC_SEC_REG_ADDR]);
259 return -1;
260 }
261 }
262
263 if (type == mcp794xx) {
264 /* make sure that the backup battery is enabled */
265 if (!(buf[RTC_DAY_REG_ADDR] & MCP7941X_BIT_VBATEN)) {
266 dm_i2c_reg_write(dev, RTC_DAY_REG_ADDR,
267 buf[RTC_DAY_REG_ADDR] |
268 MCP7941X_BIT_VBATEN);
269 }
270
271 /* clock halted? turn it on, so clock can tick. */
272 if (!(buf[RTC_SEC_REG_ADDR] & MCP7941X_BIT_ST)) {
273 dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR,
274 MCP7941X_BIT_ST);
275 printf("Started RTC\n");
276 goto read_rtc;
277 }
278 }
279
280 tm->tm_sec = bcd2bin(buf[RTC_SEC_REG_ADDR] & 0x7F);
281 tm->tm_min = bcd2bin(buf[RTC_MIN_REG_ADDR] & 0x7F);
282 tm->tm_hour = bcd2bin(buf[RTC_HR_REG_ADDR] & 0x3F);
283 tm->tm_mday = bcd2bin(buf[RTC_DATE_REG_ADDR] & 0x3F);
284 tm->tm_mon = bcd2bin(buf[RTC_MON_REG_ADDR] & 0x1F);
285 tm->tm_year = bcd2bin(buf[RTC_YR_REG_ADDR]) +
286 (bcd2bin(buf[RTC_YR_REG_ADDR]) >= 70 ?
287 1900 : 2000);
288 tm->tm_wday = bcd2bin((buf[RTC_DAY_REG_ADDR] - 1) & 0x07);
289 tm->tm_yday = 0;
290 tm->tm_isdst = 0;
291
292 debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
293 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
294 tm->tm_hour, tm->tm_min, tm->tm_sec);
295
296 return 0;
297}
298
299static int ds1307_rtc_reset(struct udevice *dev)
300{
301 int ret;
Chris Packham97a3e912017-04-29 15:20:29 +1200302
303 /* clear Clock Halt */
304 ret = dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR, 0x00);
305 if (ret < 0)
306 return ret;
307 ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR,
308 RTC_CTL_BIT_SQWE | RTC_CTL_BIT_RS1 |
309 RTC_CTL_BIT_RS0);
310 if (ret < 0)
311 return ret;
312
Chris Packham97a3e912017-04-29 15:20:29 +1200313 return 0;
314}
315
316static int ds1307_probe(struct udevice *dev)
317{
318 i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS |
319 DM_I2C_CHIP_WR_ADDRESS);
320
321 return 0;
322}
323
324static const struct rtc_ops ds1307_rtc_ops = {
325 .get = ds1307_rtc_get,
326 .set = ds1307_rtc_set,
327 .reset = ds1307_rtc_reset,
328};
329
330static const struct udevice_id ds1307_rtc_ids[] = {
331 { .compatible = "dallas,ds1307", .data = ds_1307 },
332 { .compatible = "dallas,ds1337", .data = ds_1337 },
333 { .compatible = "dallas,ds1340", .data = ds_1340 },
334 { .compatible = "microchip,mcp7941x", .data = mcp794xx },
335 { }
336};
337
338U_BOOT_DRIVER(rtc_ds1307) = {
339 .name = "rtc-ds1307",
340 .id = UCLASS_RTC,
341 .probe = ds1307_probe,
342 .of_match = ds1307_rtc_ids,
343 .ops = &ds1307_rtc_ops,
344};
345#endif /* CONFIG_DM_RTC */