blob: c36e90cd22ed4e74254f9265349ed4a36b9c9cb9 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stefan Agner13011752017-04-11 11:12:14 +05302/*
3 * Copyright 2017 Toradex AG
4 *
5 * FSL DCU platform driver
Stefan Agner13011752017-04-11 11:12:14 +05306 */
7
8#include <asm/arch/crm_regs.h>
9#include <asm/io.h>
10#include <common.h>
11#include <fsl_dcu_fb.h>
12#include "div64.h"
13
Stefan Agner13011752017-04-11 11:12:14 +053014unsigned int dcu_set_pixel_clock(unsigned int pixclock)
15{
16 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
17 unsigned long long div;
18
19 clrbits_le32(&ccm->cscmr1, CCM_CSCMR1_DCU0_CLK_SEL);
20 clrsetbits_le32(&ccm->cscdr3,
21 CCM_CSCDR3_DCU0_DIV_MASK | CCM_CSCDR3_DCU0_EN,
22 CCM_CSCDR3_DCU0_DIV(0) | CCM_CSCDR3_DCU0_EN);
23 div = (unsigned long long)(PLL1_PFD2_FREQ / 1000);
24 do_div(div, pixclock);
25
26 return div;
27}
28
29int platform_dcu_init(unsigned int xres, unsigned int yres,
30 const char *port,
31 struct fb_videomode *dcu_fb_videomode)
32{
33 fsl_dcu_init(xres, yres, 32);
34
35 return 0;
36}