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Sedji Gaouaou538566d2009-07-09 10:16:29 +02001/*
2 * (C) Copyright 2007-2008
Stelian Pop5ee0c7f2011-11-01 00:00:39 +01003 * Stelian Pop <stelian@popies.net>
Sedji Gaouaou538566d2009-07-09 10:16:29 +02004 * Lead Tech Design <www.leadtechdesign.com>
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Sedji Gaouaou538566d2009-07-09 10:16:29 +02007 */
8
9#include <common.h>
10#include <asm/arch/at91_common.h>
Wenyou Yang57b7f292016-02-03 10:16:49 +080011#include <asm/arch/clk.h>
Sedji Gaouaou538566d2009-07-09 10:16:29 +020012#include <asm/arch/gpio.h>
Thomas Petazzonib0263c52011-08-04 08:53:29 +000013#include <asm/io.h>
14
15/*
16 * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
17 * peripheral pins. Good to have if hardware is soldered optionally
18 * or in case of SPI no slave is selected. Avoid lines to float
19 * needlessly. Use a short local PUP define.
20 *
21 * Due to errata "TXD floats when CTS is inactive" pullups are always
22 * on for TXD pins.
23 */
24#ifdef CONFIG_AT91_GPIO_PULLUP
25# define PUP CONFIG_AT91_GPIO_PULLUP
26#else
27# define PUP 0
28#endif
Sedji Gaouaou538566d2009-07-09 10:16:29 +020029
30void at91_serial0_hw_init(void)
31{
Jens Scharsigb49d15c2010-02-03 22:46:46 +010032 at91_set_a_periph(AT91_PIO_PORTB, 19, 1); /* TXD0 */
Thomas Petazzonib0263c52011-08-04 08:53:29 +000033 at91_set_a_periph(AT91_PIO_PORTB, 18, PUP); /* RXD0 */
Wenyou Yang57b7f292016-02-03 10:16:49 +080034 at91_periph_clk_enable(ATMEL_ID_USART0);
Sedji Gaouaou538566d2009-07-09 10:16:29 +020035}
36
37void at91_serial1_hw_init(void)
38{
Jens Scharsigb49d15c2010-02-03 22:46:46 +010039 at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD1 */
Thomas Petazzonib0263c52011-08-04 08:53:29 +000040 at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD1 */
Wenyou Yang57b7f292016-02-03 10:16:49 +080041 at91_periph_clk_enable(ATMEL_ID_USART1);
Sedji Gaouaou538566d2009-07-09 10:16:29 +020042}
43
44void at91_serial2_hw_init(void)
45{
Jens Scharsigb49d15c2010-02-03 22:46:46 +010046 at91_set_a_periph(AT91_PIO_PORTD, 6, 1); /* TXD2 */
Thomas Petazzonib0263c52011-08-04 08:53:29 +000047 at91_set_a_periph(AT91_PIO_PORTD, 7, PUP); /* RXD2 */
Wenyou Yang57b7f292016-02-03 10:16:49 +080048 at91_periph_clk_enable(ATMEL_ID_USART2);
Sedji Gaouaou538566d2009-07-09 10:16:29 +020049}
50
Thomas Petazzonib0263c52011-08-04 08:53:29 +000051void at91_seriald_hw_init(void)
Sedji Gaouaou538566d2009-07-09 10:16:29 +020052{
Jens Scharsigb49d15c2010-02-03 22:46:46 +010053 at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* DRXD */
54 at91_set_a_periph(AT91_PIO_PORTB, 13, 1); /* DTXD */
Wenyou Yang57b7f292016-02-03 10:16:49 +080055 at91_periph_clk_enable(ATMEL_ID_SYS);
Sedji Gaouaou538566d2009-07-09 10:16:29 +020056}
57
Thomas Petazzonib0263c52011-08-04 08:53:29 +000058#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
Sedji Gaouaou538566d2009-07-09 10:16:29 +020059void at91_spi0_hw_init(unsigned long cs_mask)
60{
Thomas Petazzonib0263c52011-08-04 08:53:29 +000061 at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI0_MISO */
62 at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI0_MOSI */
63 at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI0_SPCK */
Sedji Gaouaou538566d2009-07-09 10:16:29 +020064
Wenyou Yang57b7f292016-02-03 10:16:49 +080065 at91_periph_clk_enable(ATMEL_ID_SPI0);
Sedji Gaouaou538566d2009-07-09 10:16:29 +020066
67 if (cs_mask & (1 << 0)) {
Thomas Petazzonib0263c52011-08-04 08:53:29 +000068 at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
Sedji Gaouaou538566d2009-07-09 10:16:29 +020069 }
70 if (cs_mask & (1 << 1)) {
Thomas Petazzonib0263c52011-08-04 08:53:29 +000071 at91_set_b_periph(AT91_PIO_PORTB, 18, 1);
Sedji Gaouaou538566d2009-07-09 10:16:29 +020072 }
73 if (cs_mask & (1 << 2)) {
Thomas Petazzonib0263c52011-08-04 08:53:29 +000074 at91_set_b_periph(AT91_PIO_PORTB, 19, 1);
Sedji Gaouaou538566d2009-07-09 10:16:29 +020075 }
76 if (cs_mask & (1 << 3)) {
Thomas Petazzonib0263c52011-08-04 08:53:29 +000077 at91_set_b_periph(AT91_PIO_PORTD, 27, 1);
Sedji Gaouaou538566d2009-07-09 10:16:29 +020078 }
79 if (cs_mask & (1 << 4)) {
Thomas Petazzonib0263c52011-08-04 08:53:29 +000080 at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
Sedji Gaouaou538566d2009-07-09 10:16:29 +020081 }
82 if (cs_mask & (1 << 5)) {
Thomas Petazzonib0263c52011-08-04 08:53:29 +000083 at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
Sedji Gaouaou538566d2009-07-09 10:16:29 +020084 }
85 if (cs_mask & (1 << 6)) {
Thomas Petazzonib0263c52011-08-04 08:53:29 +000086 at91_set_pio_output(AT91_PIO_PORTB, 19, 1);
Sedji Gaouaou538566d2009-07-09 10:16:29 +020087 }
88 if (cs_mask & (1 << 7)) {
Thomas Petazzonib0263c52011-08-04 08:53:29 +000089 at91_set_pio_output(AT91_PIO_PORTD, 27, 1);
Sedji Gaouaou538566d2009-07-09 10:16:29 +020090 }
91}
92
93void at91_spi1_hw_init(unsigned long cs_mask)
94{
Thomas Petazzonib0263c52011-08-04 08:53:29 +000095 at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* SPI1_MISO */
96 at91_set_a_periph(AT91_PIO_PORTB, 15, PUP); /* SPI1_MOSI */
97 at91_set_a_periph(AT91_PIO_PORTB, 16, PUP); /* SPI1_SPCK */
Sedji Gaouaou538566d2009-07-09 10:16:29 +020098
Wenyou Yang57b7f292016-02-03 10:16:49 +080099 at91_periph_clk_enable(ATMEL_ID_SPI1);
Sedji Gaouaou538566d2009-07-09 10:16:29 +0200100
101 if (cs_mask & (1 << 0)) {
Thomas Petazzonib0263c52011-08-04 08:53:29 +0000102 at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
Sedji Gaouaou538566d2009-07-09 10:16:29 +0200103 }
104 if (cs_mask & (1 << 1)) {
Thomas Petazzonib0263c52011-08-04 08:53:29 +0000105 at91_set_b_periph(AT91_PIO_PORTD, 28, 1);
Sedji Gaouaou538566d2009-07-09 10:16:29 +0200106 }
107 if (cs_mask & (1 << 2)) {
Thomas Petazzonib0263c52011-08-04 08:53:29 +0000108 at91_set_a_periph(AT91_PIO_PORTD, 18, 1);
Sedji Gaouaou538566d2009-07-09 10:16:29 +0200109 }
110 if (cs_mask & (1 << 3)) {
Thomas Petazzonib0263c52011-08-04 08:53:29 +0000111 at91_set_a_periph(AT91_PIO_PORTD, 19, 1);
Sedji Gaouaou538566d2009-07-09 10:16:29 +0200112 }
113 if (cs_mask & (1 << 4)) {
Thomas Petazzonib0263c52011-08-04 08:53:29 +0000114 at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
Sedji Gaouaou538566d2009-07-09 10:16:29 +0200115 }
116 if (cs_mask & (1 << 5)) {
Thomas Petazzonib0263c52011-08-04 08:53:29 +0000117 at91_set_pio_output(AT91_PIO_PORTD, 28, 1);
Sedji Gaouaou538566d2009-07-09 10:16:29 +0200118 }
119 if (cs_mask & (1 << 6)) {
Thomas Petazzonib0263c52011-08-04 08:53:29 +0000120 at91_set_pio_output(AT91_PIO_PORTD, 18, 1);
Sedji Gaouaou538566d2009-07-09 10:16:29 +0200121 }
122 if (cs_mask & (1 << 7)) {
Thomas Petazzonib0263c52011-08-04 08:53:29 +0000123 at91_set_pio_output(AT91_PIO_PORTD, 19, 1);
Sedji Gaouaou538566d2009-07-09 10:16:29 +0200124 }
125
126}
127#endif
128
129#ifdef CONFIG_MACB
130void at91_macb_hw_init(void)
131{
Jens Scharsigb49d15c2010-02-03 22:46:46 +0100132 at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ETXCK_EREFCK */
133 at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* ERXDV */
134 at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* ERX0 */
135 at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* ERX1 */
136 at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* ERXER */
137 at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* ETXEN */
138 at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* ETX0 */
139 at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* ETX1 */
140 at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* EMDIO */
141 at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* EMDC */
Sedji Gaouaou538566d2009-07-09 10:16:29 +0200142#ifndef CONFIG_RMII
Jens Scharsigb49d15c2010-02-03 22:46:46 +0100143 at91_set_b_periph(AT91_PIO_PORTA, 29, 0); /* ECRS */
144 at91_set_b_periph(AT91_PIO_PORTA, 30, 0); /* ECOL */
145 at91_set_b_periph(AT91_PIO_PORTA, 8, 0); /* ERX2 */
146 at91_set_b_periph(AT91_PIO_PORTA, 9, 0); /* ERX3 */
147 at91_set_b_periph(AT91_PIO_PORTA, 28, 0); /* ERXCK */
148 at91_set_b_periph(AT91_PIO_PORTA, 6, 0); /* ETX2 */
149 at91_set_b_periph(AT91_PIO_PORTA, 7, 0); /* ETX3 */
150 at91_set_b_periph(AT91_PIO_PORTA, 27, 0); /* ETXER */
Sedji Gaouaou538566d2009-07-09 10:16:29 +0200151#endif
152}
153#endif
Wu, Joshdff665a2014-05-21 10:42:15 +0800154
155#ifdef CONFIG_GENERIC_ATMEL_MCI
156void at91_mci_hw_init(void)
157{
Wu, Joshdff665a2014-05-21 10:42:15 +0800158 at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* MCI0 CLK */
159 at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* MCI0 CDA */
160 at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* MCI0 DA0 */
161 at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* MCI0 DA1 */
162 at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* MCI0 DA2 */
163 at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* MCI0 DA3 */
164
Wenyou Yang57b7f292016-02-03 10:16:49 +0800165 at91_periph_clk_enable(ATMEL_ID_MCI0);
Wu, Joshdff665a2014-05-21 10:42:15 +0800166}
167#endif