| Lokesh Vutla | 86106ed | 2021-05-06 16:45:00 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ |
| 4 | * This file was generated with the |
| Sinthu Raja | 7b9717c | 2021-11-29 17:34:49 +0530 | [diff] [blame] | 5 | * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.00 |
| 6 | * Wed Oct 13 2021 10:08:29 GMT-0500 (Central Daylight Time) |
| Lokesh Vutla | 86106ed | 2021-05-06 16:45:00 +0530 | [diff] [blame] | 7 | * DDR Type: LPDDR4 |
| 8 | * F0 = 50MHz F1 = 666.7MHz F2 = 666.7MHz |
| 9 | * Density (per channel): 16Gb |
| 10 | * Number of Ranks: 1 |
| 11 | */ |
| 12 | |
| 13 | #define DDRSS_PLL_FHS_CNT 6 |
| 14 | #define DDRSS_PLL_FREQUENCY_1 333350000 |
| 15 | #define DDRSS_PLL_FREQUENCY_2 333350000 |
| 16 | |
| 17 | #define DDRSS_CTL_0_DATA 0x00000B00 |
| 18 | #define DDRSS_CTL_1_DATA 0x00000000 |
| 19 | #define DDRSS_CTL_2_DATA 0x00000000 |
| 20 | #define DDRSS_CTL_3_DATA 0x00000000 |
| 21 | #define DDRSS_CTL_4_DATA 0x00000000 |
| 22 | #define DDRSS_CTL_5_DATA 0x00000000 |
| 23 | #define DDRSS_CTL_6_DATA 0x00000000 |
| 24 | #define DDRSS_CTL_7_DATA 0x00002710 |
| 25 | #define DDRSS_CTL_8_DATA 0x000186A0 |
| 26 | #define DDRSS_CTL_9_DATA 0x00000005 |
| 27 | #define DDRSS_CTL_10_DATA 0x00000064 |
| 28 | #define DDRSS_CTL_11_DATA 0x000208D6 |
| 29 | #define DDRSS_CTL_12_DATA 0x00145856 |
| 30 | #define DDRSS_CTL_13_DATA 0x00000005 |
| 31 | #define DDRSS_CTL_14_DATA 0x00000536 |
| 32 | #define DDRSS_CTL_15_DATA 0x000208D6 |
| 33 | #define DDRSS_CTL_16_DATA 0x00145856 |
| 34 | #define DDRSS_CTL_17_DATA 0x00000005 |
| 35 | #define DDRSS_CTL_18_DATA 0x00000536 |
| 36 | #define DDRSS_CTL_19_DATA 0x01010100 |
| 37 | #define DDRSS_CTL_20_DATA 0x01010100 |
| 38 | #define DDRSS_CTL_21_DATA 0x01000110 |
| 39 | #define DDRSS_CTL_22_DATA 0x02010002 |
| 40 | #define DDRSS_CTL_23_DATA 0x0000000A |
| 41 | #define DDRSS_CTL_24_DATA 0x000186A0 |
| 42 | #define DDRSS_CTL_25_DATA 0x00000000 |
| 43 | #define DDRSS_CTL_26_DATA 0x00000000 |
| 44 | #define DDRSS_CTL_27_DATA 0x00000000 |
| 45 | #define DDRSS_CTL_28_DATA 0x00000000 |
| 46 | #define DDRSS_CTL_29_DATA 0x00020200 |
| 47 | #define DDRSS_CTL_30_DATA 0x00000000 |
| 48 | #define DDRSS_CTL_31_DATA 0x00000000 |
| 49 | #define DDRSS_CTL_32_DATA 0x00000000 |
| 50 | #define DDRSS_CTL_33_DATA 0x00000000 |
| 51 | #define DDRSS_CTL_34_DATA 0x02000010 |
| 52 | #define DDRSS_CTL_35_DATA 0x00001B1B |
| 53 | #define DDRSS_CTL_36_DATA 0x00000000 |
| 54 | #define DDRSS_CTL_37_DATA 0x00000000 |
| 55 | #define DDRSS_CTL_38_DATA 0x0000040C |
| 56 | #define DDRSS_CTL_39_DATA 0x00000000 |
| 57 | #define DDRSS_CTL_40_DATA 0x0000081C |
| 58 | #define DDRSS_CTL_41_DATA 0x00000000 |
| 59 | #define DDRSS_CTL_42_DATA 0x0000081C |
| 60 | #define DDRSS_CTL_43_DATA 0x00000000 |
| 61 | #define DDRSS_CTL_44_DATA 0x05000804 |
| 62 | #define DDRSS_CTL_45_DATA 0x00000700 |
| 63 | #define DDRSS_CTL_46_DATA 0x09090004 |
| 64 | #define DDRSS_CTL_47_DATA 0x00000203 |
| 65 | #define DDRSS_CTL_48_DATA 0x00290006 |
| 66 | #define DDRSS_CTL_49_DATA 0x0909001D |
| 67 | #define DDRSS_CTL_50_DATA 0x0000150C |
| 68 | #define DDRSS_CTL_51_DATA 0x00290006 |
| 69 | #define DDRSS_CTL_52_DATA 0x0909001D |
| 70 | #define DDRSS_CTL_53_DATA 0x0900150C |
| 71 | #define DDRSS_CTL_54_DATA 0x000A0A09 |
| 72 | #define DDRSS_CTL_55_DATA 0x040006DB |
| 73 | #define DDRSS_CTL_56_DATA 0x09092004 |
| 74 | #define DDRSS_CTL_57_DATA 0x00000A0A |
| 75 | #define DDRSS_CTL_58_DATA 0x05005B68 |
| 76 | #define DDRSS_CTL_59_DATA 0x09092005 |
| 77 | #define DDRSS_CTL_60_DATA 0x00000A0A |
| 78 | #define DDRSS_CTL_61_DATA 0x05005B68 |
| 79 | #define DDRSS_CTL_62_DATA 0x03042005 |
| 80 | #define DDRSS_CTL_63_DATA 0x04050002 |
| 81 | #define DDRSS_CTL_64_DATA 0x0E0D0E0D |
| 82 | #define DDRSS_CTL_65_DATA 0x01010008 |
| 83 | #define DDRSS_CTL_66_DATA 0x041A1A07 |
| 84 | #define DDRSS_CTL_67_DATA 0x030E0E03 |
| 85 | #define DDRSS_CTL_68_DATA 0x00000E0E |
| 86 | #define DDRSS_CTL_69_DATA 0x00000101 |
| 87 | #define DDRSS_CTL_70_DATA 0x00000000 |
| 88 | #define DDRSS_CTL_71_DATA 0x01000000 |
| 89 | #define DDRSS_CTL_72_DATA 0x00130803 |
| 90 | #define DDRSS_CTL_73_DATA 0x000000BB |
| 91 | #define DDRSS_CTL_74_DATA 0x000000FE |
| 92 | #define DDRSS_CTL_75_DATA 0x00000A20 |
| 93 | #define DDRSS_CTL_76_DATA 0x000000FE |
| 94 | #define DDRSS_CTL_77_DATA 0x00000A20 |
| 95 | #define DDRSS_CTL_78_DATA 0x00000005 |
| 96 | #define DDRSS_CTL_79_DATA 0x0000000A |
| 97 | #define DDRSS_CTL_80_DATA 0x00000010 |
| 98 | #define DDRSS_CTL_81_DATA 0x0000007F |
| 99 | #define DDRSS_CTL_82_DATA 0x0000013D |
| 100 | #define DDRSS_CTL_83_DATA 0x0000007F |
| 101 | #define DDRSS_CTL_84_DATA 0x0000013D |
| 102 | #define DDRSS_CTL_85_DATA 0x03004000 |
| 103 | #define DDRSS_CTL_86_DATA 0x00001201 |
| 104 | #define DDRSS_CTL_87_DATA 0x00050005 |
| 105 | #define DDRSS_CTL_88_DATA 0x00000005 |
| 106 | #define DDRSS_CTL_89_DATA 0x00000000 |
| 107 | #define DDRSS_CTL_90_DATA 0x05101008 |
| 108 | #define DDRSS_CTL_91_DATA 0x05030A05 |
| 109 | #define DDRSS_CTL_92_DATA 0x05030A05 |
| 110 | #define DDRSS_CTL_93_DATA 0x01030A05 |
| 111 | #define DDRSS_CTL_94_DATA 0x02010201 |
| 112 | #define DDRSS_CTL_95_DATA 0x00001401 |
| 113 | #define DDRSS_CTL_96_DATA 0x01030014 |
| 114 | #define DDRSS_CTL_97_DATA 0x01030103 |
| 115 | #define DDRSS_CTL_98_DATA 0x00000103 |
| 116 | #define DDRSS_CTL_99_DATA 0x00000000 |
| 117 | #define DDRSS_CTL_100_DATA 0x05010303 |
| 118 | #define DDRSS_CTL_101_DATA 0x0A040505 |
| 119 | #define DDRSS_CTL_102_DATA 0x05050203 |
| 120 | #define DDRSS_CTL_103_DATA 0x030A0505 |
| 121 | #define DDRSS_CTL_104_DATA 0x05050502 |
| 122 | #define DDRSS_CTL_105_DATA 0x03030305 |
| 123 | #define DDRSS_CTL_106_DATA 0x03010000 |
| 124 | #define DDRSS_CTL_107_DATA 0x00010000 |
| 125 | #define DDRSS_CTL_108_DATA 0x00000000 |
| 126 | #define DDRSS_CTL_109_DATA 0x01000000 |
| 127 | #define DDRSS_CTL_110_DATA 0x80104002 |
| 128 | #define DDRSS_CTL_111_DATA 0x00040003 |
| 129 | #define DDRSS_CTL_112_DATA 0x00040005 |
| 130 | #define DDRSS_CTL_113_DATA 0x00030000 |
| 131 | #define DDRSS_CTL_114_DATA 0x00050004 |
| 132 | #define DDRSS_CTL_115_DATA 0x00000004 |
| 133 | #define DDRSS_CTL_116_DATA 0x00040003 |
| 134 | #define DDRSS_CTL_117_DATA 0x00040005 |
| 135 | #define DDRSS_CTL_118_DATA 0x00000000 |
| 136 | #define DDRSS_CTL_119_DATA 0x00002EC0 |
| 137 | #define DDRSS_CTL_120_DATA 0x00002EC0 |
| 138 | #define DDRSS_CTL_121_DATA 0x00002EC0 |
| 139 | #define DDRSS_CTL_122_DATA 0x00002EC0 |
| 140 | #define DDRSS_CTL_123_DATA 0x00002EC0 |
| 141 | #define DDRSS_CTL_124_DATA 0x00000000 |
| 142 | #define DDRSS_CTL_125_DATA 0x0000051D |
| 143 | #define DDRSS_CTL_126_DATA 0x00028800 |
| 144 | #define DDRSS_CTL_127_DATA 0x00028800 |
| 145 | #define DDRSS_CTL_128_DATA 0x00028800 |
| 146 | #define DDRSS_CTL_129_DATA 0x00028800 |
| 147 | #define DDRSS_CTL_130_DATA 0x00028800 |
| 148 | #define DDRSS_CTL_131_DATA 0x00000000 |
| 149 | #define DDRSS_CTL_132_DATA 0x000046E0 |
| 150 | #define DDRSS_CTL_133_DATA 0x00028800 |
| 151 | #define DDRSS_CTL_134_DATA 0x00028800 |
| 152 | #define DDRSS_CTL_135_DATA 0x00028800 |
| 153 | #define DDRSS_CTL_136_DATA 0x00028800 |
| 154 | #define DDRSS_CTL_137_DATA 0x00028800 |
| 155 | #define DDRSS_CTL_138_DATA 0x00000000 |
| 156 | #define DDRSS_CTL_139_DATA 0x000046E0 |
| 157 | #define DDRSS_CTL_140_DATA 0x00000000 |
| 158 | #define DDRSS_CTL_141_DATA 0x00000000 |
| 159 | #define DDRSS_CTL_142_DATA 0x00000000 |
| 160 | #define DDRSS_CTL_143_DATA 0x00000000 |
| 161 | #define DDRSS_CTL_144_DATA 0x00000000 |
| 162 | #define DDRSS_CTL_145_DATA 0x00000000 |
| 163 | #define DDRSS_CTL_146_DATA 0x00000000 |
| 164 | #define DDRSS_CTL_147_DATA 0x00000000 |
| 165 | #define DDRSS_CTL_148_DATA 0x00000000 |
| 166 | #define DDRSS_CTL_149_DATA 0x00000000 |
| 167 | #define DDRSS_CTL_150_DATA 0x00000000 |
| 168 | #define DDRSS_CTL_151_DATA 0x00000000 |
| 169 | #define DDRSS_CTL_152_DATA 0x00000000 |
| 170 | #define DDRSS_CTL_153_DATA 0x00000000 |
| 171 | #define DDRSS_CTL_154_DATA 0x00000000 |
| 172 | #define DDRSS_CTL_155_DATA 0x00000000 |
| 173 | #define DDRSS_CTL_156_DATA 0x03050000 |
| 174 | #define DDRSS_CTL_157_DATA 0x03050305 |
| 175 | #define DDRSS_CTL_158_DATA 0x00000000 |
| 176 | #define DDRSS_CTL_159_DATA 0x07010A09 |
| 177 | #define DDRSS_CTL_160_DATA 0x000E0A09 |
| 178 | #define DDRSS_CTL_161_DATA 0x010A0900 |
| 179 | #define DDRSS_CTL_162_DATA 0x0E0A0907 |
| 180 | #define DDRSS_CTL_163_DATA 0x0A090000 |
| 181 | #define DDRSS_CTL_164_DATA 0x0A090701 |
| 182 | #define DDRSS_CTL_165_DATA 0x0000000E |
| 183 | #define DDRSS_CTL_166_DATA 0x00040003 |
| 184 | #define DDRSS_CTL_167_DATA 0x00000007 |
| 185 | #define DDRSS_CTL_168_DATA 0x00000000 |
| 186 | #define DDRSS_CTL_169_DATA 0x00000000 |
| 187 | #define DDRSS_CTL_170_DATA 0x00000000 |
| 188 | #define DDRSS_CTL_171_DATA 0x00000000 |
| 189 | #define DDRSS_CTL_172_DATA 0x00000000 |
| 190 | #define DDRSS_CTL_173_DATA 0x00000000 |
| 191 | #define DDRSS_CTL_174_DATA 0x01000000 |
| 192 | #define DDRSS_CTL_175_DATA 0x00000000 |
| 193 | #define DDRSS_CTL_176_DATA 0x00001500 |
| 194 | #define DDRSS_CTL_177_DATA 0x0000100E |
| 195 | #define DDRSS_CTL_178_DATA 0x00000002 |
| 196 | #define DDRSS_CTL_179_DATA 0x00000000 |
| 197 | #define DDRSS_CTL_180_DATA 0x00000001 |
| 198 | #define DDRSS_CTL_181_DATA 0x00000002 |
| 199 | #define DDRSS_CTL_182_DATA 0x00000C00 |
| 200 | #define DDRSS_CTL_183_DATA 0x00001000 |
| 201 | #define DDRSS_CTL_184_DATA 0x00000C00 |
| 202 | #define DDRSS_CTL_185_DATA 0x00001000 |
| 203 | #define DDRSS_CTL_186_DATA 0x00000C00 |
| 204 | #define DDRSS_CTL_187_DATA 0x00001000 |
| 205 | #define DDRSS_CTL_188_DATA 0x00000000 |
| 206 | #define DDRSS_CTL_189_DATA 0x00000000 |
| 207 | #define DDRSS_CTL_190_DATA 0x00000000 |
| 208 | #define DDRSS_CTL_191_DATA 0x00000000 |
| 209 | #define DDRSS_CTL_192_DATA 0x0005000A |
| 210 | #define DDRSS_CTL_193_DATA 0x0404000D |
| 211 | #define DDRSS_CTL_194_DATA 0x0000000D |
| 212 | #define DDRSS_CTL_195_DATA 0x00430086 |
| 213 | #define DDRSS_CTL_196_DATA 0x050500A7 |
| 214 | #define DDRSS_CTL_197_DATA 0x000000A7 |
| 215 | #define DDRSS_CTL_198_DATA 0x00430086 |
| 216 | #define DDRSS_CTL_199_DATA 0x050500A7 |
| 217 | #define DDRSS_CTL_200_DATA 0x000000A7 |
| 218 | #define DDRSS_CTL_201_DATA 0x00000000 |
| 219 | #define DDRSS_CTL_202_DATA 0x00000000 |
| 220 | #define DDRSS_CTL_203_DATA 0x00000000 |
| 221 | #define DDRSS_CTL_204_DATA 0x00000000 |
| 222 | #define DDRSS_CTL_205_DATA 0x00000004 |
| 223 | #define DDRSS_CTL_206_DATA 0x00000000 |
| 224 | #define DDRSS_CTL_207_DATA 0x00000000 |
| 225 | #define DDRSS_CTL_208_DATA 0x00000024 |
| 226 | #define DDRSS_CTL_209_DATA 0x00000012 |
| 227 | #define DDRSS_CTL_210_DATA 0x00000000 |
| 228 | #define DDRSS_CTL_211_DATA 0x00000024 |
| 229 | #define DDRSS_CTL_212_DATA 0x00000012 |
| 230 | #define DDRSS_CTL_213_DATA 0x00000000 |
| 231 | #define DDRSS_CTL_214_DATA 0x00000004 |
| 232 | #define DDRSS_CTL_215_DATA 0x00000000 |
| 233 | #define DDRSS_CTL_216_DATA 0x00000000 |
| 234 | #define DDRSS_CTL_217_DATA 0x00000024 |
| 235 | #define DDRSS_CTL_218_DATA 0x00000012 |
| 236 | #define DDRSS_CTL_219_DATA 0x00000000 |
| 237 | #define DDRSS_CTL_220_DATA 0x00000024 |
| 238 | #define DDRSS_CTL_221_DATA 0x00000012 |
| 239 | #define DDRSS_CTL_222_DATA 0x00000000 |
| 240 | #define DDRSS_CTL_223_DATA 0x00000000 |
| 241 | #define DDRSS_CTL_224_DATA 0x00000031 |
| 242 | #define DDRSS_CTL_225_DATA 0x00000031 |
| 243 | #define DDRSS_CTL_226_DATA 0x00000031 |
| 244 | #define DDRSS_CTL_227_DATA 0x00000031 |
| 245 | #define DDRSS_CTL_228_DATA 0x00000031 |
| 246 | #define DDRSS_CTL_229_DATA 0x00000031 |
| 247 | #define DDRSS_CTL_230_DATA 0x00000000 |
| 248 | #define DDRSS_CTL_231_DATA 0x00000000 |
| 249 | #define DDRSS_CTL_232_DATA 0x00000000 |
| 250 | #define DDRSS_CTL_233_DATA 0x00000000 |
| 251 | #define DDRSS_CTL_234_DATA 0x00000000 |
| 252 | #define DDRSS_CTL_235_DATA 0x00000000 |
| 253 | #define DDRSS_CTL_236_DATA 0x00000000 |
| 254 | #define DDRSS_CTL_237_DATA 0x00000000 |
| 255 | #define DDRSS_CTL_238_DATA 0x00000000 |
| 256 | #define DDRSS_CTL_239_DATA 0x00000000 |
| 257 | #define DDRSS_CTL_240_DATA 0x00000000 |
| 258 | #define DDRSS_CTL_241_DATA 0x00000000 |
| 259 | #define DDRSS_CTL_242_DATA 0x00000000 |
| 260 | #define DDRSS_CTL_243_DATA 0x00000000 |
| 261 | #define DDRSS_CTL_244_DATA 0x00000000 |
| 262 | #define DDRSS_CTL_245_DATA 0x00000000 |
| 263 | #define DDRSS_CTL_246_DATA 0x00000000 |
| 264 | #define DDRSS_CTL_247_DATA 0x00000000 |
| 265 | #define DDRSS_CTL_248_DATA 0x00000000 |
| 266 | #define DDRSS_CTL_249_DATA 0x00000000 |
| 267 | #define DDRSS_CTL_250_DATA 0x00000000 |
| 268 | #define DDRSS_CTL_251_DATA 0x00000000 |
| 269 | #define DDRSS_CTL_252_DATA 0x00000000 |
| 270 | #define DDRSS_CTL_253_DATA 0x00000000 |
| Sinthu Raja | 7b9717c | 2021-11-29 17:34:49 +0530 | [diff] [blame] | 271 | #define DDRSS_CTL_254_DATA 0x46004646 |
| 272 | #define DDRSS_CTL_255_DATA 0x00002746 |
| Lokesh Vutla | 86106ed | 2021-05-06 16:45:00 +0530 | [diff] [blame] | 273 | #define DDRSS_CTL_256_DATA 0x00000027 |
| 274 | #define DDRSS_CTL_257_DATA 0x00000027 |
| 275 | #define DDRSS_CTL_258_DATA 0x00000027 |
| 276 | #define DDRSS_CTL_259_DATA 0x00000027 |
| 277 | #define DDRSS_CTL_260_DATA 0x00000027 |
| 278 | #define DDRSS_CTL_261_DATA 0x00000000 |
| 279 | #define DDRSS_CTL_262_DATA 0x00000000 |
| 280 | #define DDRSS_CTL_263_DATA 0x0000000F |
| 281 | #define DDRSS_CTL_264_DATA 0x0000000F |
| 282 | #define DDRSS_CTL_265_DATA 0x0000000F |
| 283 | #define DDRSS_CTL_266_DATA 0x0000000F |
| 284 | #define DDRSS_CTL_267_DATA 0x0000000F |
| 285 | #define DDRSS_CTL_268_DATA 0x0000000F |
| 286 | #define DDRSS_CTL_269_DATA 0x00000000 |
| 287 | #define DDRSS_CTL_270_DATA 0x00000000 |
| 288 | #define DDRSS_CTL_271_DATA 0x00000015 |
| 289 | #define DDRSS_CTL_272_DATA 0x00000015 |
| 290 | #define DDRSS_CTL_273_DATA 0x00000000 |
| 291 | #define DDRSS_CTL_274_DATA 0x00000015 |
| 292 | #define DDRSS_CTL_275_DATA 0x00000015 |
| 293 | #define DDRSS_CTL_276_DATA 0x00000020 |
| 294 | #define DDRSS_CTL_277_DATA 0x00010000 |
| 295 | #define DDRSS_CTL_278_DATA 0x00000100 |
| 296 | #define DDRSS_CTL_279_DATA 0x00000000 |
| 297 | #define DDRSS_CTL_280_DATA 0x00000000 |
| 298 | #define DDRSS_CTL_281_DATA 0x00000101 |
| 299 | #define DDRSS_CTL_282_DATA 0x00000000 |
| 300 | #define DDRSS_CTL_283_DATA 0x00000000 |
| 301 | #define DDRSS_CTL_284_DATA 0x00000000 |
| 302 | #define DDRSS_CTL_285_DATA 0x00000000 |
| 303 | #define DDRSS_CTL_286_DATA 0x00000000 |
| 304 | #define DDRSS_CTL_287_DATA 0x00000000 |
| 305 | #define DDRSS_CTL_288_DATA 0x00000000 |
| 306 | #define DDRSS_CTL_289_DATA 0x00000000 |
| 307 | #define DDRSS_CTL_290_DATA 0x0C181511 |
| 308 | #define DDRSS_CTL_291_DATA 0x00000304 |
| 309 | #define DDRSS_CTL_292_DATA 0x00000000 |
| 310 | #define DDRSS_CTL_293_DATA 0x00000000 |
| 311 | #define DDRSS_CTL_294_DATA 0x00000000 |
| 312 | #define DDRSS_CTL_295_DATA 0x00000000 |
| 313 | #define DDRSS_CTL_296_DATA 0x00000000 |
| 314 | #define DDRSS_CTL_297_DATA 0x00000000 |
| 315 | #define DDRSS_CTL_298_DATA 0x00000000 |
| 316 | #define DDRSS_CTL_299_DATA 0x00000000 |
| 317 | #define DDRSS_CTL_300_DATA 0x00000000 |
| 318 | #define DDRSS_CTL_301_DATA 0x00000000 |
| 319 | #define DDRSS_CTL_302_DATA 0x00000000 |
| 320 | #define DDRSS_CTL_303_DATA 0x00000000 |
| 321 | #define DDRSS_CTL_304_DATA 0x00000000 |
| 322 | #define DDRSS_CTL_305_DATA 0x00020000 |
| 323 | #define DDRSS_CTL_306_DATA 0x00400100 |
| 324 | #define DDRSS_CTL_307_DATA 0x00080032 |
| 325 | #define DDRSS_CTL_308_DATA 0x01000200 |
| 326 | #define DDRSS_CTL_309_DATA 0x029B0040 |
| 327 | #define DDRSS_CTL_310_DATA 0x00020014 |
| 328 | #define DDRSS_CTL_311_DATA 0x00400100 |
| 329 | #define DDRSS_CTL_312_DATA 0x0014029B |
| 330 | #define DDRSS_CTL_313_DATA 0x00030000 |
| 331 | #define DDRSS_CTL_314_DATA 0x00220022 |
| 332 | #define DDRSS_CTL_315_DATA 0x00000100 |
| 333 | #define DDRSS_CTL_316_DATA 0x01010000 |
| 334 | #define DDRSS_CTL_317_DATA 0x00000000 |
| 335 | #define DDRSS_CTL_318_DATA 0x3FFF0000 |
| 336 | #define DDRSS_CTL_319_DATA 0x000FFF00 |
| 337 | #define DDRSS_CTL_320_DATA 0xFFFFFFFF |
| 338 | #define DDRSS_CTL_321_DATA 0x000FFF00 |
| 339 | #define DDRSS_CTL_322_DATA 0x0B000000 |
| 340 | #define DDRSS_CTL_323_DATA 0x0001FFFF |
| 341 | #define DDRSS_CTL_324_DATA 0x01010101 |
| 342 | #define DDRSS_CTL_325_DATA 0x01010101 |
| 343 | #define DDRSS_CTL_326_DATA 0x00000118 |
| 344 | #define DDRSS_CTL_327_DATA 0x00000C01 |
| 345 | #define DDRSS_CTL_328_DATA 0x01000100 |
| 346 | #define DDRSS_CTL_329_DATA 0x00000000 |
| 347 | #define DDRSS_CTL_330_DATA 0x01000000 |
| 348 | #define DDRSS_CTL_331_DATA 0x01030303 |
| 349 | #define DDRSS_CTL_332_DATA 0x00000000 |
| 350 | #define DDRSS_CTL_333_DATA 0x00000000 |
| 351 | #define DDRSS_CTL_334_DATA 0x00000000 |
| 352 | #define DDRSS_CTL_335_DATA 0x00000000 |
| 353 | #define DDRSS_CTL_336_DATA 0x00000000 |
| 354 | #define DDRSS_CTL_337_DATA 0x00000000 |
| 355 | #define DDRSS_CTL_338_DATA 0x00000000 |
| 356 | #define DDRSS_CTL_339_DATA 0x00000000 |
| 357 | #define DDRSS_CTL_340_DATA 0x00000000 |
| 358 | #define DDRSS_CTL_341_DATA 0x00000000 |
| 359 | #define DDRSS_CTL_342_DATA 0x00000000 |
| 360 | #define DDRSS_CTL_343_DATA 0x00000000 |
| 361 | #define DDRSS_CTL_344_DATA 0x00000000 |
| 362 | #define DDRSS_CTL_345_DATA 0x00000000 |
| 363 | #define DDRSS_CTL_346_DATA 0x00000000 |
| 364 | #define DDRSS_CTL_347_DATA 0x00000000 |
| 365 | #define DDRSS_CTL_348_DATA 0x00000000 |
| 366 | #define DDRSS_CTL_349_DATA 0x00000000 |
| 367 | #define DDRSS_CTL_350_DATA 0x00000000 |
| 368 | #define DDRSS_CTL_351_DATA 0x00000000 |
| 369 | #define DDRSS_CTL_352_DATA 0x00000000 |
| 370 | #define DDRSS_CTL_353_DATA 0x00000000 |
| 371 | #define DDRSS_CTL_354_DATA 0x00000000 |
| 372 | #define DDRSS_CTL_355_DATA 0x00000000 |
| 373 | #define DDRSS_CTL_356_DATA 0x00000000 |
| 374 | #define DDRSS_CTL_357_DATA 0x00000000 |
| 375 | #define DDRSS_CTL_358_DATA 0x00000000 |
| 376 | #define DDRSS_CTL_359_DATA 0x00000000 |
| 377 | #define DDRSS_CTL_360_DATA 0x00000000 |
| 378 | #define DDRSS_CTL_361_DATA 0x00000000 |
| 379 | #define DDRSS_CTL_362_DATA 0x00000000 |
| 380 | #define DDRSS_CTL_363_DATA 0x00000000 |
| 381 | #define DDRSS_CTL_364_DATA 0x00000000 |
| 382 | #define DDRSS_CTL_365_DATA 0x00000000 |
| 383 | #define DDRSS_CTL_366_DATA 0x00000000 |
| 384 | #define DDRSS_CTL_367_DATA 0x00000000 |
| 385 | #define DDRSS_CTL_368_DATA 0x00000000 |
| 386 | #define DDRSS_CTL_369_DATA 0x00000000 |
| 387 | #define DDRSS_CTL_370_DATA 0x00000000 |
| 388 | #define DDRSS_CTL_371_DATA 0x01000101 |
| 389 | #define DDRSS_CTL_372_DATA 0x01010001 |
| 390 | #define DDRSS_CTL_373_DATA 0x00010101 |
| 391 | #define DDRSS_CTL_374_DATA 0x01050503 |
| 392 | #define DDRSS_CTL_375_DATA 0x05020201 |
| 393 | #define DDRSS_CTL_376_DATA 0x08080B0B |
| 394 | #define DDRSS_CTL_377_DATA 0x00080308 |
| 395 | #define DDRSS_CTL_378_DATA 0x000C030E |
| 396 | #define DDRSS_CTL_379_DATA 0x000C0310 |
| 397 | #define DDRSS_CTL_380_DATA 0x0C0C0810 |
| 398 | #define DDRSS_CTL_381_DATA 0x01000000 |
| 399 | #define DDRSS_CTL_382_DATA 0x03010301 |
| 400 | #define DDRSS_CTL_383_DATA 0x04000101 |
| 401 | #define DDRSS_CTL_384_DATA 0x1B000004 |
| 402 | #define DDRSS_CTL_385_DATA 0x00000176 |
| 403 | #define DDRSS_CTL_386_DATA 0x00000200 |
| 404 | #define DDRSS_CTL_387_DATA 0x00000200 |
| 405 | #define DDRSS_CTL_388_DATA 0x00000200 |
| 406 | #define DDRSS_CTL_389_DATA 0x00000200 |
| 407 | #define DDRSS_CTL_390_DATA 0x00000693 |
| 408 | #define DDRSS_CTL_391_DATA 0x00000E9C |
| 409 | #define DDRSS_CTL_392_DATA 0x03050202 |
| 410 | #define DDRSS_CTL_393_DATA 0x00240201 |
| 411 | #define DDRSS_CTL_394_DATA 0x00001440 |
| 412 | #define DDRSS_CTL_395_DATA 0x00000200 |
| 413 | #define DDRSS_CTL_396_DATA 0x00000200 |
| 414 | #define DDRSS_CTL_397_DATA 0x00000200 |
| 415 | #define DDRSS_CTL_398_DATA 0x00000200 |
| 416 | #define DDRSS_CTL_399_DATA 0x00005B20 |
| 417 | #define DDRSS_CTL_400_DATA 0x0000CA80 |
| 418 | #define DDRSS_CTL_401_DATA 0x080D0402 |
| 419 | #define DDRSS_CTL_402_DATA 0x00240405 |
| 420 | #define DDRSS_CTL_403_DATA 0x00001440 |
| 421 | #define DDRSS_CTL_404_DATA 0x00000200 |
| 422 | #define DDRSS_CTL_405_DATA 0x00000200 |
| 423 | #define DDRSS_CTL_406_DATA 0x00000200 |
| 424 | #define DDRSS_CTL_407_DATA 0x00000200 |
| 425 | #define DDRSS_CTL_408_DATA 0x00005B20 |
| 426 | #define DDRSS_CTL_409_DATA 0x0000CA80 |
| 427 | #define DDRSS_CTL_410_DATA 0x080D0402 |
| 428 | #define DDRSS_CTL_411_DATA 0x00000405 |
| 429 | #define DDRSS_CTL_412_DATA 0x00000000 |
| 430 | #define DDRSS_CTL_413_DATA 0x0302000A |
| 431 | #define DDRSS_CTL_414_DATA 0x01000500 |
| 432 | #define DDRSS_CTL_415_DATA 0x01010001 |
| 433 | #define DDRSS_CTL_416_DATA 0x00010001 |
| 434 | #define DDRSS_CTL_417_DATA 0x01010001 |
| 435 | #define DDRSS_CTL_418_DATA 0x02010000 |
| 436 | #define DDRSS_CTL_419_DATA 0x00000200 |
| 437 | #define DDRSS_CTL_420_DATA 0x02000201 |
| 438 | #define DDRSS_CTL_421_DATA 0x10100600 |
| 439 | #define DDRSS_CTL_422_DATA 0x00202020 |
| 440 | #define DDRSS_PI_0_DATA 0x00000B00 |
| 441 | #define DDRSS_PI_1_DATA 0x00000000 |
| 442 | #define DDRSS_PI_2_DATA 0x00000000 |
| 443 | #define DDRSS_PI_3_DATA 0x01000000 |
| 444 | #define DDRSS_PI_4_DATA 0x00000001 |
| 445 | #define DDRSS_PI_5_DATA 0x00010064 |
| 446 | #define DDRSS_PI_6_DATA 0x00000000 |
| 447 | #define DDRSS_PI_7_DATA 0x00000000 |
| 448 | #define DDRSS_PI_8_DATA 0x00000000 |
| 449 | #define DDRSS_PI_9_DATA 0x00000000 |
| 450 | #define DDRSS_PI_10_DATA 0x00000000 |
| 451 | #define DDRSS_PI_11_DATA 0x00000002 |
| 452 | #define DDRSS_PI_12_DATA 0x00000007 |
| 453 | #define DDRSS_PI_13_DATA 0x00010001 |
| 454 | #define DDRSS_PI_14_DATA 0x08000000 |
| 455 | #define DDRSS_PI_15_DATA 0x00010300 |
| 456 | #define DDRSS_PI_16_DATA 0x00000005 |
| 457 | #define DDRSS_PI_17_DATA 0x00000000 |
| 458 | #define DDRSS_PI_18_DATA 0x00000000 |
| 459 | #define DDRSS_PI_19_DATA 0x00000000 |
| 460 | #define DDRSS_PI_20_DATA 0x00000000 |
| 461 | #define DDRSS_PI_21_DATA 0x00000000 |
| 462 | #define DDRSS_PI_22_DATA 0x00000000 |
| 463 | #define DDRSS_PI_23_DATA 0x00010000 |
| 464 | #define DDRSS_PI_24_DATA 0x280A0001 |
| 465 | #define DDRSS_PI_25_DATA 0x00000000 |
| 466 | #define DDRSS_PI_26_DATA 0x00010000 |
| 467 | #define DDRSS_PI_27_DATA 0x00003200 |
| 468 | #define DDRSS_PI_28_DATA 0x00000000 |
| 469 | #define DDRSS_PI_29_DATA 0x00000000 |
| 470 | #define DDRSS_PI_30_DATA 0x01010102 |
| 471 | #define DDRSS_PI_31_DATA 0x00000000 |
| 472 | #define DDRSS_PI_32_DATA 0x00000000 |
| 473 | #define DDRSS_PI_33_DATA 0x00000000 |
| 474 | #define DDRSS_PI_34_DATA 0x00000001 |
| 475 | #define DDRSS_PI_35_DATA 0x000000AA |
| 476 | #define DDRSS_PI_36_DATA 0x00000055 |
| 477 | #define DDRSS_PI_37_DATA 0x000000B5 |
| 478 | #define DDRSS_PI_38_DATA 0x0000004A |
| 479 | #define DDRSS_PI_39_DATA 0x00000056 |
| 480 | #define DDRSS_PI_40_DATA 0x000000A9 |
| 481 | #define DDRSS_PI_41_DATA 0x000000A9 |
| 482 | #define DDRSS_PI_42_DATA 0x000000B5 |
| 483 | #define DDRSS_PI_43_DATA 0x00000000 |
| 484 | #define DDRSS_PI_44_DATA 0x00000000 |
| 485 | #define DDRSS_PI_45_DATA 0x00010100 |
| 486 | #define DDRSS_PI_46_DATA 0x00000014 |
| 487 | #define DDRSS_PI_47_DATA 0x000007D0 |
| 488 | #define DDRSS_PI_48_DATA 0x00000300 |
| 489 | #define DDRSS_PI_49_DATA 0x00000000 |
| 490 | #define DDRSS_PI_50_DATA 0x00000000 |
| 491 | #define DDRSS_PI_51_DATA 0x01000000 |
| 492 | #define DDRSS_PI_52_DATA 0x00010101 |
| 493 | #define DDRSS_PI_53_DATA 0x01000000 |
| 494 | #define DDRSS_PI_54_DATA 0x03000000 |
| 495 | #define DDRSS_PI_55_DATA 0x00000000 |
| 496 | #define DDRSS_PI_56_DATA 0x00001701 |
| 497 | #define DDRSS_PI_57_DATA 0x00000000 |
| 498 | #define DDRSS_PI_58_DATA 0x00000000 |
| 499 | #define DDRSS_PI_59_DATA 0x00000000 |
| 500 | #define DDRSS_PI_60_DATA 0x0A0A140A |
| 501 | #define DDRSS_PI_61_DATA 0x10020101 |
| 502 | #define DDRSS_PI_62_DATA 0x01000210 |
| 503 | #define DDRSS_PI_63_DATA 0x05000404 |
| 504 | #define DDRSS_PI_64_DATA 0x00010001 |
| 505 | #define DDRSS_PI_65_DATA 0x0001000E |
| 506 | #define DDRSS_PI_66_DATA 0x01010100 |
| 507 | #define DDRSS_PI_67_DATA 0x00010000 |
| 508 | #define DDRSS_PI_68_DATA 0x00000034 |
| 509 | #define DDRSS_PI_69_DATA 0x00000000 |
| 510 | #define DDRSS_PI_70_DATA 0x00000000 |
| 511 | #define DDRSS_PI_71_DATA 0x0000FFFF |
| 512 | #define DDRSS_PI_72_DATA 0x00000000 |
| 513 | #define DDRSS_PI_73_DATA 0x00000000 |
| 514 | #define DDRSS_PI_74_DATA 0x00000000 |
| 515 | #define DDRSS_PI_75_DATA 0x00000000 |
| 516 | #define DDRSS_PI_76_DATA 0x01000000 |
| 517 | #define DDRSS_PI_77_DATA 0x08000100 |
| 518 | #define DDRSS_PI_78_DATA 0x00020000 |
| 519 | #define DDRSS_PI_79_DATA 0x00010002 |
| 520 | #define DDRSS_PI_80_DATA 0x00000001 |
| 521 | #define DDRSS_PI_81_DATA 0x00020001 |
| 522 | #define DDRSS_PI_82_DATA 0x00020002 |
| 523 | #define DDRSS_PI_83_DATA 0x00000000 |
| 524 | #define DDRSS_PI_84_DATA 0x00000000 |
| 525 | #define DDRSS_PI_85_DATA 0x00000000 |
| 526 | #define DDRSS_PI_86_DATA 0x00000000 |
| 527 | #define DDRSS_PI_87_DATA 0x00000000 |
| 528 | #define DDRSS_PI_88_DATA 0x00000000 |
| 529 | #define DDRSS_PI_89_DATA 0x00000000 |
| 530 | #define DDRSS_PI_90_DATA 0x00000000 |
| 531 | #define DDRSS_PI_91_DATA 0x00000400 |
| 532 | #define DDRSS_PI_92_DATA 0x0A090B0C |
| 533 | #define DDRSS_PI_93_DATA 0x04060708 |
| 534 | #define DDRSS_PI_94_DATA 0x01000005 |
| 535 | #define DDRSS_PI_95_DATA 0x00000800 |
| 536 | #define DDRSS_PI_96_DATA 0x00000000 |
| 537 | #define DDRSS_PI_97_DATA 0x00010008 |
| 538 | #define DDRSS_PI_98_DATA 0x00000000 |
| 539 | #define DDRSS_PI_99_DATA 0x0000AA00 |
| 540 | #define DDRSS_PI_100_DATA 0x00000000 |
| 541 | #define DDRSS_PI_101_DATA 0x00010000 |
| 542 | #define DDRSS_PI_102_DATA 0x00000000 |
| 543 | #define DDRSS_PI_103_DATA 0x00000000 |
| 544 | #define DDRSS_PI_104_DATA 0x00000000 |
| 545 | #define DDRSS_PI_105_DATA 0x00000000 |
| 546 | #define DDRSS_PI_106_DATA 0x00000000 |
| 547 | #define DDRSS_PI_107_DATA 0x00000000 |
| 548 | #define DDRSS_PI_108_DATA 0x00000000 |
| 549 | #define DDRSS_PI_109_DATA 0x00000000 |
| 550 | #define DDRSS_PI_110_DATA 0x00000000 |
| 551 | #define DDRSS_PI_111_DATA 0x00000000 |
| 552 | #define DDRSS_PI_112_DATA 0x00000000 |
| 553 | #define DDRSS_PI_113_DATA 0x00000000 |
| 554 | #define DDRSS_PI_114_DATA 0x00000000 |
| 555 | #define DDRSS_PI_115_DATA 0x00000000 |
| 556 | #define DDRSS_PI_116_DATA 0x00000000 |
| 557 | #define DDRSS_PI_117_DATA 0x00000000 |
| 558 | #define DDRSS_PI_118_DATA 0x00000000 |
| 559 | #define DDRSS_PI_119_DATA 0x00000000 |
| 560 | #define DDRSS_PI_120_DATA 0x00000000 |
| 561 | #define DDRSS_PI_121_DATA 0x00000000 |
| 562 | #define DDRSS_PI_122_DATA 0x00000000 |
| 563 | #define DDRSS_PI_123_DATA 0x00000000 |
| 564 | #define DDRSS_PI_124_DATA 0x00000008 |
| 565 | #define DDRSS_PI_125_DATA 0x00000000 |
| 566 | #define DDRSS_PI_126_DATA 0x00000000 |
| 567 | #define DDRSS_PI_127_DATA 0x00000000 |
| 568 | #define DDRSS_PI_128_DATA 0x00000000 |
| 569 | #define DDRSS_PI_129_DATA 0x00000000 |
| 570 | #define DDRSS_PI_130_DATA 0x00000000 |
| 571 | #define DDRSS_PI_131_DATA 0x00000000 |
| 572 | #define DDRSS_PI_132_DATA 0x00000000 |
| 573 | #define DDRSS_PI_133_DATA 0x00010000 |
| 574 | #define DDRSS_PI_134_DATA 0x00000000 |
| 575 | #define DDRSS_PI_135_DATA 0x00000000 |
| 576 | #define DDRSS_PI_136_DATA 0x0000000A |
| 577 | #define DDRSS_PI_137_DATA 0x000186A0 |
| 578 | #define DDRSS_PI_138_DATA 0x00000100 |
| 579 | #define DDRSS_PI_139_DATA 0x00000000 |
| 580 | #define DDRSS_PI_140_DATA 0x00000000 |
| 581 | #define DDRSS_PI_141_DATA 0x00000000 |
| 582 | #define DDRSS_PI_142_DATA 0x00000000 |
| 583 | #define DDRSS_PI_143_DATA 0x00000000 |
| 584 | #define DDRSS_PI_144_DATA 0x01000000 |
| 585 | #define DDRSS_PI_145_DATA 0x00010003 |
| 586 | #define DDRSS_PI_146_DATA 0x02000101 |
| 587 | #define DDRSS_PI_147_DATA 0x01030001 |
| 588 | #define DDRSS_PI_148_DATA 0x00010400 |
| 589 | #define DDRSS_PI_149_DATA 0x06000105 |
| 590 | #define DDRSS_PI_150_DATA 0x01070001 |
| 591 | #define DDRSS_PI_151_DATA 0x00000000 |
| 592 | #define DDRSS_PI_152_DATA 0x00000000 |
| 593 | #define DDRSS_PI_153_DATA 0x00000000 |
| 594 | #define DDRSS_PI_154_DATA 0x00010001 |
| 595 | #define DDRSS_PI_155_DATA 0x00000000 |
| 596 | #define DDRSS_PI_156_DATA 0x00000000 |
| 597 | #define DDRSS_PI_157_DATA 0x00000000 |
| 598 | #define DDRSS_PI_158_DATA 0x00000000 |
| 599 | #define DDRSS_PI_159_DATA 0x00010000 |
| 600 | #define DDRSS_PI_160_DATA 0x00000004 |
| 601 | #define DDRSS_PI_161_DATA 0x00000000 |
| 602 | #define DDRSS_PI_162_DATA 0x00000000 |
| 603 | #define DDRSS_PI_163_DATA 0x00000000 |
| 604 | #define DDRSS_PI_164_DATA 0x00000800 |
| 605 | #define DDRSS_PI_165_DATA 0x00640064 |
| 606 | #define DDRSS_PI_166_DATA 0x000E0E01 |
| 607 | #define DDRSS_PI_167_DATA 0x00000034 |
| 608 | #define DDRSS_PI_168_DATA 0x00000042 |
| 609 | #define DDRSS_PI_169_DATA 0x00020042 |
| 610 | #define DDRSS_PI_170_DATA 0x02000200 |
| 611 | #define DDRSS_PI_171_DATA 0x00000004 |
| 612 | #define DDRSS_PI_172_DATA 0x0000080C |
| 613 | #define DDRSS_PI_173_DATA 0x00081C00 |
| 614 | #define DDRSS_PI_174_DATA 0x001C0000 |
| 615 | #define DDRSS_PI_175_DATA 0x00000013 |
| 616 | #define DDRSS_PI_176_DATA 0x000000BB |
| 617 | #define DDRSS_PI_177_DATA 0x000000FE |
| 618 | #define DDRSS_PI_178_DATA 0x00000A20 |
| 619 | #define DDRSS_PI_179_DATA 0x000000FE |
| 620 | #define DDRSS_PI_180_DATA 0x04000A20 |
| 621 | #define DDRSS_PI_181_DATA 0x01010404 |
| 622 | #define DDRSS_PI_182_DATA 0x00001501 |
| 623 | #define DDRSS_PI_183_DATA 0x001B001B |
| 624 | #define DDRSS_PI_184_DATA 0x01000100 |
| 625 | #define DDRSS_PI_185_DATA 0x00000100 |
| 626 | #define DDRSS_PI_186_DATA 0x00000000 |
| 627 | #define DDRSS_PI_187_DATA 0x05050503 |
| 628 | #define DDRSS_PI_188_DATA 0x01010B0B |
| 629 | #define DDRSS_PI_189_DATA 0x01010101 |
| 630 | #define DDRSS_PI_190_DATA 0x000C0C0A |
| 631 | #define DDRSS_PI_191_DATA 0x00000000 |
| 632 | #define DDRSS_PI_192_DATA 0x00000000 |
| 633 | #define DDRSS_PI_193_DATA 0x04000000 |
| 634 | #define DDRSS_PI_194_DATA 0x04020909 |
| 635 | #define DDRSS_PI_195_DATA 0x04040204 |
| 636 | #define DDRSS_PI_196_DATA 0x00090031 |
| 637 | #define DDRSS_PI_197_DATA 0x000F0037 |
| 638 | #define DDRSS_PI_198_DATA 0x000F0037 |
| 639 | #define DDRSS_PI_199_DATA 0x01010101 |
| 640 | #define DDRSS_PI_200_DATA 0x0001000D |
| 641 | #define DDRSS_PI_201_DATA 0x000100A7 |
| 642 | #define DDRSS_PI_202_DATA 0x010000A7 |
| 643 | #define DDRSS_PI_203_DATA 0x000E000E |
| 644 | #define DDRSS_PI_204_DATA 0x00A80100 |
| 645 | #define DDRSS_PI_205_DATA 0x010000A8 |
| 646 | #define DDRSS_PI_206_DATA 0x00A800A8 |
| 647 | #define DDRSS_PI_207_DATA 0x32103200 |
| 648 | #define DDRSS_PI_208_DATA 0x01013210 |
| 649 | #define DDRSS_PI_209_DATA 0x0A070601 |
| 650 | #define DDRSS_PI_210_DATA 0x0B08070D |
| 651 | #define DDRSS_PI_211_DATA 0x0B08070D |
| 652 | #define DDRSS_PI_212_DATA 0x000C000D |
| 653 | #define DDRSS_PI_213_DATA 0x00001000 |
| 654 | #define DDRSS_PI_214_DATA 0x00000C00 |
| 655 | #define DDRSS_PI_215_DATA 0x00001000 |
| 656 | #define DDRSS_PI_216_DATA 0x00000C00 |
| 657 | #define DDRSS_PI_217_DATA 0x02001000 |
| 658 | #define DDRSS_PI_218_DATA 0x0015000D |
| 659 | #define DDRSS_PI_219_DATA 0x001500A7 |
| 660 | #define DDRSS_PI_220_DATA 0x000000A7 |
| 661 | #define DDRSS_PI_221_DATA 0x00001900 |
| 662 | #define DDRSS_PI_222_DATA 0x32000056 |
| Sinthu Raja | 7b9717c | 2021-11-29 17:34:49 +0530 | [diff] [blame] | 663 | #define DDRSS_PI_223_DATA 0x06000101 |
| Lokesh Vutla | 86106ed | 2021-05-06 16:45:00 +0530 | [diff] [blame] | 664 | #define DDRSS_PI_224_DATA 0x001D0204 |
| 665 | #define DDRSS_PI_225_DATA 0x32120059 |
| Sinthu Raja | 7b9717c | 2021-11-29 17:34:49 +0530 | [diff] [blame] | 666 | #define DDRSS_PI_226_DATA 0x05000101 |
| Lokesh Vutla | 86106ed | 2021-05-06 16:45:00 +0530 | [diff] [blame] | 667 | #define DDRSS_PI_227_DATA 0x001D0409 |
| 668 | #define DDRSS_PI_228_DATA 0x32120059 |
| Sinthu Raja | 7b9717c | 2021-11-29 17:34:49 +0530 | [diff] [blame] | 669 | #define DDRSS_PI_229_DATA 0x05000101 |
| Lokesh Vutla | 86106ed | 2021-05-06 16:45:00 +0530 | [diff] [blame] | 670 | #define DDRSS_PI_230_DATA 0x00000409 |
| 671 | #define DDRSS_PI_231_DATA 0x05030900 |
| 672 | #define DDRSS_PI_232_DATA 0x00040900 |
| 673 | #define DDRSS_PI_233_DATA 0x0000062B |
| 674 | #define DDRSS_PI_234_DATA 0x20010004 |
| 675 | #define DDRSS_PI_235_DATA 0x0A0A0A03 |
| 676 | #define DDRSS_PI_236_DATA 0x0E090000 |
| 677 | #define DDRSS_PI_237_DATA 0x0E09000D |
| 678 | #define DDRSS_PI_238_DATA 0x00005244 |
| 679 | #define DDRSS_PI_239_DATA 0x2003001D |
| 680 | #define DDRSS_PI_240_DATA 0x0A0A0A0A |
| 681 | #define DDRSS_PI_241_DATA 0x0E090000 |
| 682 | #define DDRSS_PI_242_DATA 0x0E09000D |
| 683 | #define DDRSS_PI_243_DATA 0x00005244 |
| 684 | #define DDRSS_PI_244_DATA 0x2003001D |
| 685 | #define DDRSS_PI_245_DATA 0x0A0A0A0A |
| 686 | #define DDRSS_PI_246_DATA 0x00000000 |
| 687 | #define DDRSS_PI_247_DATA 0x00000176 |
| 688 | #define DDRSS_PI_248_DATA 0x00000E9C |
| 689 | #define DDRSS_PI_249_DATA 0x00001440 |
| 690 | #define DDRSS_PI_250_DATA 0x0000CA80 |
| 691 | #define DDRSS_PI_251_DATA 0x00001440 |
| 692 | #define DDRSS_PI_252_DATA 0x0000CA80 |
| 693 | #define DDRSS_PI_253_DATA 0x01030014 |
| 694 | #define DDRSS_PI_254_DATA 0x03030103 |
| 695 | #define DDRSS_PI_255_DATA 0x00000003 |
| 696 | #define DDRSS_PI_256_DATA 0x00000000 |
| 697 | #define DDRSS_PI_257_DATA 0x05030503 |
| 698 | #define DDRSS_PI_258_DATA 0x00000503 |
| 699 | #define DDRSS_PI_259_DATA 0x00002710 |
| 700 | #define DDRSS_PI_260_DATA 0x000186A0 |
| 701 | #define DDRSS_PI_261_DATA 0x00000005 |
| 702 | #define DDRSS_PI_262_DATA 0x00000064 |
| 703 | #define DDRSS_PI_263_DATA 0x00000014 |
| 704 | #define DDRSS_PI_264_DATA 0x000208D6 |
| 705 | #define DDRSS_PI_265_DATA 0x000186A0 |
| 706 | #define DDRSS_PI_266_DATA 0x00000005 |
| 707 | #define DDRSS_PI_267_DATA 0x00000536 |
| 708 | #define DDRSS_PI_268_DATA 0x00000103 |
| 709 | #define DDRSS_PI_269_DATA 0x000208D6 |
| 710 | #define DDRSS_PI_270_DATA 0x000186A0 |
| 711 | #define DDRSS_PI_271_DATA 0x00000005 |
| 712 | #define DDRSS_PI_272_DATA 0x00000536 |
| 713 | #define DDRSS_PI_273_DATA 0x01000103 |
| 714 | #define DDRSS_PI_274_DATA 0x00320040 |
| 715 | #define DDRSS_PI_275_DATA 0x00010008 |
| 716 | #define DDRSS_PI_276_DATA 0x029B0040 |
| 717 | #define DDRSS_PI_277_DATA 0x00010014 |
| 718 | #define DDRSS_PI_278_DATA 0x029B0040 |
| 719 | #define DDRSS_PI_279_DATA 0x00000314 |
| 720 | #define DDRSS_PI_280_DATA 0x00280021 |
| 721 | #define DDRSS_PI_281_DATA 0x03040404 |
| 722 | #define DDRSS_PI_282_DATA 0x00000303 |
| 723 | #define DDRSS_PI_283_DATA 0x02020101 |
| 724 | #define DDRSS_PI_284_DATA 0x67676767 |
| 725 | #define DDRSS_PI_285_DATA 0x00000000 |
| 726 | #define DDRSS_PI_286_DATA 0x55000000 |
| 727 | #define DDRSS_PI_287_DATA 0x00000000 |
| 728 | #define DDRSS_PI_288_DATA 0x3C00005A |
| 729 | #define DDRSS_PI_289_DATA 0x00005500 |
| 730 | #define DDRSS_PI_290_DATA 0x00005A00 |
| 731 | #define DDRSS_PI_291_DATA 0x0D100F3C |
| 732 | #define DDRSS_PI_292_DATA 0x0003020E |
| 733 | #define DDRSS_PI_293_DATA 0x00000001 |
| 734 | #define DDRSS_PI_294_DATA 0x01000000 |
| 735 | #define DDRSS_PI_295_DATA 0x00020201 |
| 736 | #define DDRSS_PI_296_DATA 0x00000000 |
| 737 | #define DDRSS_PI_297_DATA 0x00000000 |
| 738 | #define DDRSS_PI_298_DATA 0x00000004 |
| 739 | #define DDRSS_PI_299_DATA 0x00000000 |
| 740 | #define DDRSS_PI_300_DATA 0x00000031 |
| 741 | #define DDRSS_PI_301_DATA 0x00000000 |
| 742 | #define DDRSS_PI_302_DATA 0x00000000 |
| 743 | #define DDRSS_PI_303_DATA 0x00000000 |
| 744 | #define DDRSS_PI_304_DATA 0x00000F27 |
| 745 | #define DDRSS_PI_305_DATA 0x00000000 |
| 746 | #define DDRSS_PI_306_DATA 0x00000024 |
| 747 | #define DDRSS_PI_307_DATA 0x00000012 |
| 748 | #define DDRSS_PI_308_DATA 0x00000031 |
| 749 | #define DDRSS_PI_309_DATA 0x00000000 |
| 750 | #define DDRSS_PI_310_DATA 0x00000000 |
| Sinthu Raja | 7b9717c | 2021-11-29 17:34:49 +0530 | [diff] [blame] | 751 | #define DDRSS_PI_311_DATA 0x46000000 |
| Lokesh Vutla | 86106ed | 2021-05-06 16:45:00 +0530 | [diff] [blame] | 752 | #define DDRSS_PI_312_DATA 0x00150F27 |
| 753 | #define DDRSS_PI_313_DATA 0x00000000 |
| 754 | #define DDRSS_PI_314_DATA 0x00000024 |
| 755 | #define DDRSS_PI_315_DATA 0x00000012 |
| 756 | #define DDRSS_PI_316_DATA 0x00000031 |
| 757 | #define DDRSS_PI_317_DATA 0x00000000 |
| 758 | #define DDRSS_PI_318_DATA 0x00000000 |
| Sinthu Raja | 7b9717c | 2021-11-29 17:34:49 +0530 | [diff] [blame] | 759 | #define DDRSS_PI_319_DATA 0x46000000 |
| Lokesh Vutla | 86106ed | 2021-05-06 16:45:00 +0530 | [diff] [blame] | 760 | #define DDRSS_PI_320_DATA 0x00150F27 |
| 761 | #define DDRSS_PI_321_DATA 0x00000000 |
| 762 | #define DDRSS_PI_322_DATA 0x00000004 |
| 763 | #define DDRSS_PI_323_DATA 0x00000000 |
| 764 | #define DDRSS_PI_324_DATA 0x00000031 |
| 765 | #define DDRSS_PI_325_DATA 0x00000000 |
| 766 | #define DDRSS_PI_326_DATA 0x00000000 |
| 767 | #define DDRSS_PI_327_DATA 0x00000000 |
| 768 | #define DDRSS_PI_328_DATA 0x00000F27 |
| 769 | #define DDRSS_PI_329_DATA 0x00000000 |
| 770 | #define DDRSS_PI_330_DATA 0x00000024 |
| 771 | #define DDRSS_PI_331_DATA 0x00000012 |
| 772 | #define DDRSS_PI_332_DATA 0x00000031 |
| 773 | #define DDRSS_PI_333_DATA 0x00000000 |
| 774 | #define DDRSS_PI_334_DATA 0x00000000 |
| Sinthu Raja | 7b9717c | 2021-11-29 17:34:49 +0530 | [diff] [blame] | 775 | #define DDRSS_PI_335_DATA 0x46000000 |
| Lokesh Vutla | 86106ed | 2021-05-06 16:45:00 +0530 | [diff] [blame] | 776 | #define DDRSS_PI_336_DATA 0x00150F27 |
| 777 | #define DDRSS_PI_337_DATA 0x00000000 |
| 778 | #define DDRSS_PI_338_DATA 0x00000024 |
| 779 | #define DDRSS_PI_339_DATA 0x00000012 |
| 780 | #define DDRSS_PI_340_DATA 0x00000031 |
| 781 | #define DDRSS_PI_341_DATA 0x00000000 |
| 782 | #define DDRSS_PI_342_DATA 0x00000000 |
| Sinthu Raja | 7b9717c | 2021-11-29 17:34:49 +0530 | [diff] [blame] | 783 | #define DDRSS_PI_343_DATA 0x46000000 |
| Lokesh Vutla | 86106ed | 2021-05-06 16:45:00 +0530 | [diff] [blame] | 784 | #define DDRSS_PI_344_DATA 0x00150F27 |
| 785 | #define DDRSS_PHY_0_DATA 0x04F00000 |
| 786 | #define DDRSS_PHY_1_DATA 0x00000000 |
| 787 | #define DDRSS_PHY_2_DATA 0x00030200 |
| 788 | #define DDRSS_PHY_3_DATA 0x00000000 |
| 789 | #define DDRSS_PHY_4_DATA 0x00000000 |
| 790 | #define DDRSS_PHY_5_DATA 0x01000000 |
| 791 | #define DDRSS_PHY_6_DATA 0x03000400 |
| 792 | #define DDRSS_PHY_7_DATA 0x00000001 |
| 793 | #define DDRSS_PHY_8_DATA 0x00000001 |
| 794 | #define DDRSS_PHY_9_DATA 0x00000000 |
| 795 | #define DDRSS_PHY_10_DATA 0x00000000 |
| 796 | #define DDRSS_PHY_11_DATA 0x01010000 |
| 797 | #define DDRSS_PHY_12_DATA 0x00010000 |
| 798 | #define DDRSS_PHY_13_DATA 0x00C00001 |
| 799 | #define DDRSS_PHY_14_DATA 0x00CC0008 |
| 800 | #define DDRSS_PHY_15_DATA 0x00660601 |
| 801 | #define DDRSS_PHY_16_DATA 0x00000003 |
| 802 | #define DDRSS_PHY_17_DATA 0x00000000 |
| 803 | #define DDRSS_PHY_18_DATA 0x00000000 |
| 804 | #define DDRSS_PHY_19_DATA 0x0000AAAA |
| 805 | #define DDRSS_PHY_20_DATA 0x00005555 |
| 806 | #define DDRSS_PHY_21_DATA 0x0000B5B5 |
| 807 | #define DDRSS_PHY_22_DATA 0x00004A4A |
| 808 | #define DDRSS_PHY_23_DATA 0x00005656 |
| 809 | #define DDRSS_PHY_24_DATA 0x0000A9A9 |
| 810 | #define DDRSS_PHY_25_DATA 0x0000B7B7 |
| 811 | #define DDRSS_PHY_26_DATA 0x00004848 |
| 812 | #define DDRSS_PHY_27_DATA 0x00000000 |
| 813 | #define DDRSS_PHY_28_DATA 0x00000000 |
| 814 | #define DDRSS_PHY_29_DATA 0x08000000 |
| 815 | #define DDRSS_PHY_30_DATA 0x0F000008 |
| 816 | #define DDRSS_PHY_31_DATA 0x00000F0F |
| 817 | #define DDRSS_PHY_32_DATA 0x00E4E400 |
| 818 | #define DDRSS_PHY_33_DATA 0x00071020 |
| 819 | #define DDRSS_PHY_34_DATA 0x000C0020 |
| 820 | #define DDRSS_PHY_35_DATA 0x00062000 |
| 821 | #define DDRSS_PHY_36_DATA 0x00000000 |
| 822 | #define DDRSS_PHY_37_DATA 0x55555555 |
| 823 | #define DDRSS_PHY_38_DATA 0xAAAAAAAA |
| 824 | #define DDRSS_PHY_39_DATA 0x55555555 |
| 825 | #define DDRSS_PHY_40_DATA 0xAAAAAAAA |
| 826 | #define DDRSS_PHY_41_DATA 0x00005555 |
| 827 | #define DDRSS_PHY_42_DATA 0x01000100 |
| 828 | #define DDRSS_PHY_43_DATA 0x00800180 |
| 829 | #define DDRSS_PHY_44_DATA 0x00000001 |
| 830 | #define DDRSS_PHY_45_DATA 0x00000000 |
| 831 | #define DDRSS_PHY_46_DATA 0x00000000 |
| 832 | #define DDRSS_PHY_47_DATA 0x00000000 |
| 833 | #define DDRSS_PHY_48_DATA 0x00000000 |
| 834 | #define DDRSS_PHY_49_DATA 0x00000000 |
| 835 | #define DDRSS_PHY_50_DATA 0x00000000 |
| 836 | #define DDRSS_PHY_51_DATA 0x00000000 |
| 837 | #define DDRSS_PHY_52_DATA 0x00000000 |
| 838 | #define DDRSS_PHY_53_DATA 0x00000000 |
| 839 | #define DDRSS_PHY_54_DATA 0x00000000 |
| 840 | #define DDRSS_PHY_55_DATA 0x00000000 |
| 841 | #define DDRSS_PHY_56_DATA 0x00000000 |
| 842 | #define DDRSS_PHY_57_DATA 0x00000000 |
| 843 | #define DDRSS_PHY_58_DATA 0x00000000 |
| 844 | #define DDRSS_PHY_59_DATA 0x00000000 |
| 845 | #define DDRSS_PHY_60_DATA 0x00000000 |
| 846 | #define DDRSS_PHY_61_DATA 0x00000000 |
| 847 | #define DDRSS_PHY_62_DATA 0x00000000 |
| 848 | #define DDRSS_PHY_63_DATA 0x00000000 |
| 849 | #define DDRSS_PHY_64_DATA 0x00000000 |
| 850 | #define DDRSS_PHY_65_DATA 0x00000004 |
| 851 | #define DDRSS_PHY_66_DATA 0x00000000 |
| 852 | #define DDRSS_PHY_67_DATA 0x00000000 |
| 853 | #define DDRSS_PHY_68_DATA 0x00000000 |
| 854 | #define DDRSS_PHY_69_DATA 0x00000000 |
| 855 | #define DDRSS_PHY_70_DATA 0x00000000 |
| 856 | #define DDRSS_PHY_71_DATA 0x00000000 |
| 857 | #define DDRSS_PHY_72_DATA 0x041F07FF |
| 858 | #define DDRSS_PHY_73_DATA 0x00000000 |
| 859 | #define DDRSS_PHY_74_DATA 0x01CC0B01 |
| 860 | #define DDRSS_PHY_75_DATA 0x1003CC0B |
| 861 | #define DDRSS_PHY_76_DATA 0x20000140 |
| 862 | #define DDRSS_PHY_77_DATA 0x07FF0200 |
| 863 | #define DDRSS_PHY_78_DATA 0x0000DD01 |
| 864 | #define DDRSS_PHY_79_DATA 0x00100303 |
| 865 | #define DDRSS_PHY_80_DATA 0x00000000 |
| 866 | #define DDRSS_PHY_81_DATA 0x00000000 |
| 867 | #define DDRSS_PHY_82_DATA 0x00021000 |
| 868 | #define DDRSS_PHY_83_DATA 0x00100010 |
| 869 | #define DDRSS_PHY_84_DATA 0x00100010 |
| 870 | #define DDRSS_PHY_85_DATA 0x00100010 |
| 871 | #define DDRSS_PHY_86_DATA 0x00100010 |
| 872 | #define DDRSS_PHY_87_DATA 0x02000010 |
| 873 | #define DDRSS_PHY_88_DATA 0x51516041 |
| 874 | #define DDRSS_PHY_89_DATA 0x31C06000 |
| 875 | #define DDRSS_PHY_90_DATA 0x07AB0340 |
| Sinthu Raja | 7b9717c | 2021-11-29 17:34:49 +0530 | [diff] [blame] | 876 | #define DDRSS_PHY_91_DATA 0x0000C0C0 |
| Lokesh Vutla | 86106ed | 2021-05-06 16:45:00 +0530 | [diff] [blame] | 877 | #define DDRSS_PHY_92_DATA 0x03040000 |
| 878 | #define DDRSS_PHY_93_DATA 0x00000403 |
| 879 | #define DDRSS_PHY_94_DATA 0x42100010 |
| 880 | #define DDRSS_PHY_95_DATA 0x010C053E |
| 881 | #define DDRSS_PHY_96_DATA 0x000F0C1A |
| 882 | #define DDRSS_PHY_97_DATA 0x01000140 |
| 883 | #define DDRSS_PHY_98_DATA 0x00660120 |
| 884 | #define DDRSS_PHY_99_DATA 0x00000C00 |
| 885 | #define DDRSS_PHY_100_DATA 0x000001AA |
| 886 | #define DDRSS_PHY_101_DATA 0x20100200 |
| 887 | #define DDRSS_PHY_102_DATA 0x00000004 |
| 888 | #define DDRSS_PHY_103_DATA 0x76543210 |
| 889 | #define DDRSS_PHY_104_DATA 0x00000008 |
| 890 | #define DDRSS_PHY_105_DATA 0x032A032A |
| 891 | #define DDRSS_PHY_106_DATA 0x032A032A |
| 892 | #define DDRSS_PHY_107_DATA 0x032A032A |
| 893 | #define DDRSS_PHY_108_DATA 0x032A032A |
| 894 | #define DDRSS_PHY_109_DATA 0x0000032A |
| 895 | #define DDRSS_PHY_110_DATA 0x00008000 |
| 896 | #define DDRSS_PHY_111_DATA 0x00800080 |
| 897 | #define DDRSS_PHY_112_DATA 0x00800080 |
| 898 | #define DDRSS_PHY_113_DATA 0x00800080 |
| 899 | #define DDRSS_PHY_114_DATA 0x00800080 |
| 900 | #define DDRSS_PHY_115_DATA 0x00800080 |
| 901 | #define DDRSS_PHY_116_DATA 0x00800080 |
| 902 | #define DDRSS_PHY_117_DATA 0x00800080 |
| 903 | #define DDRSS_PHY_118_DATA 0x00800080 |
| 904 | #define DDRSS_PHY_119_DATA 0x01190080 |
| 905 | #define DDRSS_PHY_120_DATA 0x01A00001 |
| 906 | #define DDRSS_PHY_121_DATA 0x00000000 |
| 907 | #define DDRSS_PHY_122_DATA 0x00000000 |
| 908 | #define DDRSS_PHY_123_DATA 0x00080200 |
| 909 | #define DDRSS_PHY_124_DATA 0x00000000 |
| 910 | #define DDRSS_PHY_125_DATA 0x0000F0F0 |
| 911 | #define DDRSS_PHY_126_DATA 0x00000000 |
| 912 | #define DDRSS_PHY_127_DATA 0x00000000 |
| 913 | #define DDRSS_PHY_128_DATA 0x00000000 |
| 914 | #define DDRSS_PHY_129_DATA 0x00000000 |
| 915 | #define DDRSS_PHY_130_DATA 0x00000000 |
| 916 | #define DDRSS_PHY_131_DATA 0x00000000 |
| 917 | #define DDRSS_PHY_132_DATA 0x00000000 |
| 918 | #define DDRSS_PHY_133_DATA 0x00000000 |
| 919 | #define DDRSS_PHY_134_DATA 0x00000000 |
| 920 | #define DDRSS_PHY_135_DATA 0x00000000 |
| 921 | #define DDRSS_PHY_136_DATA 0x00000000 |
| 922 | #define DDRSS_PHY_137_DATA 0x00000000 |
| 923 | #define DDRSS_PHY_138_DATA 0x00000000 |
| 924 | #define DDRSS_PHY_139_DATA 0x00000000 |
| 925 | #define DDRSS_PHY_140_DATA 0x00000000 |
| 926 | #define DDRSS_PHY_141_DATA 0x00000000 |
| 927 | #define DDRSS_PHY_142_DATA 0x00000000 |
| 928 | #define DDRSS_PHY_143_DATA 0x00000000 |
| 929 | #define DDRSS_PHY_144_DATA 0x00000000 |
| 930 | #define DDRSS_PHY_145_DATA 0x00000000 |
| 931 | #define DDRSS_PHY_146_DATA 0x00000000 |
| 932 | #define DDRSS_PHY_147_DATA 0x00000000 |
| 933 | #define DDRSS_PHY_148_DATA 0x00000000 |
| 934 | #define DDRSS_PHY_149_DATA 0x00000000 |
| 935 | #define DDRSS_PHY_150_DATA 0x00000000 |
| 936 | #define DDRSS_PHY_151_DATA 0x00000000 |
| 937 | #define DDRSS_PHY_152_DATA 0x00000000 |
| 938 | #define DDRSS_PHY_153_DATA 0x00000000 |
| 939 | #define DDRSS_PHY_154_DATA 0x00000000 |
| 940 | #define DDRSS_PHY_155_DATA 0x00000000 |
| 941 | #define DDRSS_PHY_156_DATA 0x00000000 |
| 942 | #define DDRSS_PHY_157_DATA 0x00000000 |
| 943 | #define DDRSS_PHY_158_DATA 0x00000000 |
| 944 | #define DDRSS_PHY_159_DATA 0x00000000 |
| 945 | #define DDRSS_PHY_160_DATA 0x00000000 |
| 946 | #define DDRSS_PHY_161_DATA 0x00000000 |
| 947 | #define DDRSS_PHY_162_DATA 0x00000000 |
| 948 | #define DDRSS_PHY_163_DATA 0x00000000 |
| 949 | #define DDRSS_PHY_164_DATA 0x00000000 |
| 950 | #define DDRSS_PHY_165_DATA 0x00000000 |
| 951 | #define DDRSS_PHY_166_DATA 0x00000000 |
| 952 | #define DDRSS_PHY_167_DATA 0x00000000 |
| 953 | #define DDRSS_PHY_168_DATA 0x00000000 |
| 954 | #define DDRSS_PHY_169_DATA 0x00000000 |
| 955 | #define DDRSS_PHY_170_DATA 0x00000000 |
| 956 | #define DDRSS_PHY_171_DATA 0x00000000 |
| 957 | #define DDRSS_PHY_172_DATA 0x00000000 |
| 958 | #define DDRSS_PHY_173_DATA 0x00000000 |
| 959 | #define DDRSS_PHY_174_DATA 0x00000000 |
| 960 | #define DDRSS_PHY_175_DATA 0x00000000 |
| 961 | #define DDRSS_PHY_176_DATA 0x00000000 |
| 962 | #define DDRSS_PHY_177_DATA 0x00000000 |
| 963 | #define DDRSS_PHY_178_DATA 0x00000000 |
| 964 | #define DDRSS_PHY_179_DATA 0x00000000 |
| 965 | #define DDRSS_PHY_180_DATA 0x00000000 |
| 966 | #define DDRSS_PHY_181_DATA 0x00000000 |
| 967 | #define DDRSS_PHY_182_DATA 0x00000000 |
| 968 | #define DDRSS_PHY_183_DATA 0x00000000 |
| 969 | #define DDRSS_PHY_184_DATA 0x00000000 |
| 970 | #define DDRSS_PHY_185_DATA 0x00000000 |
| 971 | #define DDRSS_PHY_186_DATA 0x00000000 |
| 972 | #define DDRSS_PHY_187_DATA 0x00000000 |
| 973 | #define DDRSS_PHY_188_DATA 0x00000000 |
| 974 | #define DDRSS_PHY_189_DATA 0x00000000 |
| 975 | #define DDRSS_PHY_190_DATA 0x00000000 |
| 976 | #define DDRSS_PHY_191_DATA 0x00000000 |
| 977 | #define DDRSS_PHY_192_DATA 0x00000000 |
| 978 | #define DDRSS_PHY_193_DATA 0x00000000 |
| 979 | #define DDRSS_PHY_194_DATA 0x00000000 |
| 980 | #define DDRSS_PHY_195_DATA 0x00000000 |
| 981 | #define DDRSS_PHY_196_DATA 0x00000000 |
| 982 | #define DDRSS_PHY_197_DATA 0x00000000 |
| 983 | #define DDRSS_PHY_198_DATA 0x00000000 |
| 984 | #define DDRSS_PHY_199_DATA 0x00000000 |
| 985 | #define DDRSS_PHY_200_DATA 0x00000000 |
| 986 | #define DDRSS_PHY_201_DATA 0x00000000 |
| 987 | #define DDRSS_PHY_202_DATA 0x00000000 |
| 988 | #define DDRSS_PHY_203_DATA 0x00000000 |
| 989 | #define DDRSS_PHY_204_DATA 0x00000000 |
| 990 | #define DDRSS_PHY_205_DATA 0x00000000 |
| 991 | #define DDRSS_PHY_206_DATA 0x00000000 |
| 992 | #define DDRSS_PHY_207_DATA 0x00000000 |
| 993 | #define DDRSS_PHY_208_DATA 0x00000000 |
| 994 | #define DDRSS_PHY_209_DATA 0x00000000 |
| 995 | #define DDRSS_PHY_210_DATA 0x00000000 |
| 996 | #define DDRSS_PHY_211_DATA 0x00000000 |
| 997 | #define DDRSS_PHY_212_DATA 0x00000000 |
| 998 | #define DDRSS_PHY_213_DATA 0x00000000 |
| 999 | #define DDRSS_PHY_214_DATA 0x00000000 |
| 1000 | #define DDRSS_PHY_215_DATA 0x00000000 |
| 1001 | #define DDRSS_PHY_216_DATA 0x00000000 |
| 1002 | #define DDRSS_PHY_217_DATA 0x00000000 |
| 1003 | #define DDRSS_PHY_218_DATA 0x00000000 |
| 1004 | #define DDRSS_PHY_219_DATA 0x00000000 |
| 1005 | #define DDRSS_PHY_220_DATA 0x00000000 |
| 1006 | #define DDRSS_PHY_221_DATA 0x00000000 |
| 1007 | #define DDRSS_PHY_222_DATA 0x00000000 |
| 1008 | #define DDRSS_PHY_223_DATA 0x00000000 |
| 1009 | #define DDRSS_PHY_224_DATA 0x00000000 |
| 1010 | #define DDRSS_PHY_225_DATA 0x00000000 |
| 1011 | #define DDRSS_PHY_226_DATA 0x00000000 |
| 1012 | #define DDRSS_PHY_227_DATA 0x00000000 |
| 1013 | #define DDRSS_PHY_228_DATA 0x00000000 |
| 1014 | #define DDRSS_PHY_229_DATA 0x00000000 |
| 1015 | #define DDRSS_PHY_230_DATA 0x00000000 |
| 1016 | #define DDRSS_PHY_231_DATA 0x00000000 |
| 1017 | #define DDRSS_PHY_232_DATA 0x00000000 |
| 1018 | #define DDRSS_PHY_233_DATA 0x00000000 |
| 1019 | #define DDRSS_PHY_234_DATA 0x00000000 |
| 1020 | #define DDRSS_PHY_235_DATA 0x00000000 |
| 1021 | #define DDRSS_PHY_236_DATA 0x00000000 |
| 1022 | #define DDRSS_PHY_237_DATA 0x00000000 |
| 1023 | #define DDRSS_PHY_238_DATA 0x00000000 |
| 1024 | #define DDRSS_PHY_239_DATA 0x00000000 |
| 1025 | #define DDRSS_PHY_240_DATA 0x00000000 |
| 1026 | #define DDRSS_PHY_241_DATA 0x00000000 |
| 1027 | #define DDRSS_PHY_242_DATA 0x00000000 |
| 1028 | #define DDRSS_PHY_243_DATA 0x00000000 |
| 1029 | #define DDRSS_PHY_244_DATA 0x00000000 |
| 1030 | #define DDRSS_PHY_245_DATA 0x00000000 |
| 1031 | #define DDRSS_PHY_246_DATA 0x00000000 |
| 1032 | #define DDRSS_PHY_247_DATA 0x00000000 |
| 1033 | #define DDRSS_PHY_248_DATA 0x00000000 |
| 1034 | #define DDRSS_PHY_249_DATA 0x00000000 |
| 1035 | #define DDRSS_PHY_250_DATA 0x00000000 |
| 1036 | #define DDRSS_PHY_251_DATA 0x00000000 |
| 1037 | #define DDRSS_PHY_252_DATA 0x00000000 |
| 1038 | #define DDRSS_PHY_253_DATA 0x00000000 |
| 1039 | #define DDRSS_PHY_254_DATA 0x00000000 |
| 1040 | #define DDRSS_PHY_255_DATA 0x00000000 |
| 1041 | #define DDRSS_PHY_256_DATA 0x04F00000 |
| 1042 | #define DDRSS_PHY_257_DATA 0x00000000 |
| 1043 | #define DDRSS_PHY_258_DATA 0x00030200 |
| 1044 | #define DDRSS_PHY_259_DATA 0x00000000 |
| 1045 | #define DDRSS_PHY_260_DATA 0x00000000 |
| 1046 | #define DDRSS_PHY_261_DATA 0x01000000 |
| 1047 | #define DDRSS_PHY_262_DATA 0x03000400 |
| 1048 | #define DDRSS_PHY_263_DATA 0x00000001 |
| 1049 | #define DDRSS_PHY_264_DATA 0x00000001 |
| 1050 | #define DDRSS_PHY_265_DATA 0x00000000 |
| 1051 | #define DDRSS_PHY_266_DATA 0x00000000 |
| 1052 | #define DDRSS_PHY_267_DATA 0x01010000 |
| 1053 | #define DDRSS_PHY_268_DATA 0x00010000 |
| 1054 | #define DDRSS_PHY_269_DATA 0x00C00001 |
| 1055 | #define DDRSS_PHY_270_DATA 0x00CC0008 |
| 1056 | #define DDRSS_PHY_271_DATA 0x00660601 |
| 1057 | #define DDRSS_PHY_272_DATA 0x00000003 |
| 1058 | #define DDRSS_PHY_273_DATA 0x00000000 |
| 1059 | #define DDRSS_PHY_274_DATA 0x00000000 |
| 1060 | #define DDRSS_PHY_275_DATA 0x0000AAAA |
| 1061 | #define DDRSS_PHY_276_DATA 0x00005555 |
| 1062 | #define DDRSS_PHY_277_DATA 0x0000B5B5 |
| 1063 | #define DDRSS_PHY_278_DATA 0x00004A4A |
| 1064 | #define DDRSS_PHY_279_DATA 0x00005656 |
| 1065 | #define DDRSS_PHY_280_DATA 0x0000A9A9 |
| 1066 | #define DDRSS_PHY_281_DATA 0x0000B7B7 |
| 1067 | #define DDRSS_PHY_282_DATA 0x00004848 |
| 1068 | #define DDRSS_PHY_283_DATA 0x00000000 |
| 1069 | #define DDRSS_PHY_284_DATA 0x00000000 |
| 1070 | #define DDRSS_PHY_285_DATA 0x08000000 |
| 1071 | #define DDRSS_PHY_286_DATA 0x0F000008 |
| 1072 | #define DDRSS_PHY_287_DATA 0x00000F0F |
| 1073 | #define DDRSS_PHY_288_DATA 0x00E4E400 |
| 1074 | #define DDRSS_PHY_289_DATA 0x00071020 |
| 1075 | #define DDRSS_PHY_290_DATA 0x000C0020 |
| 1076 | #define DDRSS_PHY_291_DATA 0x00062000 |
| 1077 | #define DDRSS_PHY_292_DATA 0x00000000 |
| 1078 | #define DDRSS_PHY_293_DATA 0x55555555 |
| 1079 | #define DDRSS_PHY_294_DATA 0xAAAAAAAA |
| 1080 | #define DDRSS_PHY_295_DATA 0x55555555 |
| 1081 | #define DDRSS_PHY_296_DATA 0xAAAAAAAA |
| 1082 | #define DDRSS_PHY_297_DATA 0x00005555 |
| 1083 | #define DDRSS_PHY_298_DATA 0x01000100 |
| 1084 | #define DDRSS_PHY_299_DATA 0x00800180 |
| 1085 | #define DDRSS_PHY_300_DATA 0x00000000 |
| 1086 | #define DDRSS_PHY_301_DATA 0x00000000 |
| 1087 | #define DDRSS_PHY_302_DATA 0x00000000 |
| 1088 | #define DDRSS_PHY_303_DATA 0x00000000 |
| 1089 | #define DDRSS_PHY_304_DATA 0x00000000 |
| 1090 | #define DDRSS_PHY_305_DATA 0x00000000 |
| 1091 | #define DDRSS_PHY_306_DATA 0x00000000 |
| 1092 | #define DDRSS_PHY_307_DATA 0x00000000 |
| 1093 | #define DDRSS_PHY_308_DATA 0x00000000 |
| 1094 | #define DDRSS_PHY_309_DATA 0x00000000 |
| 1095 | #define DDRSS_PHY_310_DATA 0x00000000 |
| 1096 | #define DDRSS_PHY_311_DATA 0x00000000 |
| 1097 | #define DDRSS_PHY_312_DATA 0x00000000 |
| 1098 | #define DDRSS_PHY_313_DATA 0x00000000 |
| 1099 | #define DDRSS_PHY_314_DATA 0x00000000 |
| 1100 | #define DDRSS_PHY_315_DATA 0x00000000 |
| 1101 | #define DDRSS_PHY_316_DATA 0x00000000 |
| 1102 | #define DDRSS_PHY_317_DATA 0x00000000 |
| 1103 | #define DDRSS_PHY_318_DATA 0x00000000 |
| 1104 | #define DDRSS_PHY_319_DATA 0x00000000 |
| 1105 | #define DDRSS_PHY_320_DATA 0x00000000 |
| 1106 | #define DDRSS_PHY_321_DATA 0x00000004 |
| 1107 | #define DDRSS_PHY_322_DATA 0x00000000 |
| 1108 | #define DDRSS_PHY_323_DATA 0x00000000 |
| 1109 | #define DDRSS_PHY_324_DATA 0x00000000 |
| 1110 | #define DDRSS_PHY_325_DATA 0x00000000 |
| 1111 | #define DDRSS_PHY_326_DATA 0x00000000 |
| 1112 | #define DDRSS_PHY_327_DATA 0x00000000 |
| 1113 | #define DDRSS_PHY_328_DATA 0x041F07FF |
| 1114 | #define DDRSS_PHY_329_DATA 0x00000000 |
| 1115 | #define DDRSS_PHY_330_DATA 0x01CC0B01 |
| 1116 | #define DDRSS_PHY_331_DATA 0x1003CC0B |
| 1117 | #define DDRSS_PHY_332_DATA 0x20000140 |
| 1118 | #define DDRSS_PHY_333_DATA 0x07FF0200 |
| 1119 | #define DDRSS_PHY_334_DATA 0x0000DD01 |
| 1120 | #define DDRSS_PHY_335_DATA 0x00100303 |
| 1121 | #define DDRSS_PHY_336_DATA 0x00000000 |
| 1122 | #define DDRSS_PHY_337_DATA 0x00000000 |
| 1123 | #define DDRSS_PHY_338_DATA 0x00021000 |
| 1124 | #define DDRSS_PHY_339_DATA 0x00100010 |
| 1125 | #define DDRSS_PHY_340_DATA 0x00100010 |
| 1126 | #define DDRSS_PHY_341_DATA 0x00100010 |
| 1127 | #define DDRSS_PHY_342_DATA 0x00100010 |
| 1128 | #define DDRSS_PHY_343_DATA 0x02000010 |
| 1129 | #define DDRSS_PHY_344_DATA 0x51516041 |
| 1130 | #define DDRSS_PHY_345_DATA 0x31C06000 |
| 1131 | #define DDRSS_PHY_346_DATA 0x07AB0340 |
| Sinthu Raja | 7b9717c | 2021-11-29 17:34:49 +0530 | [diff] [blame] | 1132 | #define DDRSS_PHY_347_DATA 0x0000C0C0 |
| Lokesh Vutla | 86106ed | 2021-05-06 16:45:00 +0530 | [diff] [blame] | 1133 | #define DDRSS_PHY_348_DATA 0x03040000 |
| 1134 | #define DDRSS_PHY_349_DATA 0x00000403 |
| 1135 | #define DDRSS_PHY_350_DATA 0x42100010 |
| 1136 | #define DDRSS_PHY_351_DATA 0x010C053E |
| 1137 | #define DDRSS_PHY_352_DATA 0x000F0C1A |
| 1138 | #define DDRSS_PHY_353_DATA 0x01000140 |
| 1139 | #define DDRSS_PHY_354_DATA 0x00660120 |
| 1140 | #define DDRSS_PHY_355_DATA 0x00000C00 |
| 1141 | #define DDRSS_PHY_356_DATA 0x000001AA |
| 1142 | #define DDRSS_PHY_357_DATA 0x20100200 |
| 1143 | #define DDRSS_PHY_358_DATA 0x00000004 |
| 1144 | #define DDRSS_PHY_359_DATA 0x76543210 |
| 1145 | #define DDRSS_PHY_360_DATA 0x00000008 |
| 1146 | #define DDRSS_PHY_361_DATA 0x032A032A |
| 1147 | #define DDRSS_PHY_362_DATA 0x032A032A |
| 1148 | #define DDRSS_PHY_363_DATA 0x032A032A |
| 1149 | #define DDRSS_PHY_364_DATA 0x032A032A |
| 1150 | #define DDRSS_PHY_365_DATA 0x0000032A |
| 1151 | #define DDRSS_PHY_366_DATA 0x00008000 |
| 1152 | #define DDRSS_PHY_367_DATA 0x00800080 |
| 1153 | #define DDRSS_PHY_368_DATA 0x00800080 |
| 1154 | #define DDRSS_PHY_369_DATA 0x00800080 |
| 1155 | #define DDRSS_PHY_370_DATA 0x00800080 |
| 1156 | #define DDRSS_PHY_371_DATA 0x00800080 |
| 1157 | #define DDRSS_PHY_372_DATA 0x00800080 |
| 1158 | #define DDRSS_PHY_373_DATA 0x00800080 |
| 1159 | #define DDRSS_PHY_374_DATA 0x00800080 |
| 1160 | #define DDRSS_PHY_375_DATA 0x01190080 |
| 1161 | #define DDRSS_PHY_376_DATA 0x01A00001 |
| 1162 | #define DDRSS_PHY_377_DATA 0x00000000 |
| 1163 | #define DDRSS_PHY_378_DATA 0x00000000 |
| 1164 | #define DDRSS_PHY_379_DATA 0x00080200 |
| 1165 | #define DDRSS_PHY_380_DATA 0x00000000 |
| 1166 | #define DDRSS_PHY_381_DATA 0x0000F0F0 |
| 1167 | #define DDRSS_PHY_382_DATA 0x00000000 |
| 1168 | #define DDRSS_PHY_383_DATA 0x00000000 |
| 1169 | #define DDRSS_PHY_384_DATA 0x00000000 |
| 1170 | #define DDRSS_PHY_385_DATA 0x00000000 |
| 1171 | #define DDRSS_PHY_386_DATA 0x00000000 |
| 1172 | #define DDRSS_PHY_387_DATA 0x00000000 |
| 1173 | #define DDRSS_PHY_388_DATA 0x00000000 |
| 1174 | #define DDRSS_PHY_389_DATA 0x00000000 |
| 1175 | #define DDRSS_PHY_390_DATA 0x00000000 |
| 1176 | #define DDRSS_PHY_391_DATA 0x00000000 |
| 1177 | #define DDRSS_PHY_392_DATA 0x00000000 |
| 1178 | #define DDRSS_PHY_393_DATA 0x00000000 |
| 1179 | #define DDRSS_PHY_394_DATA 0x00000000 |
| 1180 | #define DDRSS_PHY_395_DATA 0x00000000 |
| 1181 | #define DDRSS_PHY_396_DATA 0x00000000 |
| 1182 | #define DDRSS_PHY_397_DATA 0x00000000 |
| 1183 | #define DDRSS_PHY_398_DATA 0x00000000 |
| 1184 | #define DDRSS_PHY_399_DATA 0x00000000 |
| 1185 | #define DDRSS_PHY_400_DATA 0x00000000 |
| 1186 | #define DDRSS_PHY_401_DATA 0x00000000 |
| 1187 | #define DDRSS_PHY_402_DATA 0x00000000 |
| 1188 | #define DDRSS_PHY_403_DATA 0x00000000 |
| 1189 | #define DDRSS_PHY_404_DATA 0x00000000 |
| 1190 | #define DDRSS_PHY_405_DATA 0x00000000 |
| 1191 | #define DDRSS_PHY_406_DATA 0x00000000 |
| 1192 | #define DDRSS_PHY_407_DATA 0x00000000 |
| 1193 | #define DDRSS_PHY_408_DATA 0x00000000 |
| 1194 | #define DDRSS_PHY_409_DATA 0x00000000 |
| 1195 | #define DDRSS_PHY_410_DATA 0x00000000 |
| 1196 | #define DDRSS_PHY_411_DATA 0x00000000 |
| 1197 | #define DDRSS_PHY_412_DATA 0x00000000 |
| 1198 | #define DDRSS_PHY_413_DATA 0x00000000 |
| 1199 | #define DDRSS_PHY_414_DATA 0x00000000 |
| 1200 | #define DDRSS_PHY_415_DATA 0x00000000 |
| 1201 | #define DDRSS_PHY_416_DATA 0x00000000 |
| 1202 | #define DDRSS_PHY_417_DATA 0x00000000 |
| 1203 | #define DDRSS_PHY_418_DATA 0x00000000 |
| 1204 | #define DDRSS_PHY_419_DATA 0x00000000 |
| 1205 | #define DDRSS_PHY_420_DATA 0x00000000 |
| 1206 | #define DDRSS_PHY_421_DATA 0x00000000 |
| 1207 | #define DDRSS_PHY_422_DATA 0x00000000 |
| 1208 | #define DDRSS_PHY_423_DATA 0x00000000 |
| 1209 | #define DDRSS_PHY_424_DATA 0x00000000 |
| 1210 | #define DDRSS_PHY_425_DATA 0x00000000 |
| 1211 | #define DDRSS_PHY_426_DATA 0x00000000 |
| 1212 | #define DDRSS_PHY_427_DATA 0x00000000 |
| 1213 | #define DDRSS_PHY_428_DATA 0x00000000 |
| 1214 | #define DDRSS_PHY_429_DATA 0x00000000 |
| 1215 | #define DDRSS_PHY_430_DATA 0x00000000 |
| 1216 | #define DDRSS_PHY_431_DATA 0x00000000 |
| 1217 | #define DDRSS_PHY_432_DATA 0x00000000 |
| 1218 | #define DDRSS_PHY_433_DATA 0x00000000 |
| 1219 | #define DDRSS_PHY_434_DATA 0x00000000 |
| 1220 | #define DDRSS_PHY_435_DATA 0x00000000 |
| 1221 | #define DDRSS_PHY_436_DATA 0x00000000 |
| 1222 | #define DDRSS_PHY_437_DATA 0x00000000 |
| 1223 | #define DDRSS_PHY_438_DATA 0x00000000 |
| 1224 | #define DDRSS_PHY_439_DATA 0x00000000 |
| 1225 | #define DDRSS_PHY_440_DATA 0x00000000 |
| 1226 | #define DDRSS_PHY_441_DATA 0x00000000 |
| 1227 | #define DDRSS_PHY_442_DATA 0x00000000 |
| 1228 | #define DDRSS_PHY_443_DATA 0x00000000 |
| 1229 | #define DDRSS_PHY_444_DATA 0x00000000 |
| 1230 | #define DDRSS_PHY_445_DATA 0x00000000 |
| 1231 | #define DDRSS_PHY_446_DATA 0x00000000 |
| 1232 | #define DDRSS_PHY_447_DATA 0x00000000 |
| 1233 | #define DDRSS_PHY_448_DATA 0x00000000 |
| 1234 | #define DDRSS_PHY_449_DATA 0x00000000 |
| 1235 | #define DDRSS_PHY_450_DATA 0x00000000 |
| 1236 | #define DDRSS_PHY_451_DATA 0x00000000 |
| 1237 | #define DDRSS_PHY_452_DATA 0x00000000 |
| 1238 | #define DDRSS_PHY_453_DATA 0x00000000 |
| 1239 | #define DDRSS_PHY_454_DATA 0x00000000 |
| 1240 | #define DDRSS_PHY_455_DATA 0x00000000 |
| 1241 | #define DDRSS_PHY_456_DATA 0x00000000 |
| 1242 | #define DDRSS_PHY_457_DATA 0x00000000 |
| 1243 | #define DDRSS_PHY_458_DATA 0x00000000 |
| 1244 | #define DDRSS_PHY_459_DATA 0x00000000 |
| 1245 | #define DDRSS_PHY_460_DATA 0x00000000 |
| 1246 | #define DDRSS_PHY_461_DATA 0x00000000 |
| 1247 | #define DDRSS_PHY_462_DATA 0x00000000 |
| 1248 | #define DDRSS_PHY_463_DATA 0x00000000 |
| 1249 | #define DDRSS_PHY_464_DATA 0x00000000 |
| 1250 | #define DDRSS_PHY_465_DATA 0x00000000 |
| 1251 | #define DDRSS_PHY_466_DATA 0x00000000 |
| 1252 | #define DDRSS_PHY_467_DATA 0x00000000 |
| 1253 | #define DDRSS_PHY_468_DATA 0x00000000 |
| 1254 | #define DDRSS_PHY_469_DATA 0x00000000 |
| 1255 | #define DDRSS_PHY_470_DATA 0x00000000 |
| 1256 | #define DDRSS_PHY_471_DATA 0x00000000 |
| 1257 | #define DDRSS_PHY_472_DATA 0x00000000 |
| 1258 | #define DDRSS_PHY_473_DATA 0x00000000 |
| 1259 | #define DDRSS_PHY_474_DATA 0x00000000 |
| 1260 | #define DDRSS_PHY_475_DATA 0x00000000 |
| 1261 | #define DDRSS_PHY_476_DATA 0x00000000 |
| 1262 | #define DDRSS_PHY_477_DATA 0x00000000 |
| 1263 | #define DDRSS_PHY_478_DATA 0x00000000 |
| 1264 | #define DDRSS_PHY_479_DATA 0x00000000 |
| 1265 | #define DDRSS_PHY_480_DATA 0x00000000 |
| 1266 | #define DDRSS_PHY_481_DATA 0x00000000 |
| 1267 | #define DDRSS_PHY_482_DATA 0x00000000 |
| 1268 | #define DDRSS_PHY_483_DATA 0x00000000 |
| 1269 | #define DDRSS_PHY_484_DATA 0x00000000 |
| 1270 | #define DDRSS_PHY_485_DATA 0x00000000 |
| 1271 | #define DDRSS_PHY_486_DATA 0x00000000 |
| 1272 | #define DDRSS_PHY_487_DATA 0x00000000 |
| 1273 | #define DDRSS_PHY_488_DATA 0x00000000 |
| 1274 | #define DDRSS_PHY_489_DATA 0x00000000 |
| 1275 | #define DDRSS_PHY_490_DATA 0x00000000 |
| 1276 | #define DDRSS_PHY_491_DATA 0x00000000 |
| 1277 | #define DDRSS_PHY_492_DATA 0x00000000 |
| 1278 | #define DDRSS_PHY_493_DATA 0x00000000 |
| 1279 | #define DDRSS_PHY_494_DATA 0x00000000 |
| 1280 | #define DDRSS_PHY_495_DATA 0x00000000 |
| 1281 | #define DDRSS_PHY_496_DATA 0x00000000 |
| 1282 | #define DDRSS_PHY_497_DATA 0x00000000 |
| 1283 | #define DDRSS_PHY_498_DATA 0x00000000 |
| 1284 | #define DDRSS_PHY_499_DATA 0x00000000 |
| 1285 | #define DDRSS_PHY_500_DATA 0x00000000 |
| 1286 | #define DDRSS_PHY_501_DATA 0x00000000 |
| 1287 | #define DDRSS_PHY_502_DATA 0x00000000 |
| 1288 | #define DDRSS_PHY_503_DATA 0x00000000 |
| 1289 | #define DDRSS_PHY_504_DATA 0x00000000 |
| 1290 | #define DDRSS_PHY_505_DATA 0x00000000 |
| 1291 | #define DDRSS_PHY_506_DATA 0x00000000 |
| 1292 | #define DDRSS_PHY_507_DATA 0x00000000 |
| 1293 | #define DDRSS_PHY_508_DATA 0x00000000 |
| 1294 | #define DDRSS_PHY_509_DATA 0x00000000 |
| 1295 | #define DDRSS_PHY_510_DATA 0x00000000 |
| 1296 | #define DDRSS_PHY_511_DATA 0x00000000 |
| 1297 | #define DDRSS_PHY_512_DATA 0x00000000 |
| 1298 | #define DDRSS_PHY_513_DATA 0x00000000 |
| 1299 | #define DDRSS_PHY_514_DATA 0x00000000 |
| 1300 | #define DDRSS_PHY_515_DATA 0x00000000 |
| 1301 | #define DDRSS_PHY_516_DATA 0x00000000 |
| 1302 | #define DDRSS_PHY_517_DATA 0x00000100 |
| 1303 | #define DDRSS_PHY_518_DATA 0x00000200 |
| 1304 | #define DDRSS_PHY_519_DATA 0x00000000 |
| 1305 | #define DDRSS_PHY_520_DATA 0x00000000 |
| 1306 | #define DDRSS_PHY_521_DATA 0x00000000 |
| 1307 | #define DDRSS_PHY_522_DATA 0x00000000 |
| 1308 | #define DDRSS_PHY_523_DATA 0x00400000 |
| 1309 | #define DDRSS_PHY_524_DATA 0x00000080 |
| 1310 | #define DDRSS_PHY_525_DATA 0x00DCBA98 |
| 1311 | #define DDRSS_PHY_526_DATA 0x03000000 |
| 1312 | #define DDRSS_PHY_527_DATA 0x00200000 |
| 1313 | #define DDRSS_PHY_528_DATA 0x00000000 |
| 1314 | #define DDRSS_PHY_529_DATA 0x00000000 |
| 1315 | #define DDRSS_PHY_530_DATA 0x00000000 |
| 1316 | #define DDRSS_PHY_531_DATA 0x00000000 |
| 1317 | #define DDRSS_PHY_532_DATA 0x0000002A |
| 1318 | #define DDRSS_PHY_533_DATA 0x00000015 |
| 1319 | #define DDRSS_PHY_534_DATA 0x00000015 |
| 1320 | #define DDRSS_PHY_535_DATA 0x0000002A |
| 1321 | #define DDRSS_PHY_536_DATA 0x00000033 |
| 1322 | #define DDRSS_PHY_537_DATA 0x0000000C |
| 1323 | #define DDRSS_PHY_538_DATA 0x0000000C |
| 1324 | #define DDRSS_PHY_539_DATA 0x00000033 |
| 1325 | #define DDRSS_PHY_540_DATA 0x0A418820 |
| 1326 | #define DDRSS_PHY_541_DATA 0x003F0000 |
| 1327 | #define DDRSS_PHY_542_DATA 0x000F013F |
| 1328 | #define DDRSS_PHY_543_DATA 0x0000000F |
| 1329 | #define DDRSS_PHY_544_DATA 0x000002CC |
| 1330 | #define DDRSS_PHY_545_DATA 0x00030000 |
| 1331 | #define DDRSS_PHY_546_DATA 0x00000300 |
| 1332 | #define DDRSS_PHY_547_DATA 0x00000300 |
| 1333 | #define DDRSS_PHY_548_DATA 0x00000300 |
| 1334 | #define DDRSS_PHY_549_DATA 0x00000300 |
| 1335 | #define DDRSS_PHY_550_DATA 0x00000300 |
| 1336 | #define DDRSS_PHY_551_DATA 0x42080010 |
| 1337 | #define DDRSS_PHY_552_DATA 0x0000803E |
| 1338 | #define DDRSS_PHY_553_DATA 0x00000003 |
| 1339 | #define DDRSS_PHY_554_DATA 0x00000002 |
| 1340 | #define DDRSS_PHY_555_DATA 0x00000000 |
| 1341 | #define DDRSS_PHY_556_DATA 0x00000000 |
| 1342 | #define DDRSS_PHY_557_DATA 0x00000000 |
| 1343 | #define DDRSS_PHY_558_DATA 0x00000000 |
| 1344 | #define DDRSS_PHY_559_DATA 0x00000000 |
| 1345 | #define DDRSS_PHY_560_DATA 0x00000000 |
| 1346 | #define DDRSS_PHY_561_DATA 0x00000000 |
| 1347 | #define DDRSS_PHY_562_DATA 0x00000000 |
| 1348 | #define DDRSS_PHY_563_DATA 0x00000000 |
| 1349 | #define DDRSS_PHY_564_DATA 0x00000000 |
| 1350 | #define DDRSS_PHY_565_DATA 0x00000000 |
| 1351 | #define DDRSS_PHY_566_DATA 0x00000000 |
| 1352 | #define DDRSS_PHY_567_DATA 0x00000000 |
| 1353 | #define DDRSS_PHY_568_DATA 0x00000000 |
| 1354 | #define DDRSS_PHY_569_DATA 0x00000000 |
| 1355 | #define DDRSS_PHY_570_DATA 0x00000000 |
| 1356 | #define DDRSS_PHY_571_DATA 0x00000000 |
| 1357 | #define DDRSS_PHY_572_DATA 0x00000000 |
| 1358 | #define DDRSS_PHY_573_DATA 0x00000000 |
| 1359 | #define DDRSS_PHY_574_DATA 0x00000000 |
| 1360 | #define DDRSS_PHY_575_DATA 0x00000000 |
| 1361 | #define DDRSS_PHY_576_DATA 0x00000000 |
| 1362 | #define DDRSS_PHY_577_DATA 0x00000000 |
| 1363 | #define DDRSS_PHY_578_DATA 0x00000000 |
| 1364 | #define DDRSS_PHY_579_DATA 0x00000000 |
| 1365 | #define DDRSS_PHY_580_DATA 0x00000000 |
| 1366 | #define DDRSS_PHY_581_DATA 0x00000000 |
| 1367 | #define DDRSS_PHY_582_DATA 0x00000000 |
| 1368 | #define DDRSS_PHY_583_DATA 0x00000000 |
| 1369 | #define DDRSS_PHY_584_DATA 0x00000000 |
| 1370 | #define DDRSS_PHY_585_DATA 0x00000000 |
| 1371 | #define DDRSS_PHY_586_DATA 0x00000000 |
| 1372 | #define DDRSS_PHY_587_DATA 0x00000000 |
| 1373 | #define DDRSS_PHY_588_DATA 0x00000000 |
| 1374 | #define DDRSS_PHY_589_DATA 0x00000000 |
| 1375 | #define DDRSS_PHY_590_DATA 0x00000000 |
| 1376 | #define DDRSS_PHY_591_DATA 0x00000000 |
| 1377 | #define DDRSS_PHY_592_DATA 0x00000000 |
| 1378 | #define DDRSS_PHY_593_DATA 0x00000000 |
| 1379 | #define DDRSS_PHY_594_DATA 0x00000000 |
| 1380 | #define DDRSS_PHY_595_DATA 0x00000000 |
| 1381 | #define DDRSS_PHY_596_DATA 0x00000000 |
| 1382 | #define DDRSS_PHY_597_DATA 0x00000000 |
| 1383 | #define DDRSS_PHY_598_DATA 0x00000000 |
| 1384 | #define DDRSS_PHY_599_DATA 0x00000000 |
| 1385 | #define DDRSS_PHY_600_DATA 0x00000000 |
| 1386 | #define DDRSS_PHY_601_DATA 0x00000000 |
| 1387 | #define DDRSS_PHY_602_DATA 0x00000000 |
| 1388 | #define DDRSS_PHY_603_DATA 0x00000000 |
| 1389 | #define DDRSS_PHY_604_DATA 0x00000000 |
| 1390 | #define DDRSS_PHY_605_DATA 0x00000000 |
| 1391 | #define DDRSS_PHY_606_DATA 0x00000000 |
| 1392 | #define DDRSS_PHY_607_DATA 0x00000000 |
| 1393 | #define DDRSS_PHY_608_DATA 0x00000000 |
| 1394 | #define DDRSS_PHY_609_DATA 0x00000000 |
| 1395 | #define DDRSS_PHY_610_DATA 0x00000000 |
| 1396 | #define DDRSS_PHY_611_DATA 0x00000000 |
| 1397 | #define DDRSS_PHY_612_DATA 0x00000000 |
| 1398 | #define DDRSS_PHY_613_DATA 0x00000000 |
| 1399 | #define DDRSS_PHY_614_DATA 0x00000000 |
| 1400 | #define DDRSS_PHY_615_DATA 0x00000000 |
| 1401 | #define DDRSS_PHY_616_DATA 0x00000000 |
| 1402 | #define DDRSS_PHY_617_DATA 0x00000000 |
| 1403 | #define DDRSS_PHY_618_DATA 0x00000000 |
| 1404 | #define DDRSS_PHY_619_DATA 0x00000000 |
| 1405 | #define DDRSS_PHY_620_DATA 0x00000000 |
| 1406 | #define DDRSS_PHY_621_DATA 0x00000000 |
| 1407 | #define DDRSS_PHY_622_DATA 0x00000000 |
| 1408 | #define DDRSS_PHY_623_DATA 0x00000000 |
| 1409 | #define DDRSS_PHY_624_DATA 0x00000000 |
| 1410 | #define DDRSS_PHY_625_DATA 0x00000000 |
| 1411 | #define DDRSS_PHY_626_DATA 0x00000000 |
| 1412 | #define DDRSS_PHY_627_DATA 0x00000000 |
| 1413 | #define DDRSS_PHY_628_DATA 0x00000000 |
| 1414 | #define DDRSS_PHY_629_DATA 0x00000000 |
| 1415 | #define DDRSS_PHY_630_DATA 0x00000000 |
| 1416 | #define DDRSS_PHY_631_DATA 0x00000000 |
| 1417 | #define DDRSS_PHY_632_DATA 0x00000000 |
| 1418 | #define DDRSS_PHY_633_DATA 0x00000000 |
| 1419 | #define DDRSS_PHY_634_DATA 0x00000000 |
| 1420 | #define DDRSS_PHY_635_DATA 0x00000000 |
| 1421 | #define DDRSS_PHY_636_DATA 0x00000000 |
| 1422 | #define DDRSS_PHY_637_DATA 0x00000000 |
| 1423 | #define DDRSS_PHY_638_DATA 0x00000000 |
| 1424 | #define DDRSS_PHY_639_DATA 0x00000000 |
| 1425 | #define DDRSS_PHY_640_DATA 0x00000000 |
| 1426 | #define DDRSS_PHY_641_DATA 0x00000000 |
| 1427 | #define DDRSS_PHY_642_DATA 0x00000000 |
| 1428 | #define DDRSS_PHY_643_DATA 0x00000000 |
| 1429 | #define DDRSS_PHY_644_DATA 0x00000000 |
| 1430 | #define DDRSS_PHY_645_DATA 0x00000000 |
| 1431 | #define DDRSS_PHY_646_DATA 0x00000000 |
| 1432 | #define DDRSS_PHY_647_DATA 0x00000000 |
| 1433 | #define DDRSS_PHY_648_DATA 0x00000000 |
| 1434 | #define DDRSS_PHY_649_DATA 0x00000000 |
| 1435 | #define DDRSS_PHY_650_DATA 0x00000000 |
| 1436 | #define DDRSS_PHY_651_DATA 0x00000000 |
| 1437 | #define DDRSS_PHY_652_DATA 0x00000000 |
| 1438 | #define DDRSS_PHY_653_DATA 0x00000000 |
| 1439 | #define DDRSS_PHY_654_DATA 0x00000000 |
| 1440 | #define DDRSS_PHY_655_DATA 0x00000000 |
| 1441 | #define DDRSS_PHY_656_DATA 0x00000000 |
| 1442 | #define DDRSS_PHY_657_DATA 0x00000000 |
| 1443 | #define DDRSS_PHY_658_DATA 0x00000000 |
| 1444 | #define DDRSS_PHY_659_DATA 0x00000000 |
| 1445 | #define DDRSS_PHY_660_DATA 0x00000000 |
| 1446 | #define DDRSS_PHY_661_DATA 0x00000000 |
| 1447 | #define DDRSS_PHY_662_DATA 0x00000000 |
| 1448 | #define DDRSS_PHY_663_DATA 0x00000000 |
| 1449 | #define DDRSS_PHY_664_DATA 0x00000000 |
| 1450 | #define DDRSS_PHY_665_DATA 0x00000000 |
| 1451 | #define DDRSS_PHY_666_DATA 0x00000000 |
| 1452 | #define DDRSS_PHY_667_DATA 0x00000000 |
| 1453 | #define DDRSS_PHY_668_DATA 0x00000000 |
| 1454 | #define DDRSS_PHY_669_DATA 0x00000000 |
| 1455 | #define DDRSS_PHY_670_DATA 0x00000000 |
| 1456 | #define DDRSS_PHY_671_DATA 0x00000000 |
| 1457 | #define DDRSS_PHY_672_DATA 0x00000000 |
| 1458 | #define DDRSS_PHY_673_DATA 0x00000000 |
| 1459 | #define DDRSS_PHY_674_DATA 0x00000000 |
| 1460 | #define DDRSS_PHY_675_DATA 0x00000000 |
| 1461 | #define DDRSS_PHY_676_DATA 0x00000000 |
| 1462 | #define DDRSS_PHY_677_DATA 0x00000000 |
| 1463 | #define DDRSS_PHY_678_DATA 0x00000000 |
| 1464 | #define DDRSS_PHY_679_DATA 0x00000000 |
| 1465 | #define DDRSS_PHY_680_DATA 0x00000000 |
| 1466 | #define DDRSS_PHY_681_DATA 0x00000000 |
| 1467 | #define DDRSS_PHY_682_DATA 0x00000000 |
| 1468 | #define DDRSS_PHY_683_DATA 0x00000000 |
| 1469 | #define DDRSS_PHY_684_DATA 0x00000000 |
| 1470 | #define DDRSS_PHY_685_DATA 0x00000000 |
| 1471 | #define DDRSS_PHY_686_DATA 0x00000000 |
| 1472 | #define DDRSS_PHY_687_DATA 0x00000000 |
| 1473 | #define DDRSS_PHY_688_DATA 0x00000000 |
| 1474 | #define DDRSS_PHY_689_DATA 0x00000000 |
| 1475 | #define DDRSS_PHY_690_DATA 0x00000000 |
| 1476 | #define DDRSS_PHY_691_DATA 0x00000000 |
| 1477 | #define DDRSS_PHY_692_DATA 0x00000000 |
| 1478 | #define DDRSS_PHY_693_DATA 0x00000000 |
| 1479 | #define DDRSS_PHY_694_DATA 0x00000000 |
| 1480 | #define DDRSS_PHY_695_DATA 0x00000000 |
| 1481 | #define DDRSS_PHY_696_DATA 0x00000000 |
| 1482 | #define DDRSS_PHY_697_DATA 0x00000000 |
| 1483 | #define DDRSS_PHY_698_DATA 0x00000000 |
| 1484 | #define DDRSS_PHY_699_DATA 0x00000000 |
| 1485 | #define DDRSS_PHY_700_DATA 0x00000000 |
| 1486 | #define DDRSS_PHY_701_DATA 0x00000000 |
| 1487 | #define DDRSS_PHY_702_DATA 0x00000000 |
| 1488 | #define DDRSS_PHY_703_DATA 0x00000000 |
| 1489 | #define DDRSS_PHY_704_DATA 0x00000000 |
| 1490 | #define DDRSS_PHY_705_DATA 0x00000000 |
| 1491 | #define DDRSS_PHY_706_DATA 0x00000000 |
| 1492 | #define DDRSS_PHY_707_DATA 0x00000000 |
| 1493 | #define DDRSS_PHY_708_DATA 0x00000000 |
| 1494 | #define DDRSS_PHY_709_DATA 0x00000000 |
| 1495 | #define DDRSS_PHY_710_DATA 0x00000000 |
| 1496 | #define DDRSS_PHY_711_DATA 0x00000000 |
| 1497 | #define DDRSS_PHY_712_DATA 0x00000000 |
| 1498 | #define DDRSS_PHY_713_DATA 0x00000000 |
| 1499 | #define DDRSS_PHY_714_DATA 0x00000000 |
| 1500 | #define DDRSS_PHY_715_DATA 0x00000000 |
| 1501 | #define DDRSS_PHY_716_DATA 0x00000000 |
| 1502 | #define DDRSS_PHY_717_DATA 0x00000000 |
| 1503 | #define DDRSS_PHY_718_DATA 0x00000000 |
| 1504 | #define DDRSS_PHY_719_DATA 0x00000000 |
| 1505 | #define DDRSS_PHY_720_DATA 0x00000000 |
| 1506 | #define DDRSS_PHY_721_DATA 0x00000000 |
| 1507 | #define DDRSS_PHY_722_DATA 0x00000000 |
| 1508 | #define DDRSS_PHY_723_DATA 0x00000000 |
| 1509 | #define DDRSS_PHY_724_DATA 0x00000000 |
| 1510 | #define DDRSS_PHY_725_DATA 0x00000000 |
| 1511 | #define DDRSS_PHY_726_DATA 0x00000000 |
| 1512 | #define DDRSS_PHY_727_DATA 0x00000000 |
| 1513 | #define DDRSS_PHY_728_DATA 0x00000000 |
| 1514 | #define DDRSS_PHY_729_DATA 0x00000000 |
| 1515 | #define DDRSS_PHY_730_DATA 0x00000000 |
| 1516 | #define DDRSS_PHY_731_DATA 0x00000000 |
| 1517 | #define DDRSS_PHY_732_DATA 0x00000000 |
| 1518 | #define DDRSS_PHY_733_DATA 0x00000000 |
| 1519 | #define DDRSS_PHY_734_DATA 0x00000000 |
| 1520 | #define DDRSS_PHY_735_DATA 0x00000000 |
| 1521 | #define DDRSS_PHY_736_DATA 0x00000000 |
| 1522 | #define DDRSS_PHY_737_DATA 0x00000000 |
| 1523 | #define DDRSS_PHY_738_DATA 0x00000000 |
| 1524 | #define DDRSS_PHY_739_DATA 0x00000000 |
| 1525 | #define DDRSS_PHY_740_DATA 0x00000000 |
| 1526 | #define DDRSS_PHY_741_DATA 0x00000000 |
| 1527 | #define DDRSS_PHY_742_DATA 0x00000000 |
| 1528 | #define DDRSS_PHY_743_DATA 0x00000000 |
| 1529 | #define DDRSS_PHY_744_DATA 0x00000000 |
| 1530 | #define DDRSS_PHY_745_DATA 0x00000000 |
| 1531 | #define DDRSS_PHY_746_DATA 0x00000000 |
| 1532 | #define DDRSS_PHY_747_DATA 0x00000000 |
| 1533 | #define DDRSS_PHY_748_DATA 0x00000000 |
| 1534 | #define DDRSS_PHY_749_DATA 0x00000000 |
| 1535 | #define DDRSS_PHY_750_DATA 0x00000000 |
| 1536 | #define DDRSS_PHY_751_DATA 0x00000000 |
| 1537 | #define DDRSS_PHY_752_DATA 0x00000000 |
| 1538 | #define DDRSS_PHY_753_DATA 0x00000000 |
| 1539 | #define DDRSS_PHY_754_DATA 0x00000000 |
| 1540 | #define DDRSS_PHY_755_DATA 0x00000000 |
| 1541 | #define DDRSS_PHY_756_DATA 0x00000000 |
| 1542 | #define DDRSS_PHY_757_DATA 0x00000000 |
| 1543 | #define DDRSS_PHY_758_DATA 0x00000000 |
| 1544 | #define DDRSS_PHY_759_DATA 0x00000000 |
| 1545 | #define DDRSS_PHY_760_DATA 0x00000000 |
| 1546 | #define DDRSS_PHY_761_DATA 0x00000000 |
| 1547 | #define DDRSS_PHY_762_DATA 0x00000000 |
| 1548 | #define DDRSS_PHY_763_DATA 0x00000000 |
| 1549 | #define DDRSS_PHY_764_DATA 0x00000000 |
| 1550 | #define DDRSS_PHY_765_DATA 0x00000000 |
| 1551 | #define DDRSS_PHY_766_DATA 0x00000000 |
| 1552 | #define DDRSS_PHY_767_DATA 0x00000000 |
| 1553 | #define DDRSS_PHY_768_DATA 0x00000000 |
| 1554 | #define DDRSS_PHY_769_DATA 0x00000000 |
| 1555 | #define DDRSS_PHY_770_DATA 0x00000000 |
| 1556 | #define DDRSS_PHY_771_DATA 0x00000000 |
| 1557 | #define DDRSS_PHY_772_DATA 0x00000000 |
| 1558 | #define DDRSS_PHY_773_DATA 0x00000100 |
| 1559 | #define DDRSS_PHY_774_DATA 0x00000200 |
| 1560 | #define DDRSS_PHY_775_DATA 0x00000000 |
| 1561 | #define DDRSS_PHY_776_DATA 0x00000000 |
| 1562 | #define DDRSS_PHY_777_DATA 0x00000000 |
| 1563 | #define DDRSS_PHY_778_DATA 0x00000000 |
| 1564 | #define DDRSS_PHY_779_DATA 0x00400000 |
| 1565 | #define DDRSS_PHY_780_DATA 0x00000080 |
| 1566 | #define DDRSS_PHY_781_DATA 0x00DCBA98 |
| 1567 | #define DDRSS_PHY_782_DATA 0x03000000 |
| 1568 | #define DDRSS_PHY_783_DATA 0x00200000 |
| 1569 | #define DDRSS_PHY_784_DATA 0x00000000 |
| 1570 | #define DDRSS_PHY_785_DATA 0x00000000 |
| 1571 | #define DDRSS_PHY_786_DATA 0x00000000 |
| 1572 | #define DDRSS_PHY_787_DATA 0x00000000 |
| 1573 | #define DDRSS_PHY_788_DATA 0x0000002A |
| 1574 | #define DDRSS_PHY_789_DATA 0x00000015 |
| 1575 | #define DDRSS_PHY_790_DATA 0x00000015 |
| 1576 | #define DDRSS_PHY_791_DATA 0x0000002A |
| 1577 | #define DDRSS_PHY_792_DATA 0x00000033 |
| 1578 | #define DDRSS_PHY_793_DATA 0x0000000C |
| 1579 | #define DDRSS_PHY_794_DATA 0x0000000C |
| 1580 | #define DDRSS_PHY_795_DATA 0x00000033 |
| 1581 | #define DDRSS_PHY_796_DATA 0x00000000 |
| 1582 | #define DDRSS_PHY_797_DATA 0x00000000 |
| 1583 | #define DDRSS_PHY_798_DATA 0x000F0000 |
| 1584 | #define DDRSS_PHY_799_DATA 0x0000000F |
| 1585 | #define DDRSS_PHY_800_DATA 0x000002CC |
| 1586 | #define DDRSS_PHY_801_DATA 0x00030000 |
| 1587 | #define DDRSS_PHY_802_DATA 0x00000300 |
| 1588 | #define DDRSS_PHY_803_DATA 0x00000300 |
| 1589 | #define DDRSS_PHY_804_DATA 0x00000300 |
| 1590 | #define DDRSS_PHY_805_DATA 0x00000300 |
| 1591 | #define DDRSS_PHY_806_DATA 0x00000300 |
| 1592 | #define DDRSS_PHY_807_DATA 0x42080010 |
| 1593 | #define DDRSS_PHY_808_DATA 0x0000803E |
| 1594 | #define DDRSS_PHY_809_DATA 0x00000003 |
| 1595 | #define DDRSS_PHY_810_DATA 0x00000002 |
| 1596 | #define DDRSS_PHY_811_DATA 0x00000000 |
| 1597 | #define DDRSS_PHY_812_DATA 0x00000000 |
| 1598 | #define DDRSS_PHY_813_DATA 0x00000000 |
| 1599 | #define DDRSS_PHY_814_DATA 0x00000000 |
| 1600 | #define DDRSS_PHY_815_DATA 0x00000000 |
| 1601 | #define DDRSS_PHY_816_DATA 0x00000000 |
| 1602 | #define DDRSS_PHY_817_DATA 0x00000000 |
| 1603 | #define DDRSS_PHY_818_DATA 0x00000000 |
| 1604 | #define DDRSS_PHY_819_DATA 0x00000000 |
| 1605 | #define DDRSS_PHY_820_DATA 0x00000000 |
| 1606 | #define DDRSS_PHY_821_DATA 0x00000000 |
| 1607 | #define DDRSS_PHY_822_DATA 0x00000000 |
| 1608 | #define DDRSS_PHY_823_DATA 0x00000000 |
| 1609 | #define DDRSS_PHY_824_DATA 0x00000000 |
| 1610 | #define DDRSS_PHY_825_DATA 0x00000000 |
| 1611 | #define DDRSS_PHY_826_DATA 0x00000000 |
| 1612 | #define DDRSS_PHY_827_DATA 0x00000000 |
| 1613 | #define DDRSS_PHY_828_DATA 0x00000000 |
| 1614 | #define DDRSS_PHY_829_DATA 0x00000000 |
| 1615 | #define DDRSS_PHY_830_DATA 0x00000000 |
| 1616 | #define DDRSS_PHY_831_DATA 0x00000000 |
| 1617 | #define DDRSS_PHY_832_DATA 0x00000000 |
| 1618 | #define DDRSS_PHY_833_DATA 0x00000000 |
| 1619 | #define DDRSS_PHY_834_DATA 0x00000000 |
| 1620 | #define DDRSS_PHY_835_DATA 0x00000000 |
| 1621 | #define DDRSS_PHY_836_DATA 0x00000000 |
| 1622 | #define DDRSS_PHY_837_DATA 0x00000000 |
| 1623 | #define DDRSS_PHY_838_DATA 0x00000000 |
| 1624 | #define DDRSS_PHY_839_DATA 0x00000000 |
| 1625 | #define DDRSS_PHY_840_DATA 0x00000000 |
| 1626 | #define DDRSS_PHY_841_DATA 0x00000000 |
| 1627 | #define DDRSS_PHY_842_DATA 0x00000000 |
| 1628 | #define DDRSS_PHY_843_DATA 0x00000000 |
| 1629 | #define DDRSS_PHY_844_DATA 0x00000000 |
| 1630 | #define DDRSS_PHY_845_DATA 0x00000000 |
| 1631 | #define DDRSS_PHY_846_DATA 0x00000000 |
| 1632 | #define DDRSS_PHY_847_DATA 0x00000000 |
| 1633 | #define DDRSS_PHY_848_DATA 0x00000000 |
| 1634 | #define DDRSS_PHY_849_DATA 0x00000000 |
| 1635 | #define DDRSS_PHY_850_DATA 0x00000000 |
| 1636 | #define DDRSS_PHY_851_DATA 0x00000000 |
| 1637 | #define DDRSS_PHY_852_DATA 0x00000000 |
| 1638 | #define DDRSS_PHY_853_DATA 0x00000000 |
| 1639 | #define DDRSS_PHY_854_DATA 0x00000000 |
| 1640 | #define DDRSS_PHY_855_DATA 0x00000000 |
| 1641 | #define DDRSS_PHY_856_DATA 0x00000000 |
| 1642 | #define DDRSS_PHY_857_DATA 0x00000000 |
| 1643 | #define DDRSS_PHY_858_DATA 0x00000000 |
| 1644 | #define DDRSS_PHY_859_DATA 0x00000000 |
| 1645 | #define DDRSS_PHY_860_DATA 0x00000000 |
| 1646 | #define DDRSS_PHY_861_DATA 0x00000000 |
| 1647 | #define DDRSS_PHY_862_DATA 0x00000000 |
| 1648 | #define DDRSS_PHY_863_DATA 0x00000000 |
| 1649 | #define DDRSS_PHY_864_DATA 0x00000000 |
| 1650 | #define DDRSS_PHY_865_DATA 0x00000000 |
| 1651 | #define DDRSS_PHY_866_DATA 0x00000000 |
| 1652 | #define DDRSS_PHY_867_DATA 0x00000000 |
| 1653 | #define DDRSS_PHY_868_DATA 0x00000000 |
| 1654 | #define DDRSS_PHY_869_DATA 0x00000000 |
| 1655 | #define DDRSS_PHY_870_DATA 0x00000000 |
| 1656 | #define DDRSS_PHY_871_DATA 0x00000000 |
| 1657 | #define DDRSS_PHY_872_DATA 0x00000000 |
| 1658 | #define DDRSS_PHY_873_DATA 0x00000000 |
| 1659 | #define DDRSS_PHY_874_DATA 0x00000000 |
| 1660 | #define DDRSS_PHY_875_DATA 0x00000000 |
| 1661 | #define DDRSS_PHY_876_DATA 0x00000000 |
| 1662 | #define DDRSS_PHY_877_DATA 0x00000000 |
| 1663 | #define DDRSS_PHY_878_DATA 0x00000000 |
| 1664 | #define DDRSS_PHY_879_DATA 0x00000000 |
| 1665 | #define DDRSS_PHY_880_DATA 0x00000000 |
| 1666 | #define DDRSS_PHY_881_DATA 0x00000000 |
| 1667 | #define DDRSS_PHY_882_DATA 0x00000000 |
| 1668 | #define DDRSS_PHY_883_DATA 0x00000000 |
| 1669 | #define DDRSS_PHY_884_DATA 0x00000000 |
| 1670 | #define DDRSS_PHY_885_DATA 0x00000000 |
| 1671 | #define DDRSS_PHY_886_DATA 0x00000000 |
| 1672 | #define DDRSS_PHY_887_DATA 0x00000000 |
| 1673 | #define DDRSS_PHY_888_DATA 0x00000000 |
| 1674 | #define DDRSS_PHY_889_DATA 0x00000000 |
| 1675 | #define DDRSS_PHY_890_DATA 0x00000000 |
| 1676 | #define DDRSS_PHY_891_DATA 0x00000000 |
| 1677 | #define DDRSS_PHY_892_DATA 0x00000000 |
| 1678 | #define DDRSS_PHY_893_DATA 0x00000000 |
| 1679 | #define DDRSS_PHY_894_DATA 0x00000000 |
| 1680 | #define DDRSS_PHY_895_DATA 0x00000000 |
| 1681 | #define DDRSS_PHY_896_DATA 0x00000000 |
| 1682 | #define DDRSS_PHY_897_DATA 0x00000000 |
| 1683 | #define DDRSS_PHY_898_DATA 0x00000000 |
| 1684 | #define DDRSS_PHY_899_DATA 0x00000000 |
| 1685 | #define DDRSS_PHY_900_DATA 0x00000000 |
| 1686 | #define DDRSS_PHY_901_DATA 0x00000000 |
| 1687 | #define DDRSS_PHY_902_DATA 0x00000000 |
| 1688 | #define DDRSS_PHY_903_DATA 0x00000000 |
| 1689 | #define DDRSS_PHY_904_DATA 0x00000000 |
| 1690 | #define DDRSS_PHY_905_DATA 0x00000000 |
| 1691 | #define DDRSS_PHY_906_DATA 0x00000000 |
| 1692 | #define DDRSS_PHY_907_DATA 0x00000000 |
| 1693 | #define DDRSS_PHY_908_DATA 0x00000000 |
| 1694 | #define DDRSS_PHY_909_DATA 0x00000000 |
| 1695 | #define DDRSS_PHY_910_DATA 0x00000000 |
| 1696 | #define DDRSS_PHY_911_DATA 0x00000000 |
| 1697 | #define DDRSS_PHY_912_DATA 0x00000000 |
| 1698 | #define DDRSS_PHY_913_DATA 0x00000000 |
| 1699 | #define DDRSS_PHY_914_DATA 0x00000000 |
| 1700 | #define DDRSS_PHY_915_DATA 0x00000000 |
| 1701 | #define DDRSS_PHY_916_DATA 0x00000000 |
| 1702 | #define DDRSS_PHY_917_DATA 0x00000000 |
| 1703 | #define DDRSS_PHY_918_DATA 0x00000000 |
| 1704 | #define DDRSS_PHY_919_DATA 0x00000000 |
| 1705 | #define DDRSS_PHY_920_DATA 0x00000000 |
| 1706 | #define DDRSS_PHY_921_DATA 0x00000000 |
| 1707 | #define DDRSS_PHY_922_DATA 0x00000000 |
| 1708 | #define DDRSS_PHY_923_DATA 0x00000000 |
| 1709 | #define DDRSS_PHY_924_DATA 0x00000000 |
| 1710 | #define DDRSS_PHY_925_DATA 0x00000000 |
| 1711 | #define DDRSS_PHY_926_DATA 0x00000000 |
| 1712 | #define DDRSS_PHY_927_DATA 0x00000000 |
| 1713 | #define DDRSS_PHY_928_DATA 0x00000000 |
| 1714 | #define DDRSS_PHY_929_DATA 0x00000000 |
| 1715 | #define DDRSS_PHY_930_DATA 0x00000000 |
| 1716 | #define DDRSS_PHY_931_DATA 0x00000000 |
| 1717 | #define DDRSS_PHY_932_DATA 0x00000000 |
| 1718 | #define DDRSS_PHY_933_DATA 0x00000000 |
| 1719 | #define DDRSS_PHY_934_DATA 0x00000000 |
| 1720 | #define DDRSS_PHY_935_DATA 0x00000000 |
| 1721 | #define DDRSS_PHY_936_DATA 0x00000000 |
| 1722 | #define DDRSS_PHY_937_DATA 0x00000000 |
| 1723 | #define DDRSS_PHY_938_DATA 0x00000000 |
| 1724 | #define DDRSS_PHY_939_DATA 0x00000000 |
| 1725 | #define DDRSS_PHY_940_DATA 0x00000000 |
| 1726 | #define DDRSS_PHY_941_DATA 0x00000000 |
| 1727 | #define DDRSS_PHY_942_DATA 0x00000000 |
| 1728 | #define DDRSS_PHY_943_DATA 0x00000000 |
| 1729 | #define DDRSS_PHY_944_DATA 0x00000000 |
| 1730 | #define DDRSS_PHY_945_DATA 0x00000000 |
| 1731 | #define DDRSS_PHY_946_DATA 0x00000000 |
| 1732 | #define DDRSS_PHY_947_DATA 0x00000000 |
| 1733 | #define DDRSS_PHY_948_DATA 0x00000000 |
| 1734 | #define DDRSS_PHY_949_DATA 0x00000000 |
| 1735 | #define DDRSS_PHY_950_DATA 0x00000000 |
| 1736 | #define DDRSS_PHY_951_DATA 0x00000000 |
| 1737 | #define DDRSS_PHY_952_DATA 0x00000000 |
| 1738 | #define DDRSS_PHY_953_DATA 0x00000000 |
| 1739 | #define DDRSS_PHY_954_DATA 0x00000000 |
| 1740 | #define DDRSS_PHY_955_DATA 0x00000000 |
| 1741 | #define DDRSS_PHY_956_DATA 0x00000000 |
| 1742 | #define DDRSS_PHY_957_DATA 0x00000000 |
| 1743 | #define DDRSS_PHY_958_DATA 0x00000000 |
| 1744 | #define DDRSS_PHY_959_DATA 0x00000000 |
| 1745 | #define DDRSS_PHY_960_DATA 0x00000000 |
| 1746 | #define DDRSS_PHY_961_DATA 0x00000000 |
| 1747 | #define DDRSS_PHY_962_DATA 0x00000000 |
| 1748 | #define DDRSS_PHY_963_DATA 0x00000000 |
| 1749 | #define DDRSS_PHY_964_DATA 0x00000000 |
| 1750 | #define DDRSS_PHY_965_DATA 0x00000000 |
| 1751 | #define DDRSS_PHY_966_DATA 0x00000000 |
| 1752 | #define DDRSS_PHY_967_DATA 0x00000000 |
| 1753 | #define DDRSS_PHY_968_DATA 0x00000000 |
| 1754 | #define DDRSS_PHY_969_DATA 0x00000000 |
| 1755 | #define DDRSS_PHY_970_DATA 0x00000000 |
| 1756 | #define DDRSS_PHY_971_DATA 0x00000000 |
| 1757 | #define DDRSS_PHY_972_DATA 0x00000000 |
| 1758 | #define DDRSS_PHY_973_DATA 0x00000000 |
| 1759 | #define DDRSS_PHY_974_DATA 0x00000000 |
| 1760 | #define DDRSS_PHY_975_DATA 0x00000000 |
| 1761 | #define DDRSS_PHY_976_DATA 0x00000000 |
| 1762 | #define DDRSS_PHY_977_DATA 0x00000000 |
| 1763 | #define DDRSS_PHY_978_DATA 0x00000000 |
| 1764 | #define DDRSS_PHY_979_DATA 0x00000000 |
| 1765 | #define DDRSS_PHY_980_DATA 0x00000000 |
| 1766 | #define DDRSS_PHY_981_DATA 0x00000000 |
| 1767 | #define DDRSS_PHY_982_DATA 0x00000000 |
| 1768 | #define DDRSS_PHY_983_DATA 0x00000000 |
| 1769 | #define DDRSS_PHY_984_DATA 0x00000000 |
| 1770 | #define DDRSS_PHY_985_DATA 0x00000000 |
| 1771 | #define DDRSS_PHY_986_DATA 0x00000000 |
| 1772 | #define DDRSS_PHY_987_DATA 0x00000000 |
| 1773 | #define DDRSS_PHY_988_DATA 0x00000000 |
| 1774 | #define DDRSS_PHY_989_DATA 0x00000000 |
| 1775 | #define DDRSS_PHY_990_DATA 0x00000000 |
| 1776 | #define DDRSS_PHY_991_DATA 0x00000000 |
| 1777 | #define DDRSS_PHY_992_DATA 0x00000000 |
| 1778 | #define DDRSS_PHY_993_DATA 0x00000000 |
| 1779 | #define DDRSS_PHY_994_DATA 0x00000000 |
| 1780 | #define DDRSS_PHY_995_DATA 0x00000000 |
| 1781 | #define DDRSS_PHY_996_DATA 0x00000000 |
| 1782 | #define DDRSS_PHY_997_DATA 0x00000000 |
| 1783 | #define DDRSS_PHY_998_DATA 0x00000000 |
| 1784 | #define DDRSS_PHY_999_DATA 0x00000000 |
| 1785 | #define DDRSS_PHY_1000_DATA 0x00000000 |
| 1786 | #define DDRSS_PHY_1001_DATA 0x00000000 |
| 1787 | #define DDRSS_PHY_1002_DATA 0x00000000 |
| 1788 | #define DDRSS_PHY_1003_DATA 0x00000000 |
| 1789 | #define DDRSS_PHY_1004_DATA 0x00000000 |
| 1790 | #define DDRSS_PHY_1005_DATA 0x00000000 |
| 1791 | #define DDRSS_PHY_1006_DATA 0x00000000 |
| 1792 | #define DDRSS_PHY_1007_DATA 0x00000000 |
| 1793 | #define DDRSS_PHY_1008_DATA 0x00000000 |
| 1794 | #define DDRSS_PHY_1009_DATA 0x00000000 |
| 1795 | #define DDRSS_PHY_1010_DATA 0x00000000 |
| 1796 | #define DDRSS_PHY_1011_DATA 0x00000000 |
| 1797 | #define DDRSS_PHY_1012_DATA 0x00000000 |
| 1798 | #define DDRSS_PHY_1013_DATA 0x00000000 |
| 1799 | #define DDRSS_PHY_1014_DATA 0x00000000 |
| 1800 | #define DDRSS_PHY_1015_DATA 0x00000000 |
| 1801 | #define DDRSS_PHY_1016_DATA 0x00000000 |
| 1802 | #define DDRSS_PHY_1017_DATA 0x00000000 |
| 1803 | #define DDRSS_PHY_1018_DATA 0x00000000 |
| 1804 | #define DDRSS_PHY_1019_DATA 0x00000000 |
| 1805 | #define DDRSS_PHY_1020_DATA 0x00000000 |
| 1806 | #define DDRSS_PHY_1021_DATA 0x00000000 |
| 1807 | #define DDRSS_PHY_1022_DATA 0x00000000 |
| 1808 | #define DDRSS_PHY_1023_DATA 0x00000000 |
| 1809 | #define DDRSS_PHY_1024_DATA 0x00000000 |
| 1810 | #define DDRSS_PHY_1025_DATA 0x00000000 |
| 1811 | #define DDRSS_PHY_1026_DATA 0x00000000 |
| 1812 | #define DDRSS_PHY_1027_DATA 0x00000000 |
| 1813 | #define DDRSS_PHY_1028_DATA 0x00000000 |
| 1814 | #define DDRSS_PHY_1029_DATA 0x00000100 |
| 1815 | #define DDRSS_PHY_1030_DATA 0x00000200 |
| 1816 | #define DDRSS_PHY_1031_DATA 0x00000000 |
| 1817 | #define DDRSS_PHY_1032_DATA 0x00000000 |
| 1818 | #define DDRSS_PHY_1033_DATA 0x00000000 |
| 1819 | #define DDRSS_PHY_1034_DATA 0x00000000 |
| 1820 | #define DDRSS_PHY_1035_DATA 0x00400000 |
| 1821 | #define DDRSS_PHY_1036_DATA 0x00000080 |
| 1822 | #define DDRSS_PHY_1037_DATA 0x00DCBA98 |
| 1823 | #define DDRSS_PHY_1038_DATA 0x03000000 |
| 1824 | #define DDRSS_PHY_1039_DATA 0x00200000 |
| 1825 | #define DDRSS_PHY_1040_DATA 0x00000000 |
| 1826 | #define DDRSS_PHY_1041_DATA 0x00000000 |
| 1827 | #define DDRSS_PHY_1042_DATA 0x00000000 |
| 1828 | #define DDRSS_PHY_1043_DATA 0x00000000 |
| 1829 | #define DDRSS_PHY_1044_DATA 0x0000002A |
| 1830 | #define DDRSS_PHY_1045_DATA 0x00000015 |
| 1831 | #define DDRSS_PHY_1046_DATA 0x00000015 |
| 1832 | #define DDRSS_PHY_1047_DATA 0x0000002A |
| 1833 | #define DDRSS_PHY_1048_DATA 0x00000033 |
| 1834 | #define DDRSS_PHY_1049_DATA 0x0000000C |
| 1835 | #define DDRSS_PHY_1050_DATA 0x0000000C |
| 1836 | #define DDRSS_PHY_1051_DATA 0x00000033 |
| 1837 | #define DDRSS_PHY_1052_DATA 0x2307B9AC |
| 1838 | #define DDRSS_PHY_1053_DATA 0x10000000 |
| 1839 | #define DDRSS_PHY_1054_DATA 0x000F0000 |
| 1840 | #define DDRSS_PHY_1055_DATA 0x0000000F |
| 1841 | #define DDRSS_PHY_1056_DATA 0x000002CC |
| 1842 | #define DDRSS_PHY_1057_DATA 0x00030000 |
| 1843 | #define DDRSS_PHY_1058_DATA 0x00000300 |
| 1844 | #define DDRSS_PHY_1059_DATA 0x00000300 |
| 1845 | #define DDRSS_PHY_1060_DATA 0x00000300 |
| 1846 | #define DDRSS_PHY_1061_DATA 0x00000300 |
| 1847 | #define DDRSS_PHY_1062_DATA 0x00000300 |
| 1848 | #define DDRSS_PHY_1063_DATA 0x42080010 |
| 1849 | #define DDRSS_PHY_1064_DATA 0x0000803E |
| 1850 | #define DDRSS_PHY_1065_DATA 0x00000003 |
| 1851 | #define DDRSS_PHY_1066_DATA 0x00000002 |
| 1852 | #define DDRSS_PHY_1067_DATA 0x00000000 |
| 1853 | #define DDRSS_PHY_1068_DATA 0x00000000 |
| 1854 | #define DDRSS_PHY_1069_DATA 0x00000000 |
| 1855 | #define DDRSS_PHY_1070_DATA 0x00000000 |
| 1856 | #define DDRSS_PHY_1071_DATA 0x00000000 |
| 1857 | #define DDRSS_PHY_1072_DATA 0x00000000 |
| 1858 | #define DDRSS_PHY_1073_DATA 0x00000000 |
| 1859 | #define DDRSS_PHY_1074_DATA 0x00000000 |
| 1860 | #define DDRSS_PHY_1075_DATA 0x00000000 |
| 1861 | #define DDRSS_PHY_1076_DATA 0x00000000 |
| 1862 | #define DDRSS_PHY_1077_DATA 0x00000000 |
| 1863 | #define DDRSS_PHY_1078_DATA 0x00000000 |
| 1864 | #define DDRSS_PHY_1079_DATA 0x00000000 |
| 1865 | #define DDRSS_PHY_1080_DATA 0x00000000 |
| 1866 | #define DDRSS_PHY_1081_DATA 0x00000000 |
| 1867 | #define DDRSS_PHY_1082_DATA 0x00000000 |
| 1868 | #define DDRSS_PHY_1083_DATA 0x00000000 |
| 1869 | #define DDRSS_PHY_1084_DATA 0x00000000 |
| 1870 | #define DDRSS_PHY_1085_DATA 0x00000000 |
| 1871 | #define DDRSS_PHY_1086_DATA 0x00000000 |
| 1872 | #define DDRSS_PHY_1087_DATA 0x00000000 |
| 1873 | #define DDRSS_PHY_1088_DATA 0x00000000 |
| 1874 | #define DDRSS_PHY_1089_DATA 0x00000000 |
| 1875 | #define DDRSS_PHY_1090_DATA 0x00000000 |
| 1876 | #define DDRSS_PHY_1091_DATA 0x00000000 |
| 1877 | #define DDRSS_PHY_1092_DATA 0x00000000 |
| 1878 | #define DDRSS_PHY_1093_DATA 0x00000000 |
| 1879 | #define DDRSS_PHY_1094_DATA 0x00000000 |
| 1880 | #define DDRSS_PHY_1095_DATA 0x00000000 |
| 1881 | #define DDRSS_PHY_1096_DATA 0x00000000 |
| 1882 | #define DDRSS_PHY_1097_DATA 0x00000000 |
| 1883 | #define DDRSS_PHY_1098_DATA 0x00000000 |
| 1884 | #define DDRSS_PHY_1099_DATA 0x00000000 |
| 1885 | #define DDRSS_PHY_1100_DATA 0x00000000 |
| 1886 | #define DDRSS_PHY_1101_DATA 0x00000000 |
| 1887 | #define DDRSS_PHY_1102_DATA 0x00000000 |
| 1888 | #define DDRSS_PHY_1103_DATA 0x00000000 |
| 1889 | #define DDRSS_PHY_1104_DATA 0x00000000 |
| 1890 | #define DDRSS_PHY_1105_DATA 0x00000000 |
| 1891 | #define DDRSS_PHY_1106_DATA 0x00000000 |
| 1892 | #define DDRSS_PHY_1107_DATA 0x00000000 |
| 1893 | #define DDRSS_PHY_1108_DATA 0x00000000 |
| 1894 | #define DDRSS_PHY_1109_DATA 0x00000000 |
| 1895 | #define DDRSS_PHY_1110_DATA 0x00000000 |
| 1896 | #define DDRSS_PHY_1111_DATA 0x00000000 |
| 1897 | #define DDRSS_PHY_1112_DATA 0x00000000 |
| 1898 | #define DDRSS_PHY_1113_DATA 0x00000000 |
| 1899 | #define DDRSS_PHY_1114_DATA 0x00000000 |
| 1900 | #define DDRSS_PHY_1115_DATA 0x00000000 |
| 1901 | #define DDRSS_PHY_1116_DATA 0x00000000 |
| 1902 | #define DDRSS_PHY_1117_DATA 0x00000000 |
| 1903 | #define DDRSS_PHY_1118_DATA 0x00000000 |
| 1904 | #define DDRSS_PHY_1119_DATA 0x00000000 |
| 1905 | #define DDRSS_PHY_1120_DATA 0x00000000 |
| 1906 | #define DDRSS_PHY_1121_DATA 0x00000000 |
| 1907 | #define DDRSS_PHY_1122_DATA 0x00000000 |
| 1908 | #define DDRSS_PHY_1123_DATA 0x00000000 |
| 1909 | #define DDRSS_PHY_1124_DATA 0x00000000 |
| 1910 | #define DDRSS_PHY_1125_DATA 0x00000000 |
| 1911 | #define DDRSS_PHY_1126_DATA 0x00000000 |
| 1912 | #define DDRSS_PHY_1127_DATA 0x00000000 |
| 1913 | #define DDRSS_PHY_1128_DATA 0x00000000 |
| 1914 | #define DDRSS_PHY_1129_DATA 0x00000000 |
| 1915 | #define DDRSS_PHY_1130_DATA 0x00000000 |
| 1916 | #define DDRSS_PHY_1131_DATA 0x00000000 |
| 1917 | #define DDRSS_PHY_1132_DATA 0x00000000 |
| 1918 | #define DDRSS_PHY_1133_DATA 0x00000000 |
| 1919 | #define DDRSS_PHY_1134_DATA 0x00000000 |
| 1920 | #define DDRSS_PHY_1135_DATA 0x00000000 |
| 1921 | #define DDRSS_PHY_1136_DATA 0x00000000 |
| 1922 | #define DDRSS_PHY_1137_DATA 0x00000000 |
| 1923 | #define DDRSS_PHY_1138_DATA 0x00000000 |
| 1924 | #define DDRSS_PHY_1139_DATA 0x00000000 |
| 1925 | #define DDRSS_PHY_1140_DATA 0x00000000 |
| 1926 | #define DDRSS_PHY_1141_DATA 0x00000000 |
| 1927 | #define DDRSS_PHY_1142_DATA 0x00000000 |
| 1928 | #define DDRSS_PHY_1143_DATA 0x00000000 |
| 1929 | #define DDRSS_PHY_1144_DATA 0x00000000 |
| 1930 | #define DDRSS_PHY_1145_DATA 0x00000000 |
| 1931 | #define DDRSS_PHY_1146_DATA 0x00000000 |
| 1932 | #define DDRSS_PHY_1147_DATA 0x00000000 |
| 1933 | #define DDRSS_PHY_1148_DATA 0x00000000 |
| 1934 | #define DDRSS_PHY_1149_DATA 0x00000000 |
| 1935 | #define DDRSS_PHY_1150_DATA 0x00000000 |
| 1936 | #define DDRSS_PHY_1151_DATA 0x00000000 |
| 1937 | #define DDRSS_PHY_1152_DATA 0x00000000 |
| 1938 | #define DDRSS_PHY_1153_DATA 0x00000000 |
| 1939 | #define DDRSS_PHY_1154_DATA 0x00000000 |
| 1940 | #define DDRSS_PHY_1155_DATA 0x00000000 |
| 1941 | #define DDRSS_PHY_1156_DATA 0x00000000 |
| 1942 | #define DDRSS_PHY_1157_DATA 0x00000000 |
| 1943 | #define DDRSS_PHY_1158_DATA 0x00000000 |
| 1944 | #define DDRSS_PHY_1159_DATA 0x00000000 |
| 1945 | #define DDRSS_PHY_1160_DATA 0x00000000 |
| 1946 | #define DDRSS_PHY_1161_DATA 0x00000000 |
| 1947 | #define DDRSS_PHY_1162_DATA 0x00000000 |
| 1948 | #define DDRSS_PHY_1163_DATA 0x00000000 |
| 1949 | #define DDRSS_PHY_1164_DATA 0x00000000 |
| 1950 | #define DDRSS_PHY_1165_DATA 0x00000000 |
| 1951 | #define DDRSS_PHY_1166_DATA 0x00000000 |
| 1952 | #define DDRSS_PHY_1167_DATA 0x00000000 |
| 1953 | #define DDRSS_PHY_1168_DATA 0x00000000 |
| 1954 | #define DDRSS_PHY_1169_DATA 0x00000000 |
| 1955 | #define DDRSS_PHY_1170_DATA 0x00000000 |
| 1956 | #define DDRSS_PHY_1171_DATA 0x00000000 |
| 1957 | #define DDRSS_PHY_1172_DATA 0x00000000 |
| 1958 | #define DDRSS_PHY_1173_DATA 0x00000000 |
| 1959 | #define DDRSS_PHY_1174_DATA 0x00000000 |
| 1960 | #define DDRSS_PHY_1175_DATA 0x00000000 |
| 1961 | #define DDRSS_PHY_1176_DATA 0x00000000 |
| 1962 | #define DDRSS_PHY_1177_DATA 0x00000000 |
| 1963 | #define DDRSS_PHY_1178_DATA 0x00000000 |
| 1964 | #define DDRSS_PHY_1179_DATA 0x00000000 |
| 1965 | #define DDRSS_PHY_1180_DATA 0x00000000 |
| 1966 | #define DDRSS_PHY_1181_DATA 0x00000000 |
| 1967 | #define DDRSS_PHY_1182_DATA 0x00000000 |
| 1968 | #define DDRSS_PHY_1183_DATA 0x00000000 |
| 1969 | #define DDRSS_PHY_1184_DATA 0x00000000 |
| 1970 | #define DDRSS_PHY_1185_DATA 0x00000000 |
| 1971 | #define DDRSS_PHY_1186_DATA 0x00000000 |
| 1972 | #define DDRSS_PHY_1187_DATA 0x00000000 |
| 1973 | #define DDRSS_PHY_1188_DATA 0x00000000 |
| 1974 | #define DDRSS_PHY_1189_DATA 0x00000000 |
| 1975 | #define DDRSS_PHY_1190_DATA 0x00000000 |
| 1976 | #define DDRSS_PHY_1191_DATA 0x00000000 |
| 1977 | #define DDRSS_PHY_1192_DATA 0x00000000 |
| 1978 | #define DDRSS_PHY_1193_DATA 0x00000000 |
| 1979 | #define DDRSS_PHY_1194_DATA 0x00000000 |
| 1980 | #define DDRSS_PHY_1195_DATA 0x00000000 |
| 1981 | #define DDRSS_PHY_1196_DATA 0x00000000 |
| 1982 | #define DDRSS_PHY_1197_DATA 0x00000000 |
| 1983 | #define DDRSS_PHY_1198_DATA 0x00000000 |
| 1984 | #define DDRSS_PHY_1199_DATA 0x00000000 |
| 1985 | #define DDRSS_PHY_1200_DATA 0x00000000 |
| 1986 | #define DDRSS_PHY_1201_DATA 0x00000000 |
| 1987 | #define DDRSS_PHY_1202_DATA 0x00000000 |
| 1988 | #define DDRSS_PHY_1203_DATA 0x00000000 |
| 1989 | #define DDRSS_PHY_1204_DATA 0x00000000 |
| 1990 | #define DDRSS_PHY_1205_DATA 0x00000000 |
| 1991 | #define DDRSS_PHY_1206_DATA 0x00000000 |
| 1992 | #define DDRSS_PHY_1207_DATA 0x00000000 |
| 1993 | #define DDRSS_PHY_1208_DATA 0x00000000 |
| 1994 | #define DDRSS_PHY_1209_DATA 0x00000000 |
| 1995 | #define DDRSS_PHY_1210_DATA 0x00000000 |
| 1996 | #define DDRSS_PHY_1211_DATA 0x00000000 |
| 1997 | #define DDRSS_PHY_1212_DATA 0x00000000 |
| 1998 | #define DDRSS_PHY_1213_DATA 0x00000000 |
| 1999 | #define DDRSS_PHY_1214_DATA 0x00000000 |
| 2000 | #define DDRSS_PHY_1215_DATA 0x00000000 |
| 2001 | #define DDRSS_PHY_1216_DATA 0x00000000 |
| 2002 | #define DDRSS_PHY_1217_DATA 0x00000000 |
| 2003 | #define DDRSS_PHY_1218_DATA 0x00000000 |
| 2004 | #define DDRSS_PHY_1219_DATA 0x00000000 |
| 2005 | #define DDRSS_PHY_1220_DATA 0x00000000 |
| 2006 | #define DDRSS_PHY_1221_DATA 0x00000000 |
| 2007 | #define DDRSS_PHY_1222_DATA 0x00000000 |
| 2008 | #define DDRSS_PHY_1223_DATA 0x00000000 |
| 2009 | #define DDRSS_PHY_1224_DATA 0x00000000 |
| 2010 | #define DDRSS_PHY_1225_DATA 0x00000000 |
| 2011 | #define DDRSS_PHY_1226_DATA 0x00000000 |
| 2012 | #define DDRSS_PHY_1227_DATA 0x00000000 |
| 2013 | #define DDRSS_PHY_1228_DATA 0x00000000 |
| 2014 | #define DDRSS_PHY_1229_DATA 0x00000000 |
| 2015 | #define DDRSS_PHY_1230_DATA 0x00000000 |
| 2016 | #define DDRSS_PHY_1231_DATA 0x00000000 |
| 2017 | #define DDRSS_PHY_1232_DATA 0x00000000 |
| 2018 | #define DDRSS_PHY_1233_DATA 0x00000000 |
| 2019 | #define DDRSS_PHY_1234_DATA 0x00000000 |
| 2020 | #define DDRSS_PHY_1235_DATA 0x00000000 |
| 2021 | #define DDRSS_PHY_1236_DATA 0x00000000 |
| 2022 | #define DDRSS_PHY_1237_DATA 0x00000000 |
| 2023 | #define DDRSS_PHY_1238_DATA 0x00000000 |
| 2024 | #define DDRSS_PHY_1239_DATA 0x00000000 |
| 2025 | #define DDRSS_PHY_1240_DATA 0x00000000 |
| 2026 | #define DDRSS_PHY_1241_DATA 0x00000000 |
| 2027 | #define DDRSS_PHY_1242_DATA 0x00000000 |
| 2028 | #define DDRSS_PHY_1243_DATA 0x00000000 |
| 2029 | #define DDRSS_PHY_1244_DATA 0x00000000 |
| 2030 | #define DDRSS_PHY_1245_DATA 0x00000000 |
| 2031 | #define DDRSS_PHY_1246_DATA 0x00000000 |
| 2032 | #define DDRSS_PHY_1247_DATA 0x00000000 |
| 2033 | #define DDRSS_PHY_1248_DATA 0x00000000 |
| 2034 | #define DDRSS_PHY_1249_DATA 0x00000000 |
| 2035 | #define DDRSS_PHY_1250_DATA 0x00000000 |
| 2036 | #define DDRSS_PHY_1251_DATA 0x00000000 |
| 2037 | #define DDRSS_PHY_1252_DATA 0x00000000 |
| 2038 | #define DDRSS_PHY_1253_DATA 0x00000000 |
| 2039 | #define DDRSS_PHY_1254_DATA 0x00000000 |
| 2040 | #define DDRSS_PHY_1255_DATA 0x00000000 |
| 2041 | #define DDRSS_PHY_1256_DATA 0x00000000 |
| 2042 | #define DDRSS_PHY_1257_DATA 0x00000000 |
| 2043 | #define DDRSS_PHY_1258_DATA 0x00000000 |
| 2044 | #define DDRSS_PHY_1259_DATA 0x00000000 |
| 2045 | #define DDRSS_PHY_1260_DATA 0x00000000 |
| 2046 | #define DDRSS_PHY_1261_DATA 0x00000000 |
| 2047 | #define DDRSS_PHY_1262_DATA 0x00000000 |
| 2048 | #define DDRSS_PHY_1263_DATA 0x00000000 |
| 2049 | #define DDRSS_PHY_1264_DATA 0x00000000 |
| 2050 | #define DDRSS_PHY_1265_DATA 0x00000000 |
| 2051 | #define DDRSS_PHY_1266_DATA 0x00000000 |
| 2052 | #define DDRSS_PHY_1267_DATA 0x00000000 |
| 2053 | #define DDRSS_PHY_1268_DATA 0x00000000 |
| 2054 | #define DDRSS_PHY_1269_DATA 0x00000000 |
| 2055 | #define DDRSS_PHY_1270_DATA 0x00000000 |
| 2056 | #define DDRSS_PHY_1271_DATA 0x00000000 |
| 2057 | #define DDRSS_PHY_1272_DATA 0x00000000 |
| 2058 | #define DDRSS_PHY_1273_DATA 0x00000000 |
| 2059 | #define DDRSS_PHY_1274_DATA 0x00000000 |
| 2060 | #define DDRSS_PHY_1275_DATA 0x00000000 |
| 2061 | #define DDRSS_PHY_1276_DATA 0x00000000 |
| 2062 | #define DDRSS_PHY_1277_DATA 0x00000000 |
| 2063 | #define DDRSS_PHY_1278_DATA 0x00000000 |
| 2064 | #define DDRSS_PHY_1279_DATA 0x00000000 |
| 2065 | #define DDRSS_PHY_1280_DATA 0x00000000 |
| 2066 | #define DDRSS_PHY_1281_DATA 0x00010100 |
| 2067 | #define DDRSS_PHY_1282_DATA 0x00000000 |
| 2068 | #define DDRSS_PHY_1283_DATA 0x00000000 |
| 2069 | #define DDRSS_PHY_1284_DATA 0x00000000 |
| 2070 | #define DDRSS_PHY_1285_DATA 0x00000000 |
| 2071 | #define DDRSS_PHY_1286_DATA 0x00050000 |
| 2072 | #define DDRSS_PHY_1287_DATA 0x04000000 |
| 2073 | #define DDRSS_PHY_1288_DATA 0x00000055 |
| 2074 | #define DDRSS_PHY_1289_DATA 0x00000000 |
| 2075 | #define DDRSS_PHY_1290_DATA 0x00000000 |
| 2076 | #define DDRSS_PHY_1291_DATA 0x00000000 |
| 2077 | #define DDRSS_PHY_1292_DATA 0x00000000 |
| 2078 | #define DDRSS_PHY_1293_DATA 0x00002001 |
| 2079 | #define DDRSS_PHY_1294_DATA 0x00004001 |
| 2080 | #define DDRSS_PHY_1295_DATA 0x00020028 |
| 2081 | #define DDRSS_PHY_1296_DATA 0x01010100 |
| 2082 | #define DDRSS_PHY_1297_DATA 0x00000000 |
| 2083 | #define DDRSS_PHY_1298_DATA 0x00000000 |
| 2084 | #define DDRSS_PHY_1299_DATA 0x0F0F0E06 |
| 2085 | #define DDRSS_PHY_1300_DATA 0x00010101 |
| 2086 | #define DDRSS_PHY_1301_DATA 0x010F0004 |
| 2087 | #define DDRSS_PHY_1302_DATA 0x00000000 |
| 2088 | #define DDRSS_PHY_1303_DATA 0x00000000 |
| 2089 | #define DDRSS_PHY_1304_DATA 0x00000064 |
| 2090 | #define DDRSS_PHY_1305_DATA 0x00000000 |
| 2091 | #define DDRSS_PHY_1306_DATA 0x00000000 |
| 2092 | #define DDRSS_PHY_1307_DATA 0x01020103 |
| 2093 | #define DDRSS_PHY_1308_DATA 0x0F020102 |
| 2094 | #define DDRSS_PHY_1309_DATA 0x03030303 |
| 2095 | #define DDRSS_PHY_1310_DATA 0x03030303 |
| 2096 | #define DDRSS_PHY_1311_DATA 0x00041B42 |
| 2097 | #define DDRSS_PHY_1312_DATA 0x00005201 |
| 2098 | #define DDRSS_PHY_1313_DATA 0x00000000 |
| 2099 | #define DDRSS_PHY_1314_DATA 0x00000000 |
| 2100 | #define DDRSS_PHY_1315_DATA 0x00000000 |
| 2101 | #define DDRSS_PHY_1316_DATA 0x00000000 |
| 2102 | #define DDRSS_PHY_1317_DATA 0x00000000 |
| 2103 | #define DDRSS_PHY_1318_DATA 0x00000000 |
| 2104 | #define DDRSS_PHY_1319_DATA 0x07030101 |
| 2105 | #define DDRSS_PHY_1320_DATA 0x00005400 |
| 2106 | #define DDRSS_PHY_1321_DATA 0x000040A2 |
| 2107 | #define DDRSS_PHY_1322_DATA 0x00024410 |
| 2108 | #define DDRSS_PHY_1323_DATA 0x00004410 |
| 2109 | #define DDRSS_PHY_1324_DATA 0x00004410 |
| 2110 | #define DDRSS_PHY_1325_DATA 0x00004410 |
| 2111 | #define DDRSS_PHY_1326_DATA 0x00004410 |
| 2112 | #define DDRSS_PHY_1327_DATA 0x00004410 |
| 2113 | #define DDRSS_PHY_1328_DATA 0x00004410 |
| 2114 | #define DDRSS_PHY_1329_DATA 0x00004410 |
| 2115 | #define DDRSS_PHY_1330_DATA 0x00004410 |
| 2116 | #define DDRSS_PHY_1331_DATA 0x00004410 |
| 2117 | #define DDRSS_PHY_1332_DATA 0x00000000 |
| 2118 | #define DDRSS_PHY_1333_DATA 0x00000076 |
| 2119 | #define DDRSS_PHY_1334_DATA 0x00010000 |
| 2120 | #define DDRSS_PHY_1335_DATA 0x00000008 |
| 2121 | #define DDRSS_PHY_1336_DATA 0x00000000 |
| 2122 | #define DDRSS_PHY_1337_DATA 0x00000000 |
| 2123 | #define DDRSS_PHY_1338_DATA 0x00000000 |
| 2124 | #define DDRSS_PHY_1339_DATA 0x00000000 |
| 2125 | #define DDRSS_PHY_1340_DATA 0x00000000 |
| 2126 | #define DDRSS_PHY_1341_DATA 0x03000000 |
| 2127 | #define DDRSS_PHY_1342_DATA 0x00000000 |
| 2128 | #define DDRSS_PHY_1343_DATA 0x00000000 |
| 2129 | #define DDRSS_PHY_1344_DATA 0x00000000 |
| 2130 | #define DDRSS_PHY_1345_DATA 0x04102006 |
| 2131 | #define DDRSS_PHY_1346_DATA 0x00041020 |
| 2132 | #define DDRSS_PHY_1347_DATA 0x01C98C98 |
| 2133 | #define DDRSS_PHY_1348_DATA 0x3F400000 |
| 2134 | #define DDRSS_PHY_1349_DATA 0x3F3F1F3F |
| 2135 | #define DDRSS_PHY_1350_DATA 0x0000001F |
| 2136 | #define DDRSS_PHY_1351_DATA 0x00000000 |
| 2137 | #define DDRSS_PHY_1352_DATA 0x00000000 |
| 2138 | #define DDRSS_PHY_1353_DATA 0x00000000 |
| 2139 | #define DDRSS_PHY_1354_DATA 0x00000001 |
| 2140 | #define DDRSS_PHY_1355_DATA 0x00000000 |
| 2141 | #define DDRSS_PHY_1356_DATA 0x00000000 |
| 2142 | #define DDRSS_PHY_1357_DATA 0x00000000 |
| 2143 | #define DDRSS_PHY_1358_DATA 0x00000000 |
| 2144 | #define DDRSS_PHY_1359_DATA 0x76543210 |
| 2145 | #define DDRSS_PHY_1360_DATA 0x00040198 |
| 2146 | #define DDRSS_PHY_1361_DATA 0x00000000 |
| 2147 | #define DDRSS_PHY_1362_DATA 0x00000000 |
| 2148 | #define DDRSS_PHY_1363_DATA 0x00000000 |
| 2149 | #define DDRSS_PHY_1364_DATA 0x00040700 |
| 2150 | #define DDRSS_PHY_1365_DATA 0x00000000 |
| 2151 | #define DDRSS_PHY_1366_DATA 0x00000000 |
| 2152 | #define DDRSS_PHY_1367_DATA 0x00000000 |
| 2153 | #define DDRSS_PHY_1368_DATA 0x00000002 |
| 2154 | #define DDRSS_PHY_1369_DATA 0x00000000 |
| 2155 | #define DDRSS_PHY_1370_DATA 0x00000000 |
| 2156 | #define DDRSS_PHY_1371_DATA 0x0001F7C0 |
| 2157 | #define DDRSS_PHY_1372_DATA 0x00000002 |
| 2158 | #define DDRSS_PHY_1373_DATA 0x00000000 |
| 2159 | #define DDRSS_PHY_1374_DATA 0x00001142 |
| Sinthu Raja | 7b9717c | 2021-11-29 17:34:49 +0530 | [diff] [blame] | 2160 | #define DDRSS_PHY_1375_DATA 0x03020000 |
| Lokesh Vutla | 86106ed | 2021-05-06 16:45:00 +0530 | [diff] [blame] | 2161 | #define DDRSS_PHY_1376_DATA 0x00000080 |
| 2162 | #define DDRSS_PHY_1377_DATA 0x03900390 |
| 2163 | #define DDRSS_PHY_1378_DATA 0x03900390 |
| 2164 | #define DDRSS_PHY_1379_DATA 0x03900390 |
| 2165 | #define DDRSS_PHY_1380_DATA 0x03900390 |
| 2166 | #define DDRSS_PHY_1381_DATA 0x03000300 |
| 2167 | #define DDRSS_PHY_1382_DATA 0x03000300 |
| 2168 | #define DDRSS_PHY_1383_DATA 0x00000300 |
| 2169 | #define DDRSS_PHY_1384_DATA 0x00000300 |
| 2170 | #define DDRSS_PHY_1385_DATA 0x00000300 |
| 2171 | #define DDRSS_PHY_1386_DATA 0x00000300 |
| 2172 | #define DDRSS_PHY_1387_DATA 0x3183BF77 |
| 2173 | #define DDRSS_PHY_1388_DATA 0x00000000 |
| 2174 | #define DDRSS_PHY_1389_DATA 0x0C000DFF |
| 2175 | #define DDRSS_PHY_1390_DATA 0x30000DFF |
| 2176 | #define DDRSS_PHY_1391_DATA 0x3F0DFF11 |
| 2177 | #define DDRSS_PHY_1392_DATA 0x01990000 |
| 2178 | #define DDRSS_PHY_1393_DATA 0x780DFFCC |
| 2179 | #define DDRSS_PHY_1394_DATA 0x00000C11 |
| 2180 | #define DDRSS_PHY_1395_DATA 0x00018011 |
| 2181 | #define DDRSS_PHY_1396_DATA 0x0089FF00 |
| 2182 | #define DDRSS_PHY_1397_DATA 0x000C3F11 |
| 2183 | #define DDRSS_PHY_1398_DATA 0x01990000 |
| 2184 | #define DDRSS_PHY_1399_DATA 0x000C3F11 |
| 2185 | #define DDRSS_PHY_1400_DATA 0x01990000 |
| 2186 | #define DDRSS_PHY_1401_DATA 0x3F0DFF11 |
| 2187 | #define DDRSS_PHY_1402_DATA 0x019900E0 |
| 2188 | #define DDRSS_PHY_1403_DATA 0x00018011 |
| 2189 | #define DDRSS_PHY_1404_DATA 0x0089FF00 |
| 2190 | #define DDRSS_PHY_1405_DATA 0x20040001 |