wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2000 |
| 3 | * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it |
| 4 | * |
| 5 | * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 6 | * Marius Groeger <mgroeger@sysgo.de> |
| 7 | * |
| 8 | * (C) Copyright 2003 Pengutronix e.K. |
| 9 | * Robert Schwebel <r.schwebel@pengutronix.de> |
| 10 | * |
| 11 | * See file CREDITS for list of people who contributed to this |
| 12 | * project. |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or |
| 15 | * modify it under the terms of the GNU General Public License as |
| 16 | * published by the Free Software Foundation; either version 2 of |
| 17 | * the License, or (at your option) any later version. |
| 18 | * |
| 19 | * This program is distributed in the hope that it will be useful, |
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 22 | * GNU General Public License for more details. |
| 23 | * |
| 24 | * You should have received a copy of the GNU General Public License |
| 25 | * along with this program; if not, write to the Free Software |
| 26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 27 | * MA 02111-1307 USA |
| 28 | * |
| 29 | * Back ported to the 8xx platform (from the 8260 platform) by |
| 30 | * Murray.Jensen@cmst.csiro.au, 27-Jan-01. |
| 31 | */ |
| 32 | |
| 33 | /* FIXME: this file is PXA255 specific! What about other XScales? */ |
| 34 | |
| 35 | #include <common.h> |
| 36 | |
| 37 | #ifdef CONFIG_HARD_I2C |
| 38 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 39 | /* |
| 40 | * - CFG_I2C_SPEED |
| 41 | * - I2C_PXA_SLAVE_ADDR |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 42 | */ |
| 43 | |
wdenk | cc1e256 | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 44 | #include <asm/arch/hardware.h> |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 45 | #include <asm/arch/pxa-regs.h> |
| 46 | #include <i2c.h> |
| 47 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 48 | /*#define DEBUG_I2C 1 /###* activate local debugging output */ |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 49 | #define I2C_PXA_SLAVE_ADDR 0x1 /* slave pxa unit address */ |
| 50 | #define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) |
| 51 | #define I2C_ISR_INIT 0x7FF |
| 52 | |
| 53 | #ifdef DEBUG_I2C |
| 54 | #define PRINTD(x) printf x |
| 55 | #else |
| 56 | #define PRINTD(x) |
| 57 | #endif |
| 58 | |
| 59 | |
| 60 | /* Shall the current transfer have a start/stop condition? */ |
| 61 | #define I2C_COND_NORMAL 0 |
| 62 | #define I2C_COND_START 1 |
| 63 | #define I2C_COND_STOP 2 |
| 64 | |
| 65 | /* Shall the current transfer be ack/nacked or being waited for it? */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 66 | #define I2C_ACKNAK_WAITACK 1 |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 67 | #define I2C_ACKNAK_SENDACK 2 |
| 68 | #define I2C_ACKNAK_SENDNAK 4 |
| 69 | |
| 70 | /* Specify who shall transfer the data (master or slave) */ |
| 71 | #define I2C_READ 0 |
| 72 | #define I2C_WRITE 1 |
| 73 | |
| 74 | /* All transfers are described by this data structure */ |
| 75 | struct i2c_msg { |
| 76 | u8 condition; |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 77 | u8 acknack; |
| 78 | u8 direction; |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 79 | u8 data; |
| 80 | }; |
| 81 | |
| 82 | |
| 83 | /** |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 84 | * i2c_pxa_reset: - reset the host controller |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 85 | * |
| 86 | */ |
| 87 | |
| 88 | static void i2c_reset( void ) |
| 89 | { |
| 90 | ICR &= ~ICR_IUE; /* disable unit */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 91 | ICR |= ICR_UR; /* reset the unit */ |
| 92 | udelay(100); |
| 93 | ICR &= ~ICR_IUE; /* disable unit */ |
| 94 | CKEN |= CKEN14_I2C; /* set the global I2C clock on */ |
| 95 | ISAR = I2C_PXA_SLAVE_ADDR; /* set our slave address */ |
| 96 | ICR = I2C_ICR_INIT; /* set control register values */ |
| 97 | ISR = I2C_ISR_INIT; /* set clear interrupt bits */ |
| 98 | ICR |= ICR_IUE; /* enable unit */ |
| 99 | udelay(100); |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 100 | } |
| 101 | |
| 102 | |
| 103 | /** |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 104 | * i2c_isr_set_cleared: - wait until certain bits of the I2C status register |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 105 | * are set and cleared |
| 106 | * |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 107 | * @return: 0 in case of success, 1 means timeout (no match within 10 ms). |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 108 | */ |
| 109 | |
| 110 | static int i2c_isr_set_cleared( unsigned long set_mask, unsigned long cleared_mask ) |
| 111 | { |
| 112 | int timeout = 10000; |
| 113 | |
| 114 | while( ((ISR & set_mask)!=set_mask) || ((ISR & cleared_mask)!=0) ){ |
| 115 | udelay( 10 ); |
| 116 | if( timeout-- < 0 ) return 0; |
| 117 | } |
| 118 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 119 | return 1; |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 120 | } |
| 121 | |
| 122 | |
| 123 | /** |
| 124 | * i2c_transfer: - Transfer one byte over the i2c bus |
| 125 | * |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 126 | * This function can tranfer a byte over the i2c bus in both directions. |
| 127 | * It is used by the public API functions. |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 128 | * |
| 129 | * @return: 0: transfer successful |
| 130 | * -1: message is empty |
| 131 | * -2: transmit timeout |
| 132 | * -3: ACK missing |
| 133 | * -4: receive timeout |
| 134 | * -5: illegal parameters |
| 135 | * -6: bus is busy and couldn't be aquired |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 136 | */ |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 137 | int i2c_transfer(struct i2c_msg *msg) |
| 138 | { |
| 139 | int ret; |
| 140 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 141 | if (!msg) |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 142 | goto transfer_error_msg_empty; |
| 143 | |
| 144 | switch(msg->direction) { |
| 145 | |
| 146 | case I2C_WRITE: |
| 147 | |
| 148 | /* check if bus is not busy */ |
| 149 | if (!i2c_isr_set_cleared(0,ISR_IBB)) |
| 150 | goto transfer_error_bus_busy; |
| 151 | |
| 152 | /* start transmission */ |
| 153 | ICR &= ~ICR_START; |
| 154 | ICR &= ~ICR_STOP; |
| 155 | IDBR = msg->data; |
| 156 | if (msg->condition == I2C_COND_START) ICR |= ICR_START; |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 157 | if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP; |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 158 | if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK; |
| 159 | if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK; |
| 160 | ICR &= ~ICR_ALDIE; |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 161 | ICR |= ICR_TB; |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 162 | |
| 163 | /* transmit register empty? */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 164 | if (!i2c_isr_set_cleared(ISR_ITE,0)) |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 165 | goto transfer_error_transmit_timeout; |
| 166 | |
| 167 | /* clear 'transmit empty' state */ |
| 168 | ISR |= ISR_ITE; |
| 169 | |
| 170 | /* wait for ACK from slave */ |
| 171 | if (msg->acknack == I2C_ACKNAK_WAITACK) |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 172 | if (!i2c_isr_set_cleared(0,ISR_ACKNAK)) |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 173 | goto transfer_error_ack_missing; |
| 174 | break; |
| 175 | |
| 176 | case I2C_READ: |
| 177 | |
| 178 | /* check if bus is not busy */ |
| 179 | if (!i2c_isr_set_cleared(0,ISR_IBB)) |
| 180 | goto transfer_error_bus_busy; |
| 181 | |
| 182 | /* start receive */ |
| 183 | ICR &= ~ICR_START; |
| 184 | ICR &= ~ICR_STOP; |
| 185 | if (msg->condition == I2C_COND_START) ICR |= ICR_START; |
| 186 | if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP; |
| 187 | if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK; |
| 188 | if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK; |
| 189 | ICR &= ~ICR_ALDIE; |
| 190 | ICR |= ICR_TB; |
| 191 | |
| 192 | /* receive register full? */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 193 | if (!i2c_isr_set_cleared(ISR_IRF,0)) |
| 194 | goto transfer_error_receive_timeout; |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 195 | |
| 196 | msg->data = IDBR; |
| 197 | |
| 198 | /* clear 'receive empty' state */ |
| 199 | ISR |= ISR_IRF; |
| 200 | |
| 201 | break; |
| 202 | |
| 203 | default: |
| 204 | |
| 205 | goto transfer_error_illegal_param; |
| 206 | |
| 207 | } |
| 208 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 209 | return 0; |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 210 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 211 | transfer_error_msg_empty: |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 212 | PRINTD(("i2c_transfer: error: 'msg' is empty\n")); |
| 213 | ret = -1; goto i2c_transfer_finish; |
| 214 | |
| 215 | transfer_error_transmit_timeout: |
| 216 | PRINTD(("i2c_transfer: error: transmit timeout\n")); |
| 217 | ret = -2; goto i2c_transfer_finish; |
| 218 | |
| 219 | transfer_error_ack_missing: |
| 220 | PRINTD(("i2c_transfer: error: ACK missing\n")); |
| 221 | ret = -3; goto i2c_transfer_finish; |
| 222 | |
| 223 | transfer_error_receive_timeout: |
| 224 | PRINTD(("i2c_transfer: error: receive timeout\n")); |
| 225 | ret = -4; goto i2c_transfer_finish; |
| 226 | |
| 227 | transfer_error_illegal_param: |
| 228 | PRINTD(("i2c_transfer: error: illegal parameters\n")); |
| 229 | ret = -5; goto i2c_transfer_finish; |
| 230 | |
| 231 | transfer_error_bus_busy: |
| 232 | PRINTD(("i2c_transfer: error: bus is busy\n")); |
| 233 | ret = -6; goto i2c_transfer_finish; |
| 234 | |
| 235 | i2c_transfer_finish: |
| 236 | PRINTD(("i2c_transfer: ISR: 0x%04x\n",ISR)); |
| 237 | i2c_reset(); |
| 238 | return ret; |
| 239 | |
| 240 | } |
| 241 | |
| 242 | /* ------------------------------------------------------------------------ */ |
| 243 | /* API Functions */ |
| 244 | /* ------------------------------------------------------------------------ */ |
| 245 | |
| 246 | void i2c_init(int speed, int slaveaddr) |
| 247 | { |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 248 | #ifdef CFG_I2C_INIT_BOARD |
wdenk | cc1e256 | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 249 | /* call board specific i2c bus reset routine before accessing the */ |
| 250 | /* environment, which might be in a chip on that bus. For details */ |
| 251 | /* about this problem see doc/I2C_Edge_Conditions. */ |
| 252 | i2c_init_board(); |
| 253 | #endif |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 254 | } |
| 255 | |
| 256 | |
| 257 | /** |
| 258 | * i2c_probe: - Test if a chip answers for a given i2c address |
| 259 | * |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 260 | * @chip: address of the chip which is searched for |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 261 | * @return: 0 if a chip was found, -1 otherwhise |
| 262 | */ |
| 263 | |
| 264 | int i2c_probe(uchar chip) |
| 265 | { |
| 266 | struct i2c_msg msg; |
| 267 | |
| 268 | i2c_reset(); |
| 269 | |
| 270 | msg.condition = I2C_COND_START; |
| 271 | msg.acknack = I2C_ACKNAK_WAITACK; |
| 272 | msg.direction = I2C_WRITE; |
| 273 | msg.data = (chip << 1) + 1; |
| 274 | if (i2c_transfer(&msg)) return -1; |
| 275 | |
| 276 | msg.condition = I2C_COND_STOP; |
| 277 | msg.acknack = I2C_ACKNAK_SENDNAK; |
| 278 | msg.direction = I2C_READ; |
| 279 | msg.data = 0x00; |
| 280 | if (i2c_transfer(&msg)) return -1; |
| 281 | |
| 282 | return 0; |
| 283 | } |
| 284 | |
| 285 | |
| 286 | /** |
| 287 | * i2c_read: - Read multiple bytes from an i2c device |
| 288 | * |
| 289 | * The higher level routines take into account that this function is only |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 290 | * called with len < page length of the device (see configuration file) |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 291 | * |
| 292 | * @chip: address of the chip which is to be read |
| 293 | * @addr: i2c data address within the chip |
| 294 | * @alen: length of the i2c data address (1..2 bytes) |
| 295 | * @buffer: where to write the data |
| 296 | * @len: how much byte do we want to read |
| 297 | * @return: 0 in case of success |
| 298 | */ |
| 299 | |
| 300 | int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) |
| 301 | { |
| 302 | struct i2c_msg msg; |
| 303 | u8 addr_bytes[3]; /* lowest...highest byte of data address */ |
| 304 | int ret; |
| 305 | |
| 306 | PRINTD(("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, len=0x%02x)\n",chip,addr,alen,len)); |
| 307 | |
| 308 | i2c_reset(); |
| 309 | |
| 310 | /* dummy chip address write */ |
| 311 | PRINTD(("i2c_read: dummy chip address write\n")); |
| 312 | msg.condition = I2C_COND_START; |
| 313 | msg.acknack = I2C_ACKNAK_WAITACK; |
| 314 | msg.direction = I2C_WRITE; |
| 315 | msg.data = (chip << 1); |
| 316 | msg.data &= 0xFE; |
| 317 | if ((ret=i2c_transfer(&msg))) return -1; |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 318 | |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 319 | /* |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 320 | * send memory address bytes; |
| 321 | * alen defines how much bytes we have to send. |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 322 | */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 323 | /*addr &= ((1 << CFG_EEPROM_PAGE_WRITE_BITS)-1); */ |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 324 | addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF); |
| 325 | addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF); |
| 326 | addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF); |
| 327 | |
| 328 | while (--alen >= 0) { |
| 329 | |
| 330 | PRINTD(("i2c_read: send memory word address byte %1d\n",alen)); |
| 331 | msg.condition = I2C_COND_NORMAL; |
| 332 | msg.acknack = I2C_ACKNAK_WAITACK; |
| 333 | msg.direction = I2C_WRITE; |
| 334 | msg.data = addr_bytes[alen]; |
| 335 | if ((ret=i2c_transfer(&msg))) return -1; |
| 336 | } |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 337 | |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 338 | |
| 339 | /* start read sequence */ |
| 340 | PRINTD(("i2c_read: start read sequence\n")); |
| 341 | msg.condition = I2C_COND_START; |
| 342 | msg.acknack = I2C_ACKNAK_WAITACK; |
| 343 | msg.direction = I2C_WRITE; |
| 344 | msg.data = (chip << 1); |
| 345 | msg.data |= 0x01; |
| 346 | if ((ret=i2c_transfer(&msg))) return -1; |
| 347 | |
| 348 | /* read bytes; send NACK at last byte */ |
| 349 | while (len--) { |
| 350 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 351 | if (len==0) { |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 352 | msg.condition = I2C_COND_STOP; |
| 353 | msg.acknack = I2C_ACKNAK_SENDNAK; |
| 354 | } else { |
| 355 | msg.condition = I2C_COND_NORMAL; |
| 356 | msg.acknack = I2C_ACKNAK_SENDACK; |
| 357 | } |
| 358 | |
| 359 | msg.direction = I2C_READ; |
| 360 | msg.data = 0x00; |
| 361 | if ((ret=i2c_transfer(&msg))) return -1; |
| 362 | |
| 363 | *(buffer++) = msg.data; |
| 364 | |
| 365 | PRINTD(("i2c_read: reading byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer)); |
| 366 | |
| 367 | } |
| 368 | |
| 369 | i2c_reset(); |
| 370 | |
| 371 | return 0; |
| 372 | } |
| 373 | |
| 374 | |
| 375 | /** |
| 376 | * i2c_write: - Write multiple bytes to an i2c device |
| 377 | * |
| 378 | * The higher level routines take into account that this function is only |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 379 | * called with len < page length of the device (see configuration file) |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 380 | * |
| 381 | * @chip: address of the chip which is to be written |
| 382 | * @addr: i2c data address within the chip |
| 383 | * @alen: length of the i2c data address (1..2 bytes) |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 384 | * @buffer: where to find the data to be written |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 385 | * @len: how much byte do we want to read |
| 386 | * @return: 0 in case of success |
| 387 | */ |
| 388 | |
| 389 | int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) |
| 390 | { |
| 391 | struct i2c_msg msg; |
| 392 | u8 addr_bytes[3]; /* lowest...highest byte of data address */ |
| 393 | |
| 394 | PRINTD(("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, len=0x%02x)\n",chip,addr,alen,len)); |
| 395 | |
| 396 | i2c_reset(); |
| 397 | |
| 398 | /* chip address write */ |
| 399 | PRINTD(("i2c_write: chip address write\n")); |
| 400 | msg.condition = I2C_COND_START; |
| 401 | msg.acknack = I2C_ACKNAK_WAITACK; |
| 402 | msg.direction = I2C_WRITE; |
| 403 | msg.data = (chip << 1); |
| 404 | msg.data &= 0xFE; |
| 405 | if (i2c_transfer(&msg)) return -1; |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 406 | |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 407 | /* |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 408 | * send memory address bytes; |
| 409 | * alen defines how much bytes we have to send. |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 410 | */ |
| 411 | addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF); |
| 412 | addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF); |
| 413 | addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF); |
| 414 | |
| 415 | while (--alen >= 0) { |
| 416 | |
| 417 | PRINTD(("i2c_write: send memory word address\n")); |
| 418 | msg.condition = I2C_COND_NORMAL; |
| 419 | msg.acknack = I2C_ACKNAK_WAITACK; |
| 420 | msg.direction = I2C_WRITE; |
| 421 | msg.data = addr_bytes[alen]; |
| 422 | if (i2c_transfer(&msg)) return -1; |
| 423 | } |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 424 | |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 425 | /* write bytes; send NACK at last byte */ |
| 426 | while (len--) { |
| 427 | |
| 428 | PRINTD(("i2c_write: writing byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer)); |
| 429 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 430 | if (len==0) |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 431 | msg.condition = I2C_COND_STOP; |
| 432 | else |
| 433 | msg.condition = I2C_COND_NORMAL; |
| 434 | |
| 435 | msg.acknack = I2C_ACKNAK_WAITACK; |
| 436 | msg.direction = I2C_WRITE; |
| 437 | msg.data = *(buffer++); |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 438 | |
wdenk | 4a5c8a7 | 2003-03-06 00:02:04 +0000 | [diff] [blame] | 439 | if (i2c_transfer(&msg)) return -1; |
| 440 | |
| 441 | } |
| 442 | |
| 443 | i2c_reset(); |
| 444 | |
| 445 | return 0; |
| 446 | |
| 447 | } |
| 448 | |
| 449 | uchar i2c_reg_read (uchar chip, uchar reg) |
| 450 | { |
| 451 | PRINTD(("i2c_reg_read(chip=0x%02x, reg=0x%02x)\n",chip,reg)); |
| 452 | return 0; |
| 453 | } |
| 454 | |
| 455 | void i2c_reg_write(uchar chip, uchar reg, uchar val) |
| 456 | { |
| 457 | PRINTD(("i2c_reg_write(chip=0x%02x, reg=0x%02x, val=0x%02x)\n",chip,reg,val)); |
| 458 | } |
| 459 | |
| 460 | #endif /* CONFIG_HARD_I2C */ |