Blame - board/dnp1110/memsetup.S - filogic/uboot

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wdenk	fe8c280	2002-11-03 00:38:21 +0000	[diff] [blame]	1	/*
				2	* Memory Setup stuff - taken from blob memsetup.S
				3	*
				4	* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
				5	* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
				6	*
				7	* See file CREDITS for list of people who contributed to this
				8	* project.
				9	*
				10	* This program is free software; you can redistribute it and/or
				11	* modify it under the terms of the GNU General Public License as
				12	* published by the Free Software Foundation; either version 2 of
				13	* the License, or (at your option) any later version.
				14	*
				15	* This program is distributed in the hope that it will be useful,
				16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
				17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
				18	* GNU General Public License for more details.
				19	*
				20	* You should have received a copy of the GNU General Public License
				21	* along with this program; if not, write to the Free Software
				22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
				23	* MA 02111-1307 USA
				24	*/
				25
				26
wdenk	c8434db	2003-03-26 06:55:25 +0000	[diff] [blame]	27	#include "config.h"
				28	#include "version.h"
wdenk	fe8c280	2002-11-03 00:38:21 +0000	[diff] [blame]	29
				30
				31	/* some parameters for the board */
				32
				33	MEM_BASE: .long 0xa0000000
				34	MEM_START: .long 0xc0000000
				35
wdenk	c8434db	2003-03-26 06:55:25 +0000	[diff] [blame]	36	#define MDCNFG 0x00
				37	#define MDCAS00 0x04 /* CAS waveform rotate reg 0 */
				38	#define MDCAS01 0x08 /* CAS waveform rotate reg 1 bank */
				39	#define MDCAS02 0x0C /* CAS waveform rotate reg 2 bank */
				40	#define MDREFR 0x1C /* DRAM refresh control reg */
wdenk	57b2d80	2003-06-27 21:31:46 +0000	[diff] [blame^]	41	#define MDCAS20 0x20 /* CAS waveform rotate reg 0 bank */
wdenk	c8434db	2003-03-26 06:55:25 +0000	[diff] [blame]	42	#define MDCAS21 0x24 /* CAS waveform rotate reg 1 bank */
				43	#define MDCAS22 0x28 /* CAS waveform rotate reg 2 bank */
				44	#define MECR 0x18 /* Expansion memory (PCMCIA) bus configuration register */
				45	#define MSC0 0x10 /* static memory control reg 0 */
				46	#define MSC1 0x14 /* static memory control reg 1 */
				47	#define MSC2 0x2C /* static memory control reg 2 */
				48	#define SMCNFG 0x30 /* SMROM configuration reg */
wdenk	fe8c280	2002-11-03 00:38:21 +0000	[diff] [blame]	49
wdenk	c8434db	2003-03-26 06:55:25 +0000	[diff] [blame]	50	mdcas00: .long 0x5555557F
				51	mdcas01: .long 0x55555555
				52	mdcas02: .long 0x55555555
				53	mdcas20: .long 0x5555557F
				54	mdcas21: .long 0x55555555
				55	mdcas22: .long 0x55555555
				56	mdcnfg: .long 0x0000B25C
				57	mdrefr: .long 0x007000C1
				58	mecr: .long 0x10841084
				59	msc0: .long 0x00004774
				60	msc1: .long 0x00000000
				61	msc2: .long 0x00000000
				62	smcnfg: .long 0x00000000
wdenk	fe8c280	2002-11-03 00:38:21 +0000	[diff] [blame]	63
				64	/* setting up the memory */
				65
				66	.globl memsetup
				67	memsetup:
wdenk	fe8c280	2002-11-03 00:38:21 +0000	[diff] [blame]	68
wdenk	c8434db	2003-03-26 06:55:25 +0000	[diff] [blame]	69	ldr r0, MEM_BASE
wdenk	fe8c280	2002-11-03 00:38:21 +0000	[diff] [blame]	70
				71	/* Set up the DRAM */
				72
wdenk	c8434db	2003-03-26 06:55:25 +0000	[diff] [blame]	73	/* MDCAS00 */
				74	ldr r1, mdcas00
				75	str r1, [r0, #MDCAS00]
wdenk	fe8c280	2002-11-03 00:38:21 +0000	[diff] [blame]	76
wdenk	c8434db	2003-03-26 06:55:25 +0000	[diff] [blame]	77	/* MDCAS01 */
				78	ldr r1, mdcas01
				79	str r1, [r0, #MDCAS01]
wdenk	fe8c280	2002-11-03 00:38:21 +0000	[diff] [blame]	80
wdenk	c8434db	2003-03-26 06:55:25 +0000	[diff] [blame]	81	/* MDCAS02 */
				82	ldr r1, mdcas02
				83	str r1, [r0, #MDCAS02]
wdenk	fe8c280	2002-11-03 00:38:21 +0000	[diff] [blame]	84
wdenk	c8434db	2003-03-26 06:55:25 +0000	[diff] [blame]	85	/* MDCAS20 */
				86	ldr r1, mdcas20
				87	str r1, [r0, #MDCAS20]
				88
				89	/* MDCAS21 */
				90	ldr r1, mdcas21
				91	str r1, [r0, #MDCAS21]
				92
				93	/* MDCAS22 */
				94	ldr r1, mdcas22
				95	str r1, [r0, #MDCAS22]
				96
				97	/* MDREFR */
				98	ldr r1, mdrefr
				99	str r1, [r0, #MDREFR]
wdenk	fe8c280	2002-11-03 00:38:21 +0000	[diff] [blame]	100
				101	/* Set up PCMCIA space */
				102	ldr r1, mecr
				103	str r1, [r0, #MECR]
				104
wdenk	c8434db	2003-03-26 06:55:25 +0000	[diff] [blame]	105	/* Setup the flash memory and other */
				106	ldr r1, msc0
				107	str r1, [r0, #MSC0]
wdenk	fe8c280	2002-11-03 00:38:21 +0000	[diff] [blame]	108
wdenk	c8434db	2003-03-26 06:55:25 +0000	[diff] [blame]	109	ldr r1, msc1
				110	str r1, [r0, #MSC1]
				111
				112	ldr r1, msc2
				113	str r1, [r0, #MSC2]
				114
				115	ldr r1, smcnfg
				116	str r1, [r0, #SMCNFG]
				117
				118	/* MDCNFG */
				119	ldr r1, mdcnfg
				120	bic r1, r1, #0x00000001
				121	str r1, [r0, #MDCNFG]
				122
				123	/* Load something to activate bank */
				124	ldr r2, MEM_START
wdenk	fe8c280	2002-11-03 00:38:21 +0000	[diff] [blame]	125	.rept 8
wdenk	c8434db	2003-03-26 06:55:25 +0000	[diff] [blame]	126	ldr r1, [r2]
wdenk	fe8c280	2002-11-03 00:38:21 +0000	[diff] [blame]	127	.endr
				128
wdenk	c8434db	2003-03-26 06:55:25 +0000	[diff] [blame]	129	/* MDCNFG */
				130	ldr r1, mdcnfg
				131	orr r1, r1, #0x00000001
				132	str r1, [r0, #MDCNFG]
				133
wdenk	fe8c280	2002-11-03 00:38:21 +0000	[diff] [blame]	134	/* everything is fine now */
				135	mov pc, lr