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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
TsiChung Liewb354aef2009-06-12 11:29:00 +00002/*
3 * Configuation settings for the Freescale MCF5208EVBe.
4 *
5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChung Liewb354aef2009-06-12 11:29:00 +00007 */
8
9#ifndef _M5208EVBE_H
10#define _M5208EVBE_H
11
12/*
13 * High Level Configuration Options
14 * (easy to change)
15 */
Tom Rini6a5dccc2022-11-16 13:10:41 -050016#define CFG_SYS_UART_PORT (0)
TsiChung Liewb354aef2009-06-12 11:29:00 +000017
TsiChung Liewb354aef2009-06-12 11:29:00 +000018/* I2C */
TsiChung Liewb354aef2009-06-12 11:29:00 +000019
Tom Rinic9edebe2022-12-04 10:03:50 -050020#define CFG_EXTRA_ENV_SETTINGS \
TsiChung Liewb354aef2009-06-12 11:29:00 +000021 "netdev=eth0\0" \
22 "loadaddr=40010000\0" \
23 "u-boot=u-boot.bin\0" \
24 "load=tftp ${loadaddr) ${u-boot}\0" \
25 "upd=run load; run prog\0" \
26 "prog=prot off 0 3ffff;" \
27 "era 0 3ffff;" \
28 "cp.b ${loadaddr} 0 ${filesize};" \
29 "save\0" \
30 ""
31
Tom Rini0bb9b092022-12-04 10:13:37 -050032#define CFG_PRAM 512 /* 512 KB */
TsiChung Liewb354aef2009-06-12 11:29:00 +000033
Tom Rini6a5dccc2022-11-16 13:10:41 -050034#define CFG_SYS_CLK 166666666 /* CPU Core Clock */
35#define CFG_SYS_PLL_ODR 0x36
36#define CFG_SYS_PLL_FDR 0x7D
TsiChung Liewb354aef2009-06-12 11:29:00 +000037
Tom Rini6a5dccc2022-11-16 13:10:41 -050038#define CFG_SYS_MBAR 0xFC000000
TsiChung Liewb354aef2009-06-12 11:29:00 +000039
40/*
41 * Low Level Configuration Settings
42 * (address mappings, register initial values, etc.)
43 * You should know what you are doing if you make changes here.
44 */
45/* Definitions for initial stack pointer and data area (in DPRAM) */
Tom Rini6a5dccc2022-11-16 13:10:41 -050046#define CFG_SYS_INIT_RAM_ADDR 0x80000000
47#define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */
48#define CFG_SYS_INIT_RAM_CTRL 0x221
TsiChung Liewb354aef2009-06-12 11:29:00 +000049
50/*
51 * Start addresses for the final memory configuration
52 * (Set up by the startup code)
Tom Rinibb4dd962022-11-16 13:10:37 -050053 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
TsiChung Liewb354aef2009-06-12 11:29:00 +000054 */
Tom Rinibb4dd962022-11-16 13:10:37 -050055#define CFG_SYS_SDRAM_BASE 0x40000000
56#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
57#define CFG_SYS_SDRAM_CFG1 0x43711630
58#define CFG_SYS_SDRAM_CFG2 0x56670000
59#define CFG_SYS_SDRAM_CTRL 0xE1002000
60#define CFG_SYS_SDRAM_EMOD 0x80010000
61#define CFG_SYS_SDRAM_MODE 0x00CD0000
TsiChung Liewb354aef2009-06-12 11:29:00 +000062
TsiChung Liewb354aef2009-06-12 11:29:00 +000063/*
64 * For booting Linux, the board info and command line data
65 * have to be in the first 8 MB of memory, since this is
66 * the maximum mapped by the Linux kernel during initialization ??
67 */
Tom Rini6a5dccc2022-11-16 13:10:41 -050068#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
TsiChung Liewb354aef2009-06-12 11:29:00 +000069
70/* FLASH organization */
TsiChung Liewb354aef2009-06-12 11:29:00 +000071#ifdef CONFIG_SYS_FLASH_CFI
Tom Rini6a5dccc2022-11-16 13:10:41 -050072# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
TsiChung Liewb354aef2009-06-12 11:29:00 +000073#endif
74
Tom Rini6a5dccc2022-11-16 13:10:41 -050075#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
TsiChung Liewb354aef2009-06-12 11:29:00 +000076
77/*
78 * Configuration for environment
79 * Environment is embedded in u-boot in the second sector of the flash
80 */
TsiChung Liewb354aef2009-06-12 11:29:00 +000081
angelo@sysam.it6312a952015-03-29 22:54:16 +020082#define LDS_BOARD_TEXT \
Simon Glass547cb402017-08-03 12:21:49 -060083 . = DEFINED(env_offset) ? env_offset : .; \
84 env/embedded.o(.text*);
angelo@sysam.it6312a952015-03-29 22:54:16 +020085
TsiChung Liewb354aef2009-06-12 11:29:00 +000086/* Cache Configuration */
TsiChung Liewb354aef2009-06-12 11:29:00 +000087
Tom Rini6a5dccc2022-11-16 13:10:41 -050088#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
89 CFG_SYS_INIT_RAM_SIZE - 8)
90#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
91 CFG_SYS_INIT_RAM_SIZE - 4)
92#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
93#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
Tom Rinibb4dd962022-11-16 13:10:37 -050094 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
TsiChung Liew0ee47d42010-03-11 22:12:53 -060095 CF_ACR_EN | CF_ACR_SM_ALL)
Tom Rini6a5dccc2022-11-16 13:10:41 -050096#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
TsiChung Liew0ee47d42010-03-11 22:12:53 -060097 CF_CACR_DISD | CF_CACR_INVI | \
98 CF_CACR_CEIB | CF_CACR_DCM | \
99 CF_CACR_EUSP)
100
TsiChung Liewb354aef2009-06-12 11:29:00 +0000101/* Chipselect bank definitions */
102/*
103 * CS0 - NOR Flash
104 * CS1 - Available
105 * CS2 - Available
106 * CS3 - Available
107 * CS4 - Available
108 * CS5 - Available
109 */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500110#define CFG_SYS_CS0_BASE 0
111#define CFG_SYS_CS0_MASK 0x007F0001
112#define CFG_SYS_CS0_CTRL 0x00001FA0
TsiChung Liewb354aef2009-06-12 11:29:00 +0000113
Angelo Dureghello49becce2023-02-25 23:25:26 +0100114#define CFG_MCFTMR
115
TsiChung Liewb354aef2009-06-12 11:29:00 +0000116#endif /* _M5208EVBE_H */