Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Configuation settings for the Freescale MCF5208EVBe. |
| 4 | * |
| 5 | * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. |
| 6 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef _M5208EVBE_H |
| 10 | #define _M5208EVBE_H |
| 11 | |
| 12 | /* |
| 13 | * High Level Configuration Options |
| 14 | * (easy to change) |
| 15 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 16 | #define CFG_SYS_UART_PORT (0) |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 17 | |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 18 | /* I2C */ |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 19 | |
Tom Rini | c9edebe | 2022-12-04 10:03:50 -0500 | [diff] [blame] | 20 | #define CFG_EXTRA_ENV_SETTINGS \ |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 21 | "netdev=eth0\0" \ |
| 22 | "loadaddr=40010000\0" \ |
| 23 | "u-boot=u-boot.bin\0" \ |
| 24 | "load=tftp ${loadaddr) ${u-boot}\0" \ |
| 25 | "upd=run load; run prog\0" \ |
| 26 | "prog=prot off 0 3ffff;" \ |
| 27 | "era 0 3ffff;" \ |
| 28 | "cp.b ${loadaddr} 0 ${filesize};" \ |
| 29 | "save\0" \ |
| 30 | "" |
| 31 | |
Tom Rini | 0bb9b09 | 2022-12-04 10:13:37 -0500 | [diff] [blame] | 32 | #define CFG_PRAM 512 /* 512 KB */ |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 33 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 34 | #define CFG_SYS_CLK 166666666 /* CPU Core Clock */ |
| 35 | #define CFG_SYS_PLL_ODR 0x36 |
| 36 | #define CFG_SYS_PLL_FDR 0x7D |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 37 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 38 | #define CFG_SYS_MBAR 0xFC000000 |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 39 | |
| 40 | /* |
| 41 | * Low Level Configuration Settings |
| 42 | * (address mappings, register initial values, etc.) |
| 43 | * You should know what you are doing if you make changes here. |
| 44 | */ |
| 45 | /* Definitions for initial stack pointer and data area (in DPRAM) */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 46 | #define CFG_SYS_INIT_RAM_ADDR 0x80000000 |
| 47 | #define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */ |
| 48 | #define CFG_SYS_INIT_RAM_CTRL 0x221 |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 49 | |
| 50 | /* |
| 51 | * Start addresses for the final memory configuration |
| 52 | * (Set up by the startup code) |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 53 | * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 54 | */ |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 55 | #define CFG_SYS_SDRAM_BASE 0x40000000 |
| 56 | #define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ |
| 57 | #define CFG_SYS_SDRAM_CFG1 0x43711630 |
| 58 | #define CFG_SYS_SDRAM_CFG2 0x56670000 |
| 59 | #define CFG_SYS_SDRAM_CTRL 0xE1002000 |
| 60 | #define CFG_SYS_SDRAM_EMOD 0x80010000 |
| 61 | #define CFG_SYS_SDRAM_MODE 0x00CD0000 |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 62 | |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 63 | /* |
| 64 | * For booting Linux, the board info and command line data |
| 65 | * have to be in the first 8 MB of memory, since this is |
| 66 | * the maximum mapped by the Linux kernel during initialization ?? |
| 67 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 68 | #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 69 | |
| 70 | /* FLASH organization */ |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 71 | #ifdef CONFIG_SYS_FLASH_CFI |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 72 | # define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 73 | #endif |
| 74 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 75 | #define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 76 | |
| 77 | /* |
| 78 | * Configuration for environment |
| 79 | * Environment is embedded in u-boot in the second sector of the flash |
| 80 | */ |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 81 | |
angelo@sysam.it | 6312a95 | 2015-03-29 22:54:16 +0200 | [diff] [blame] | 82 | #define LDS_BOARD_TEXT \ |
Simon Glass | 547cb40 | 2017-08-03 12:21:49 -0600 | [diff] [blame] | 83 | . = DEFINED(env_offset) ? env_offset : .; \ |
| 84 | env/embedded.o(.text*); |
angelo@sysam.it | 6312a95 | 2015-03-29 22:54:16 +0200 | [diff] [blame] | 85 | |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 86 | /* Cache Configuration */ |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 87 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 88 | #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ |
| 89 | CFG_SYS_INIT_RAM_SIZE - 8) |
| 90 | #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ |
| 91 | CFG_SYS_INIT_RAM_SIZE - 4) |
| 92 | #define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) |
| 93 | #define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 94 | CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 95 | CF_ACR_EN | CF_ACR_SM_ALL) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 96 | #define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 97 | CF_CACR_DISD | CF_CACR_INVI | \ |
| 98 | CF_CACR_CEIB | CF_CACR_DCM | \ |
| 99 | CF_CACR_EUSP) |
| 100 | |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 101 | /* Chipselect bank definitions */ |
| 102 | /* |
| 103 | * CS0 - NOR Flash |
| 104 | * CS1 - Available |
| 105 | * CS2 - Available |
| 106 | * CS3 - Available |
| 107 | * CS4 - Available |
| 108 | * CS5 - Available |
| 109 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 110 | #define CFG_SYS_CS0_BASE 0 |
| 111 | #define CFG_SYS_CS0_MASK 0x007F0001 |
| 112 | #define CFG_SYS_CS0_CTRL 0x00001FA0 |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 113 | |
Angelo Dureghello | 49becce | 2023-02-25 23:25:26 +0100 | [diff] [blame] | 114 | #define CFG_MCFTMR |
| 115 | |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 116 | #endif /* _M5208EVBE_H */ |