blob: 76e680481a7c82df15d4c52590db22d40205aedb [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Hou Zhiqiang09716a7b2016-12-13 14:54:16 +08002/*
Wasim Khan54e44ef2020-01-06 12:05:57 +00003 * Copyright 2017-2020 NXP
Hou Zhiqiang09716a7b2016-12-13 14:54:16 +08004 * Copyright 2014-2015 Freescale Semiconductor, Inc.
5 * Layerscape PCIe driver
Hou Zhiqiang09716a7b2016-12-13 14:54:16 +08006 */
7
8#include <common.h>
Simon Glass97589732020-05-10 11:40:02 -06009#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Hou Zhiqiang09716a7b2016-12-13 14:54:16 +080011#include <pci.h>
12#include <asm/arch/fsl_serdes.h>
13#include <asm/io.h>
14#include <errno.h>
15#ifdef CONFIG_OF_BOARD_SETUP
Masahiro Yamada75f82d02018-03-05 01:20:11 +090016#include <linux/libfdt.h>
Hou Zhiqiang09716a7b2016-12-13 14:54:16 +080017#include <fdt_support.h>
Simon Glass243182c2017-05-17 08:23:06 -060018#ifdef CONFIG_ARM
19#include <asm/arch/clock.h>
20#endif
Hou Zhiqiang09716a7b2016-12-13 14:54:16 +080021#include "pcie_layerscape.h"
Wasim Khan54e44ef2020-01-06 12:05:57 +000022#include "pcie_layerscape_fixup_common.h"
Hou Zhiqiang09716a7b2016-12-13 14:54:16 +080023
Bharat Bhushan36e36be2017-03-22 12:06:30 +053024#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
Hou Zhiqiang09716a7b2016-12-13 14:54:16 +080025/*
26 * Return next available LUT index.
27 */
28static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
29{
30 if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
31 return pcie->next_lut_index++;
32 else
33 return -ENOSPC; /* LUT is full */
34}
35
Minghuan Lianc1067842016-12-13 14:54:17 +080036static void lut_writel(struct ls_pcie *pcie, unsigned int value,
37 unsigned int offset)
38{
39 if (pcie->big_endian)
40 out_be32(pcie->lut + offset, value);
41 else
42 out_le32(pcie->lut + offset, value);
43}
44
45/*
46 * Program a single LUT entry
47 */
48static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
49 u32 streamid)
50{
51 /* leave mask as all zeroes, want to match all bits */
52 lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
53 lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
54}
55
56/*
57 * An msi-map is a property to be added to the pci controller
58 * node. It is a table, where each entry consists of 4 fields
59 * e.g.:
60 *
61 * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
62 * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
63 */
Wasim Khan8cb089e2019-11-15 09:23:35 +000064static void fdt_pcie_set_msi_map_entry_ls(void *blob, struct ls_pcie *pcie,
65 u32 devid, u32 streamid)
Minghuan Lianc1067842016-12-13 14:54:17 +080066{
67 u32 *prop;
68 u32 phandle;
69 int nodeoffset;
Hou Zhiqiang8cd3f482017-03-03 12:35:10 +080070 uint svr;
71 char *compat = NULL;
Minghuan Lianc1067842016-12-13 14:54:17 +080072
73 /* find pci controller node */
74 nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
75 pcie->dbi_res.start);
76 if (nodeoffset < 0) {
Hou Zhiqiangd553bf22016-12-13 14:54:24 +080077#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
Hou Zhiqiang8cd3f482017-03-03 12:35:10 +080078 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
79 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
Priyanka Jain2b361782017-04-27 15:08:06 +053080 svr == SVR_LS2048A || svr == SVR_LS2044A ||
81 svr == SVR_LS2081A || svr == SVR_LS2041A)
Hou Zhiqiang8cd3f482017-03-03 12:35:10 +080082 compat = "fsl,ls2088a-pcie";
83 else
84 compat = CONFIG_FSL_PCIE_COMPAT;
85 if (compat)
86 nodeoffset = fdt_node_offset_by_compat_reg(blob,
87 compat, pcie->dbi_res.start);
88#endif
Minghuan Lianc1067842016-12-13 14:54:17 +080089 if (nodeoffset < 0)
90 return;
Minghuan Lianc1067842016-12-13 14:54:17 +080091 }
92
93 /* get phandle to MSI controller */
94 prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
95 if (prop == NULL) {
96 debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
97 __func__, pcie->idx);
98 return;
99 }
100 phandle = fdt32_to_cpu(*prop);
101
102 /* set one msi-map row */
103 fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
104 fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
105 fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
106 fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
107}
108
Bharat Bhushan50514b92017-03-22 12:12:33 +0530109/*
110 * An iommu-map is a property to be added to the pci controller
111 * node. It is a table, where each entry consists of 4 fields
112 * e.g.:
113 *
114 * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
115 * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
116 */
Wasim Khan8cb089e2019-11-15 09:23:35 +0000117static void fdt_pcie_set_iommu_map_entry_ls(void *blob, struct ls_pcie *pcie,
118 u32 devid, u32 streamid)
Bharat Bhushan50514b92017-03-22 12:12:33 +0530119{
120 u32 *prop;
121 u32 iommu_map[4];
122 int nodeoffset;
123 int lenp;
Bharat Bhushan42aea352017-08-31 13:26:46 +0530124 uint svr;
125 char *compat = NULL;
Bharat Bhushan50514b92017-03-22 12:12:33 +0530126
127 /* find pci controller node */
128 nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
129 pcie->dbi_res.start);
130 if (nodeoffset < 0) {
131#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
Bharat Bhushan42aea352017-08-31 13:26:46 +0530132 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
133 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
134 svr == SVR_LS2048A || svr == SVR_LS2044A ||
135 svr == SVR_LS2081A || svr == SVR_LS2041A)
136 compat = "fsl,ls2088a-pcie";
137 else
138 compat = CONFIG_FSL_PCIE_COMPAT;
139
140 if (compat)
141 nodeoffset = fdt_node_offset_by_compat_reg(blob,
142 compat, pcie->dbi_res.start);
143#endif
Bharat Bhushan50514b92017-03-22 12:12:33 +0530144 if (nodeoffset < 0)
145 return;
Bharat Bhushan50514b92017-03-22 12:12:33 +0530146 }
147
148 /* get phandle to iommu controller */
149 prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", &lenp);
150 if (prop == NULL) {
151 debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
152 __func__, pcie->idx);
153 return;
154 }
155
156 /* set iommu-map row */
157 iommu_map[0] = cpu_to_fdt32(devid);
158 iommu_map[1] = *++prop;
159 iommu_map[2] = cpu_to_fdt32(streamid);
160 iommu_map[3] = cpu_to_fdt32(1);
161
162 if (devid == 0) {
163 fdt_setprop_inplace(blob, nodeoffset, "iommu-map",
164 iommu_map, 16);
165 } else {
166 fdt_appendprop(blob, nodeoffset, "iommu-map", iommu_map, 16);
167 }
168}
169
Wasim Khan8cb089e2019-11-15 09:23:35 +0000170static void fdt_fixup_pcie_ls(void *blob)
Minghuan Lianc1067842016-12-13 14:54:17 +0800171{
172 struct udevice *dev, *bus;
173 struct ls_pcie *pcie;
174 int streamid;
175 int index;
176 pci_dev_t bdf;
177
178 /* Scan all known buses */
179 for (pci_find_first_device(&dev);
180 dev;
181 pci_find_next_device(&dev)) {
182 for (bus = dev; device_is_on_pci_bus(bus);)
183 bus = bus->parent;
184 pcie = dev_get_priv(bus);
185
Wasim Khan9d3d2302020-01-06 12:05:59 +0000186 streamid = pcie_next_streamid(pcie->stream_id_cur, pcie->idx);
Minghuan Lianc1067842016-12-13 14:54:17 +0800187 if (streamid < 0) {
188 debug("ERROR: no stream ids free\n");
189 continue;
Wasim Khan9d3d2302020-01-06 12:05:59 +0000190 } else {
191 pcie->stream_id_cur++;
Minghuan Lianc1067842016-12-13 14:54:17 +0800192 }
193
194 index = ls_pcie_next_lut_index(pcie);
195 if (index < 0) {
196 debug("ERROR: no LUT indexes free\n");
197 continue;
198 }
199
200 /* the DT fixup must be relative to the hose first_busno */
201 bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
202 /* map PCI b.d.f to streamID in LUT */
203 ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
204 streamid);
205 /* update msi-map in device tree */
Wasim Khan8cb089e2019-11-15 09:23:35 +0000206 fdt_pcie_set_msi_map_entry_ls(blob, pcie, bdf >> 8,
207 streamid);
Bharat Bhushan50514b92017-03-22 12:12:33 +0530208 /* update iommu-map in device tree */
Wasim Khan8cb089e2019-11-15 09:23:35 +0000209 fdt_pcie_set_iommu_map_entry_ls(blob, pcie, bdf >> 8,
210 streamid);
Minghuan Lianc1067842016-12-13 14:54:17 +0800211 }
Wasim Khan70bec5c2020-01-06 12:06:00 +0000212 pcie_board_fix_fdt(blob);
Minghuan Lianc1067842016-12-13 14:54:17 +0800213}
214#endif
215
Xiaowei Bao8d7e2e82018-10-26 09:56:26 +0800216static void ft_pcie_rc_fix(void *blob, struct ls_pcie *pcie)
Minghuan Lianc1067842016-12-13 14:54:17 +0800217{
218 int off;
Hou Zhiqiang8cd3f482017-03-03 12:35:10 +0800219 uint svr;
220 char *compat = NULL;
Minghuan Lianc1067842016-12-13 14:54:17 +0800221
222 off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
223 pcie->dbi_res.start);
224 if (off < 0) {
Hou Zhiqiangd553bf22016-12-13 14:54:24 +0800225#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
Hou Zhiqiang8cd3f482017-03-03 12:35:10 +0800226 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
227 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
Priyanka Jain2b361782017-04-27 15:08:06 +0530228 svr == SVR_LS2048A || svr == SVR_LS2044A ||
229 svr == SVR_LS2081A || svr == SVR_LS2041A)
Hou Zhiqiang8cd3f482017-03-03 12:35:10 +0800230 compat = "fsl,ls2088a-pcie";
231 else
232 compat = CONFIG_FSL_PCIE_COMPAT;
233 if (compat)
234 off = fdt_node_offset_by_compat_reg(blob,
235 compat, pcie->dbi_res.start);
236#endif
Minghuan Lianc1067842016-12-13 14:54:17 +0800237 if (off < 0)
238 return;
Minghuan Lianc1067842016-12-13 14:54:17 +0800239 }
240
Xiaowei Bao8d7e2e82018-10-26 09:56:26 +0800241 if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
Minghuan Lianc1067842016-12-13 14:54:17 +0800242 fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
243 else
244 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
245}
246
Xiaowei Bao8d7e2e82018-10-26 09:56:26 +0800247static void ft_pcie_ep_fix(void *blob, struct ls_pcie *pcie)
248{
249 int off;
250
Pankaj Bansal64d85a22019-11-30 13:14:10 +0000251 off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_EP_COMPAT,
Xiaowei Bao8d7e2e82018-10-26 09:56:26 +0800252 pcie->dbi_res.start);
253 if (off < 0)
254 return;
255
256 if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
257 fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
258 else
259 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
260}
261
262static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
263{
264 ft_pcie_ep_fix(blob, pcie);
265 ft_pcie_rc_fix(blob, pcie);
266}
267
Minghuan Lianc1067842016-12-13 14:54:17 +0800268/* Fixup Kernel DT for PCIe */
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900269void ft_pci_setup_ls(void *blob, struct bd_info *bd)
Minghuan Lianc1067842016-12-13 14:54:17 +0800270{
271 struct ls_pcie *pcie;
272
273 list_for_each_entry(pcie, &ls_pcie_list, list)
274 ft_pcie_ls_setup(blob, pcie);
Hou Zhiqiang09716a7b2016-12-13 14:54:16 +0800275
Bharat Bhushan36e36be2017-03-22 12:06:30 +0530276#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
Wasim Khan8cb089e2019-11-15 09:23:35 +0000277 fdt_fixup_pcie_ls(blob);
Hou Zhiqiang09716a7b2016-12-13 14:54:16 +0800278#endif
279}
Hou Zhiqiang09716a7b2016-12-13 14:54:16 +0800280
281#else /* !CONFIG_OF_BOARD_SETUP */
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900282void ft_pci_setup_ls(void *blob, struct bd_info *bd)
Hou Zhiqiang09716a7b2016-12-13 14:54:16 +0800283{
284}
285#endif