Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Kever Yang | 52ead2f | 2016-08-12 17:58:12 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2016 Rockchip Electronics Co., Ltd |
Kever Yang | 52ead2f | 2016-08-12 17:58:12 +0800 | [diff] [blame] | 4 | */ |
Kever Yang | d1078ea | 2019-07-22 20:02:10 +0800 | [diff] [blame] | 5 | #include <common.h> |
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 6 | #include <command.h> |
Kever Yang | bbea493 | 2019-07-22 20:02:13 +0800 | [diff] [blame] | 7 | #include <dm.h> |
Simon Glass | 5e6201b | 2019-08-01 09:46:51 -0600 | [diff] [blame] | 8 | #include <env.h> |
Kever Yang | bbea493 | 2019-07-22 20:02:13 +0800 | [diff] [blame] | 9 | #include <clk.h> |
Simon Glass | a7b5130 | 2019-11-14 12:57:46 -0700 | [diff] [blame] | 10 | #include <init.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 11 | #include <malloc.h> |
Kever Yang | 1f14514 | 2019-07-09 21:58:44 +0800 | [diff] [blame] | 12 | #include <asm/armv7.h> |
Kever Yang | 52ead2f | 2016-08-12 17:58:12 +0800 | [diff] [blame] | 13 | #include <asm/io.h> |
Kever Yang | 882b2a4 | 2019-07-22 19:59:30 +0800 | [diff] [blame] | 14 | #include <asm/arch-rockchip/bootrom.h> |
Kever Yang | bbea493 | 2019-07-22 20:02:13 +0800 | [diff] [blame] | 15 | #include <asm/arch-rockchip/clock.h> |
Jagan Teki | f461f45 | 2020-07-21 12:16:38 +0530 | [diff] [blame] | 16 | #include <asm/arch-rockchip/cpu_rk3288.h> |
Jagan Teki | 783acfd | 2020-01-09 14:22:17 +0530 | [diff] [blame] | 17 | #include <asm/arch-rockchip/cru.h> |
Kever Yang | 9fbe17c | 2019-03-28 11:01:23 +0800 | [diff] [blame] | 18 | #include <asm/arch-rockchip/hardware.h> |
Kever Yang | 655f2a7 | 2019-03-29 09:09:03 +0800 | [diff] [blame] | 19 | #include <asm/arch-rockchip/grf_rk3288.h> |
Kever Yang | 66dd594 | 2019-07-22 19:59:26 +0800 | [diff] [blame] | 20 | #include <asm/arch-rockchip/pmu_rk3288.h> |
Kever Yang | d1078ea | 2019-07-22 20:02:10 +0800 | [diff] [blame] | 21 | #include <asm/arch-rockchip/qos_rk3288.h> |
Kever Yang | e47db83 | 2019-11-15 11:04:33 +0800 | [diff] [blame] | 22 | #include <asm/arch-rockchip/sdram.h> |
Simon Glass | d66c5f7 | 2020-02-03 07:36:15 -0700 | [diff] [blame] | 23 | #include <linux/err.h> |
Kever Yang | 66dd594 | 2019-07-22 19:59:26 +0800 | [diff] [blame] | 24 | |
| 25 | DECLARE_GLOBAL_DATA_PTR; |
Kever Yang | 52ead2f | 2016-08-12 17:58:12 +0800 | [diff] [blame] | 26 | |
Kever Yang | 655f2a7 | 2019-03-29 09:09:03 +0800 | [diff] [blame] | 27 | #define GRF_BASE 0xff770000 |
Kever Yang | 52ead2f | 2016-08-12 17:58:12 +0800 | [diff] [blame] | 28 | |
Kever Yang | 882b2a4 | 2019-07-22 19:59:30 +0800 | [diff] [blame] | 29 | const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { |
Levin Du | 27df507 | 2019-10-17 15:22:38 +0800 | [diff] [blame] | 30 | [BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000", |
| 31 | [BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000", |
Kever Yang | 882b2a4 | 2019-07-22 19:59:30 +0800 | [diff] [blame] | 32 | }; |
| 33 | |
Kever Yang | 1f14514 | 2019-07-09 21:58:44 +0800 | [diff] [blame] | 34 | #ifdef CONFIG_SPL_BUILD |
| 35 | static void configure_l2ctlr(void) |
| 36 | { |
| 37 | u32 l2ctlr; |
| 38 | |
| 39 | l2ctlr = read_l2ctlr(); |
| 40 | l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ |
| 41 | |
| 42 | /* |
| 43 | * Data RAM write latency: 2 cycles |
| 44 | * Data RAM read latency: 2 cycles |
| 45 | * Data RAM setup latency: 1 cycle |
| 46 | * Tag RAM write latency: 1 cycle |
| 47 | * Tag RAM read latency: 1 cycle |
| 48 | * Tag RAM setup latency: 1 cycle |
| 49 | */ |
| 50 | l2ctlr |= (1 << 3 | 1 << 0); |
| 51 | write_l2ctlr(l2ctlr); |
| 52 | } |
| 53 | #endif |
| 54 | |
Kever Yang | d1078ea | 2019-07-22 20:02:10 +0800 | [diff] [blame] | 55 | int rk3288_qos_init(void) |
| 56 | { |
| 57 | int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT; |
| 58 | /* set vop qos to higher priority */ |
| 59 | writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS); |
| 60 | writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS); |
| 61 | |
| 62 | if (!fdt_node_check_compatible(gd->fdt_blob, 0, |
| 63 | "rockchip,rk3288-tinker")) { |
| 64 | /* set isp qos to higher priority */ |
| 65 | writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS); |
| 66 | writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS); |
| 67 | writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS); |
| 68 | } |
| 69 | |
| 70 | return 0; |
| 71 | } |
| 72 | |
Kever Yang | 52ead2f | 2016-08-12 17:58:12 +0800 | [diff] [blame] | 73 | int arch_cpu_init(void) |
| 74 | { |
Kever Yang | a3eff93 | 2019-07-09 21:58:43 +0800 | [diff] [blame] | 75 | #ifdef CONFIG_SPL_BUILD |
| 76 | configure_l2ctlr(); |
| 77 | #else |
Kever Yang | 52ead2f | 2016-08-12 17:58:12 +0800 | [diff] [blame] | 78 | /* We do some SoC one time setting here. */ |
Kever Yang | 655f2a7 | 2019-03-29 09:09:03 +0800 | [diff] [blame] | 79 | struct rk3288_grf * const grf = (void *)GRF_BASE; |
Kever Yang | 52ead2f | 2016-08-12 17:58:12 +0800 | [diff] [blame] | 80 | |
| 81 | /* Use rkpwm by default */ |
Kever Yang | 655f2a7 | 2019-03-29 09:09:03 +0800 | [diff] [blame] | 82 | rk_setreg(&grf->soc_con2, 1 << 0); |
Kever Yang | d1078ea | 2019-07-22 20:02:10 +0800 | [diff] [blame] | 83 | |
| 84 | /* |
| 85 | * Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is |
| 86 | * cleared |
| 87 | */ |
| 88 | rk_clrreg(&grf->soc_con0, 1 << 12); |
| 89 | |
| 90 | rk3288_qos_init(); |
Kever Yang | a3eff93 | 2019-07-09 21:58:43 +0800 | [diff] [blame] | 91 | #endif |
Kever Yang | 52ead2f | 2016-08-12 17:58:12 +0800 | [diff] [blame] | 92 | |
| 93 | return 0; |
| 94 | } |
Kever Yang | abfed9b | 2019-03-29 09:09:04 +0800 | [diff] [blame] | 95 | |
| 96 | #ifdef CONFIG_DEBUG_UART_BOARD_INIT |
| 97 | void board_debug_uart_init(void) |
| 98 | { |
| 99 | /* Enable early UART on the RK3288 */ |
| 100 | struct rk3288_grf * const grf = (void *)GRF_BASE; |
| 101 | |
| 102 | rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | |
| 103 | GPIO7C6_MASK << GPIO7C6_SHIFT, |
| 104 | GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | |
| 105 | GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); |
| 106 | } |
| 107 | #endif |
Kever Yang | bbea493 | 2019-07-22 20:02:13 +0800 | [diff] [blame] | 108 | |
Kever Yang | b7da271 | 2019-07-22 20:02:14 +0800 | [diff] [blame] | 109 | __weak int rk3288_board_late_init(void) |
| 110 | { |
| 111 | return 0; |
| 112 | } |
| 113 | |
| 114 | int rk_board_late_init(void) |
| 115 | { |
Kever Yang | b7da271 | 2019-07-22 20:02:14 +0800 | [diff] [blame] | 116 | return rk3288_board_late_init(); |
| 117 | } |
| 118 | |
Jagan Teki | f461f45 | 2020-07-21 12:16:38 +0530 | [diff] [blame] | 119 | static int ft_rk3288w_setup(void *blob) |
| 120 | { |
| 121 | const char *path; |
| 122 | int offs, ret; |
| 123 | |
| 124 | path = "/clock-controller@ff760000"; |
| 125 | offs = fdt_path_offset(blob, path); |
| 126 | if (offs < 0) { |
| 127 | debug("failed to found fdt path %s\n", path); |
| 128 | return offs; |
| 129 | } |
| 130 | |
| 131 | ret = fdt_setprop_string(blob, offs, "compatible", "rockchip,rk3288w-cru"); |
| 132 | if (ret) { |
| 133 | printf("failed to set rk3288w-cru compatible (ret=%d)\n", ret); |
| 134 | return ret; |
| 135 | } |
| 136 | |
| 137 | return ret; |
| 138 | } |
| 139 | |
| 140 | int ft_board_setup(void *blob, struct bd_info *bd) |
| 141 | { |
| 142 | if (soc_is_rk3288w()) |
| 143 | return ft_rk3288w_setup(blob); |
| 144 | |
| 145 | return 0; |
| 146 | } |
| 147 | |
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 148 | static int do_clock(struct cmd_tbl *cmdtp, int flag, int argc, |
| 149 | char *const argv[]) |
Kever Yang | bbea493 | 2019-07-22 20:02:13 +0800 | [diff] [blame] | 150 | { |
| 151 | static const struct { |
| 152 | char *name; |
| 153 | int id; |
| 154 | } clks[] = { |
| 155 | { "osc", CLK_OSC }, |
| 156 | { "apll", CLK_ARM }, |
| 157 | { "dpll", CLK_DDR }, |
| 158 | { "cpll", CLK_CODEC }, |
| 159 | { "gpll", CLK_GENERAL }, |
| 160 | #ifdef CONFIG_ROCKCHIP_RK3036 |
| 161 | { "mpll", CLK_NEW }, |
| 162 | #else |
| 163 | { "npll", CLK_NEW }, |
| 164 | #endif |
| 165 | }; |
| 166 | int ret, i; |
| 167 | struct udevice *dev; |
| 168 | |
| 169 | ret = rockchip_get_clk(&dev); |
| 170 | if (ret) { |
| 171 | printf("clk-uclass not found\n"); |
| 172 | return 0; |
| 173 | } |
| 174 | |
| 175 | for (i = 0; i < ARRAY_SIZE(clks); i++) { |
| 176 | struct clk clk; |
| 177 | ulong rate; |
| 178 | |
| 179 | clk.id = clks[i].id; |
| 180 | ret = clk_request(dev, &clk); |
| 181 | if (ret < 0) |
| 182 | continue; |
| 183 | |
| 184 | rate = clk_get_rate(&clk); |
| 185 | printf("%s: %lu\n", clks[i].name, rate); |
| 186 | |
| 187 | clk_free(&clk); |
| 188 | } |
| 189 | |
| 190 | return 0; |
| 191 | } |
| 192 | |
| 193 | U_BOOT_CMD( |
| 194 | clock, 2, 1, do_clock, |
| 195 | "display information about clocks", |
| 196 | "" |
| 197 | ); |