Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 5792f4b6a5f7540a41cf391b5a1d55633c3fa870 / . / drivers / clk / sunxi / clk_a64.c
blob: d96cb1aac1c9d991abb8bce71fb8955177a7d9e1 [file] [log] [blame]
Jagan Teki1d150b42018-12-22 21:32:49 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
11#include <asm/arch/ccu.h>
12#include <dt-bindings/clock/sun50i-a64-ccu.h>
Jagan Teki7f6c2a82019-01-18 22:18:13 +0530[diff] [blame]13#include <dt-bindings/reset/sun50i-a64-ccu.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]14#include <linux/bitops.h>
Jagan Teki1d150b42018-12-22 21:32:49 +0530[diff] [blame]15
16static const struct ccu_clk_gate a64_gates[] = {
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]17 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
18 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
19 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
Jagan Teki836631b2019-02-28 00:26:57 +0530[diff] [blame]20 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]21 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
22 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
Jagan Teki1d150b42018-12-22 21:32:49 +0530[diff] [blame]23 [CLK_BUS_OTG] = GATE(0x060, BIT(23)),
24 [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)),
25 [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)),
26 [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
27 [CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),
28
Jagan Teki8cf08ea2018-12-30 21:29:24 +0530[diff] [blame]29 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
30 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
31 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
32 [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
33 [CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
34
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]35 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
36 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
37
Jagan Teki1d150b42018-12-22 21:32:49 +0530[diff] [blame]38 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
39 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
40 [CLK_USB_HSIC] = GATE(0x0cc, BIT(10)),
41 [CLK_USB_HSIC_12M] = GATE(0x0cc, BIT(11)),
42 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
43 [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
44};
45
Jagan Teki7f6c2a82019-01-18 22:18:13 +0530[diff] [blame]46static const struct ccu_reset a64_resets[] = {
47 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
48 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
49 [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
50
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]51 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
52 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
53 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
Jagan Teki836631b2019-02-28 00:26:57 +0530[diff] [blame]54 [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]55 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
56 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
Jagan Teki7f6c2a82019-01-18 22:18:13 +0530[diff] [blame]57 [RST_BUS_OTG] = RESET(0x2c0, BIT(23)),
58 [RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)),
59 [RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)),
60 [RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)),
61 [RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)),
Jagan Tekib490aa52018-12-30 21:37:31 +0530[diff] [blame]62
63 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
64 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
65 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
66 [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
67 [RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
Jagan Teki7f6c2a82019-01-18 22:18:13 +0530[diff] [blame]68};
69
Jagan Teki1d150b42018-12-22 21:32:49 +0530[diff] [blame]70static const struct ccu_desc a64_ccu_desc = {
71 .gates = a64_gates,
Jagan Teki7f6c2a82019-01-18 22:18:13 +0530[diff] [blame]72 .resets = a64_resets,
Jagan Teki1d150b42018-12-22 21:32:49 +0530[diff] [blame]73};
74
Jagan Teki7f6c2a82019-01-18 22:18:13 +0530[diff] [blame]75static int a64_clk_bind(struct udevice *dev)
76{
77 return sunxi_reset_bind(dev, ARRAY_SIZE(a64_resets));
78}
79
Jagan Teki1d150b42018-12-22 21:32:49 +0530[diff] [blame]80static const struct udevice_id a64_ccu_ids[] = {
81 { .compatible = "allwinner,sun50i-a64-ccu",
82 .data = (ulong)&a64_ccu_desc },
83 { }
84};
85
86U_BOOT_DRIVER(clk_sun50i_a64) = {
87 .name = "sun50i_a64_ccu",
88 .id = UCLASS_CLK,
89 .of_match = a64_ccu_ids,
90 .priv_auto_alloc_size = sizeof(struct ccu_priv),
91 .ops = &sunxi_clk_ops,
92 .probe = sunxi_clk_probe,
Jagan Teki7f6c2a82019-01-18 22:18:13 +0530[diff] [blame]93 .bind = a64_clk_bind,
Jagan Teki1d150b42018-12-22 21:32:49 +0530[diff] [blame]94};