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git01.mediatek.com / filogic / uboot / 5792f4b6a5f7540a41cf391b5a1d55633c3fa870 / . / drivers / clk / sunxi / clk_a10.c
blob: 67507c5ab1da629356d410bc29db1a63be3f2d8f [file] [log] [blame]
Jagan Tekib38f7af2018-08-02 16:52:37 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
11#include <asm/arch/ccu.h>
12#include <dt-bindings/clock/sun4i-a10-ccu.h>
13#include <dt-bindings/reset/sun4i-a10-ccu.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]14#include <linux/bitops.h>
Jagan Tekib38f7af2018-08-02 16:52:37 +0530[diff] [blame]15
16static struct ccu_clk_gate a10_gates[] = {
17 [CLK_AHB_OTG] = GATE(0x060, BIT(0)),
18 [CLK_AHB_EHCI0] = GATE(0x060, BIT(1)),
19 [CLK_AHB_OHCI0] = GATE(0x060, BIT(2)),
20 [CLK_AHB_EHCI1] = GATE(0x060, BIT(3)),
21 [CLK_AHB_OHCI1] = GATE(0x060, BIT(4)),
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]22 [CLK_AHB_MMC0] = GATE(0x060, BIT(8)),
23 [CLK_AHB_MMC1] = GATE(0x060, BIT(9)),
24 [CLK_AHB_MMC2] = GATE(0x060, BIT(10)),
25 [CLK_AHB_MMC3] = GATE(0x060, BIT(11)),
Jagan Tekif4b29f42019-02-28 00:26:49 +0530[diff] [blame]26 [CLK_AHB_EMAC] = GATE(0x060, BIT(17)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]27 [CLK_AHB_SPI0] = GATE(0x060, BIT(20)),
28 [CLK_AHB_SPI1] = GATE(0x060, BIT(21)),
29 [CLK_AHB_SPI2] = GATE(0x060, BIT(22)),
30 [CLK_AHB_SPI3] = GATE(0x060, BIT(23)),
Jagan Tekib38f7af2018-08-02 16:52:37 +0530[diff] [blame]31
Jagan Teki53698b22019-03-28 13:46:11 +0530[diff] [blame]32 [CLK_AHB_GMAC] = GATE(0x064, BIT(17)),
33
Jagan Teki8cf08ea2018-12-30 21:29:24 +0530[diff] [blame]34 [CLK_APB1_UART0] = GATE(0x06c, BIT(16)),
35 [CLK_APB1_UART1] = GATE(0x06c, BIT(17)),
36 [CLK_APB1_UART2] = GATE(0x06c, BIT(18)),
37 [CLK_APB1_UART3] = GATE(0x06c, BIT(19)),
38 [CLK_APB1_UART4] = GATE(0x06c, BIT(20)),
39 [CLK_APB1_UART5] = GATE(0x06c, BIT(21)),
40 [CLK_APB1_UART6] = GATE(0x06c, BIT(22)),
41 [CLK_APB1_UART7] = GATE(0x06c, BIT(23)),
42
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]43 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
44 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
45 [CLK_SPI2] = GATE(0x0a8, BIT(31)),
46
Jagan Tekib38f7af2018-08-02 16:52:37 +0530[diff] [blame]47 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(6)),
48 [CLK_USB_OHCI1] = GATE(0x0cc, BIT(7)),
49 [CLK_USB_PHY] = GATE(0x0cc, BIT(8)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]50
51 [CLK_SPI3] = GATE(0x0d4, BIT(31)),
Jagan Tekib38f7af2018-08-02 16:52:37 +0530[diff] [blame]52};
53
54static struct ccu_reset a10_resets[] = {
55 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
56 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
57 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
58};
59
60static const struct ccu_desc a10_ccu_desc = {
61 .gates = a10_gates,
62 .resets = a10_resets,
63};
64
65static int a10_clk_bind(struct udevice *dev)
66{
67 return sunxi_reset_bind(dev, ARRAY_SIZE(a10_resets));
68}
69
70static const struct udevice_id a10_ccu_ids[] = {
71 { .compatible = "allwinner,sun4i-a10-ccu",
72 .data = (ulong)&a10_ccu_desc },
73 { .compatible = "allwinner,sun7i-a20-ccu",
74 .data = (ulong)&a10_ccu_desc },
75 { }
76};
77
78U_BOOT_DRIVER(clk_sun4i_a10) = {
79 .name = "sun4i_a10_ccu",
80 .id = UCLASS_CLK,
81 .of_match = a10_ccu_ids,
82 .priv_auto_alloc_size = sizeof(struct ccu_priv),
83 .ops = &sunxi_clk_ops,
84 .probe = sunxi_clk_probe,
85 .bind = a10_clk_bind,
86};