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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stephen Warrena844b012014-03-25 11:39:33 -06002/*
3 * (C) Copyright 2014
4 * NVIDIA Corporation <www.nvidia.com>
Stephen Warrena844b012014-03-25 11:39:33 -06005 */
6
7#include <common.h>
Simon Glassb3d2ed32017-07-25 08:30:12 -06008#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -06009#include <log.h>
Simon Glassbdd5f812023-09-14 18:21:46 -060010#include <linux/printk.h>
Thierry Reding0f4c83b2014-12-09 22:25:21 -070011#include <power/as3722.h>
Simon Glassb3d2ed32017-07-25 08:30:12 -060012#include <power/pmic.h>
Thierry Reding0f4c83b2014-12-09 22:25:21 -070013
Stephen Warrenfa2a1232014-04-22 14:37:55 -060014#include <asm/arch/gpio.h>
Stephen Warrena844b012014-03-25 11:39:33 -060015#include <asm/arch/pinmux.h>
Thierry Reding0f4c83b2014-12-09 22:25:21 -070016
Stephen Warrena844b012014-03-25 11:39:33 -060017#include "pinmux-config-jetson-tk1.h"
18
19/*
20 * Routine: pinmux_init
21 * Description: Do individual peripheral pinmux configs
22 */
23void pinmux_init(void)
24{
Stephen Warren2516bef2015-02-18 13:27:04 -070025 pinmux_clear_tristate_input_clamping();
Stephen Warrenf16f64f2014-04-22 14:37:56 -060026
Stephen Warrenfa2a1232014-04-22 14:37:55 -060027 gpio_config_table(jetson_tk1_gpio_inits,
28 ARRAY_SIZE(jetson_tk1_gpio_inits));
29
Stephen Warrena844b012014-03-25 11:39:33 -060030 pinmux_config_pingrp_table(jetson_tk1_pingrps,
31 ARRAY_SIZE(jetson_tk1_pingrps));
32
33 pinmux_config_drvgrp_table(jetson_tk1_drvgrps,
34 ARRAY_SIZE(jetson_tk1_drvgrps));
Stephen Warren8e7c1be2016-04-21 16:03:37 -060035
36 pinmux_config_mipipadctrlgrp_table(jetson_tk1_mipipadctrlgrps,
37 ARRAY_SIZE(jetson_tk1_mipipadctrlgrps));
Stephen Warrena844b012014-03-25 11:39:33 -060038}
Thierry Reding0f4c83b2014-12-09 22:25:21 -070039
40#ifdef CONFIG_PCI_TEGRA
Simon Glassb3d2ed32017-07-25 08:30:12 -060041/* TODO: Convert to driver model */
42static int as3722_sd_enable(struct udevice *pmic, unsigned int sd)
Thierry Reding0f4c83b2014-12-09 22:25:21 -070043{
Thierry Reding0f4c83b2014-12-09 22:25:21 -070044 int err;
45
Simon Glassb3d2ed32017-07-25 08:30:12 -060046 if (sd > 6)
47 return -EINVAL;
48
49 err = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd);
Thierry Reding0f4c83b2014-12-09 22:25:21 -070050 if (err) {
Masahiro Yamada81e10422017-09-16 14:10:41 +090051 pr_err("failed to update SD control register: %d", err);
Thierry Reding0f4c83b2014-12-09 22:25:21 -070052 return err;
53 }
54
Simon Glassb3d2ed32017-07-25 08:30:12 -060055 return 0;
56}
57
58int tegra_pcie_board_init(void)
59{
60 struct udevice *dev;
61 int ret;
62
63 ret = uclass_get_device_by_driver(UCLASS_PMIC,
Simon Glass65130cd2020-12-28 20:34:56 -070064 DM_DRIVER_GET(pmic_as3722), &dev);
Simon Glassb3d2ed32017-07-25 08:30:12 -060065 if (ret) {
66 debug("%s: Failed to find PMIC\n", __func__);
67 return ret;
Thierry Reding0f4c83b2014-12-09 22:25:21 -070068 }
69
Simon Glassb3d2ed32017-07-25 08:30:12 -060070 ret = as3722_sd_enable(dev, 4);
71 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +090072 pr_err("failed to enable SD4: %d\n", ret);
Simon Glassb3d2ed32017-07-25 08:30:12 -060073 return ret;
74 }
75
76 ret = as3722_sd_set_voltage(dev, 4, 0x24);
77 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +090078 pr_err("failed to set SD4 voltage: %d\n", ret);
Simon Glassb3d2ed32017-07-25 08:30:12 -060079 return ret;
Thierry Reding0f4c83b2014-12-09 22:25:21 -070080 }
81
Thierry Reding0f4c83b2014-12-09 22:25:21 -070082 return 0;
83}
Thierry Reding0f4c83b2014-12-09 22:25:21 -070084#endif /* PCI */