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git01.mediatek.com / filogic / uboot / 571bce1e65654d0adfe34be802c2fb415ab0debf / . / cpu / mcf52x2 / start.S
blob: 686e2a533302af0e69feae9603c7d835625f4932 [file] [log] [blame]
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]1/*
2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <config.h>
25#include "version.h"
26
27#ifndef CONFIG_IDENT_STRING
28#define CONFIG_IDENT_STRING ""
29#endif
30
31
32#define _START _start
33#define _FAULT _fault
34
35
36#define SAVE_ALL \
37 move.w #0x2700,%sr; /* disable intrs */ \
38 subl #60,%sp; /* space for 15 regs */ \
39 moveml %d0-%d7/%a0-%a6,%sp@; \
40
41#define RESTORE_ALL \
42 moveml %sp@,%d0-%d7/%a0-%a6; \
43 addl #60,%sp; /* space for 15 regs */ \
44 rte
45
46/* If we come from a pre-loader we don't need an initial exception
47 * table.
48 */
49#if !defined(CONFIG_MONITOR_IS_IN_RAM)
50
51.text
52/*
53 * Vector table. This is used for initial platform startup.
54 * These vectors are to catch any un-intended traps.
55 */
56_vectors:
57
Wolfgang Denkb4b1c462006-06-10 19:27:47 +0200[diff] [blame]58.long 0x00000000 /* Flash offset is 0 until we setup CS0 */
59#if defined(CONFIG_R5200)
60.long 0x400
61#elif defined(CONFIG_M5282)
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]62.long _start - TEXT_BASE
Zachary P. Landau0bba8622006-01-26 17:35:56 -0500[diff] [blame]63#else
Wolfgang Denkb4b1c462006-06-10 19:27:47 +0200[diff] [blame]64.long _START
Zachary P. Landau0bba8622006-01-26 17:35:56 -0500[diff] [blame]65#endif
Wolfgang Denkb4b1c462006-06-10 19:27:47 +0200[diff] [blame]66
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]67.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
68.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
69.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
70.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
71.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
72.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
73.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
74.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
75
76.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
77.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
78.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
79.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
80.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
81.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
82.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
83.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
84
85.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
86.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
87.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
88.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
89.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
90.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
91.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
92.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
93
94.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
95.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
96.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
97.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
98.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
99.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
100.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
101.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
102
103#endif
104
105 .text
106
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]107
108#if defined(CFG_INT_FLASH_BASE) && \
109 (defined(CONFIG_M5282) || defined(CONFIG_M5281))
110 #if (TEXT_BASE == CFG_INT_FLASH_BASE)
111 .long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */
112 .long 0xFFFFFFFF /* all sectors protected */
113 .long 0x00000000 /* supervisor/User restriction */
114 .long 0x00000000 /* programm/data space restriction */
115 .long 0x00000000 /* Flash security */
116 #endif
117#endif
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]118 .globl _start
119_start:
120 nop
121 nop
122 move.w #0x2700,%sr
123
TsiChungLiew34674692007-08-16 13:20:50 -0500[diff] [blame]124#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]125 move.l #(CFG_MBAR + 1), %d0 /* set MBAR address + valid flag */
126 move.c %d0, %MBAR
127
stroese53395a22004-12-16 18:09:49 +0000[diff] [blame]128 /*** The 5249 has MBAR2 as well ***/
129#ifdef CFG_MBAR2
130 move.l #(CFG_MBAR2 + 1), %d0 /* Get MBAR2 address */
131 movec %d0, #0xc0e /* Set MBAR2 */
132#endif
133
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]134 move.l #(CFG_INIT_RAM_ADDR + 1), %d0
135 movec %d0, %RAMBAR0
TsiChungLiew34674692007-08-16 13:20:50 -0500[diff] [blame]136#endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]137
Wolfgang Denkb4b1c462006-06-10 19:27:47 +0200[diff] [blame]138#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]139 /* Initialize IPSBAR */
140 move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
141 move.l %d0, 0x40000000
142
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]143 /* Initialize RAMBAR1: locate SRAM and validate it */
144 move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
145 movec %d0, %RAMBAR1
146
Bartlomiej Sieka8ff81c62006-12-20 00:27:32 +0100[diff] [blame]147#if defined(CONFIG_M5282)
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]148#if (TEXT_BASE == CFG_INT_FLASH_BASE)
149 /* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */
150
151 move.l #(_flashbar_setup-CFG_INT_FLASH_BASE), %a0
152 move.l #(_flashbar_setup_end-CFG_INT_FLASH_BASE), %a1
153 move.l #(CFG_INIT_RAM_ADDR), %a2
154_copy_flash:
155 move.l (%a0)+, (%a2)+
156 cmp.l %a0, %a1
157 bgt.s _copy_flash
158 jmp CFG_INIT_RAM_ADDR
159
160_flashbar_setup:
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]161 /* Initialize FLASHBAR: locate internal Flash and validate it */
TsiChungLiew8cd73be2007-08-15 19:21:21 -0500[diff] [blame]162 move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]163 movec %d0, %RAMBAR0
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]164 jmp _after_flashbar_copy.L /* Force jump to absolute address */
165_flashbar_setup_end:
166 nop
167_after_flashbar_copy:
168#else
169 /* Setup code to initialize FLASHBAR, if start from external Memory */
TsiChungLiew8cd73be2007-08-15 19:21:21 -0500[diff] [blame]170 move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]171 movec %d0, %RAMBAR0
172#endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]173
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]174#endif
Wolfgang Denk5b1657d2006-09-04 01:03:57 +0200[diff] [blame]175#endif
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]176 /* if we come from a pre-loader we have no exception table and
177 * therefore no VBR to set
178 */
179#if !defined(CONFIG_MONITOR_IS_IN_RAM)
180 move.l #CFG_FLASH_BASE, %d0
181 movec %d0, %VBR
Marian Balakowiczc20d87d2006-05-09 11:51:51 +0200[diff] [blame]182#endif
183
184#ifdef CONFIG_R5200
Zachary P. Landau0bba8622006-01-26 17:35:56 -0500[diff] [blame]185 move.l #(_flash_setup-CFG_FLASH_BASE), %a0
186 move.l #(_flash_setup_end-CFG_FLASH_BASE), %a1
187 move.l #(CFG_INIT_RAM_ADDR), %a2
188_copy_flash:
189 move.l (%a0)+, (%a2)+
190 cmp.l %a0, %a1
191 bgt.s _copy_flash
Zachary P. Landau0bba8622006-01-26 17:35:56 -0500[diff] [blame]192 jmp CFG_INIT_RAM_ADDR
193_after_flash_copy:
194#endif
195
196#if 0
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]197 /* invalidate and disable cache */
198 move.l #0x01000000, %d0 /* Invalidate cache cmd */
199 movec %d0, %CACR /* Invalidate cache */
200 move.l #0, %d0
201 movec %d0, %ACR0
202 movec %d0, %ACR1
Zachary P. Landau0bba8622006-01-26 17:35:56 -0500[diff] [blame]203#endif
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]204
205 /* set stackpointer to end of internal ram to get some stackspace for the first c-code */
206 move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
207 clr.l %sp@-
208
209 move.l #__got_start, %a5 /* put relocation table address to a5 */
210
211 bsr cpu_init_f /* run low-level CPU init code (from flash) */
212 bsr board_init_f /* run low-level board init code (from flash) */
213
Marian Balakowiczc20d87d2006-05-09 11:51:51 +0200[diff] [blame]214 /* board_init_f() does not return */
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]215
216/*------------------------------------------------------------------------------*/
217
Marian Balakowiczc20d87d2006-05-09 11:51:51 +0200[diff] [blame]218#ifdef CONFIG_R5200
Zachary P. Landau0bba8622006-01-26 17:35:56 -0500[diff] [blame]219_flash_setup:
Marian Balakowiczc20d87d2006-05-09 11:51:51 +0200[diff] [blame]220 /* CSAR0 */
221 move.l #((CFG_FLASH_BASE & 0xffff0000) >> 16), %d0
Zachary P. Landau0bba8622006-01-26 17:35:56 -0500[diff] [blame]222 move.w %d0, 0x40000080
Marian Balakowiczc20d87d2006-05-09 11:51:51 +0200[diff] [blame]223
224 /* CSCR0 */
225 move.l #0x2180, %d0 /* 8 wait states, 16bit port, auto ack, */
Zachary P. Landau0bba8622006-01-26 17:35:56 -0500[diff] [blame]226 move.w %d0, 0x4000008A
Marian Balakowiczc20d87d2006-05-09 11:51:51 +0200[diff] [blame]227
228 /* CSMR0 */
229 move.l #0x001f0001, %d0 /* 2 MB, valid */
Zachary P. Landau0bba8622006-01-26 17:35:56 -0500[diff] [blame]230 move.l %d0, 0x40000084
Marian Balakowiczc20d87d2006-05-09 11:51:51 +0200[diff] [blame]231
Zachary P. Landau0bba8622006-01-26 17:35:56 -0500[diff] [blame]232 jmp _after_flash_copy.L
233_flash_setup_end:
234#endif
235
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]236/*
237 * void relocate_code (addr_sp, gd, addr_moni)
238 *
239 * This "function" does not return, instead it continues in RAM
240 * after relocating the monitor code.
241 *
242 * r3 = dest
243 * r4 = src
244 * r5 = length in bytes
245 * r6 = cachelinesize
246 */
247 .globl relocate_code
248relocate_code:
249 link.w %a6,#0
250 move.l 8(%a6), %sp /* set new stack pointer */
251
252 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
253 move.l 16(%a6), %a0 /* Save copy of Destination Address */
254
255 move.l #CFG_MONITOR_BASE, %a1
256 move.l #__init_end, %a2
257 move.l %a0, %a3
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]258 /* copy the code to RAM */
2591:
260 move.l (%a1)+, (%a3)+
261 cmp.l %a1,%a2
262 bgt.s 1b
263
264/*
265 * We are done. Do not return, instead branch to second part of board
266 * initialization, now running from RAM.
267 */
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]268 move.l %a0, %a1
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]269 add.l #(in_ram - CFG_MONITOR_BASE), %a1
270 jmp (%a1)
271
272in_ram:
273
274clear_bss:
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]275 /*
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]276 * Now clear BSS segment
277 */
278 move.l %a0, %a1
279 add.l #(_sbss - CFG_MONITOR_BASE),%a1
280 move.l %a0, %d1
281 add.l #(_ebss - CFG_MONITOR_BASE),%d1
2826:
283 clr.l (%a1)+
284 cmp.l %a1,%d1
285 bgt.s 6b
286
287 /*
288 * fix got table in RAM
289 */
290 move.l %a0, %a1
291 add.l #(__got_start - CFG_MONITOR_BASE),%a1
292 move.l %a1,%a5 /* * fix got pointer register a5 */
293
294 move.l %a0, %a2
295 add.l #(__got_end - CFG_MONITOR_BASE),%a2
296
2977:
298 move.l (%a1),%d1
299 sub.l #_start,%d1
300 add.l %a0,%d1
301 move.l %d1,(%a1)+
302 cmp.l %a2, %a1
303 bne 7b
304
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]305#if defined(CONFIG_M5281) || defined(CONFIG_M5282)
306 /* patch the 3 accesspoints to 3 ichache_state */
307 /* quick and dirty */
308
309 move.l %a0,%d1
310 add.l #(icache_state - CFG_MONITOR_BASE),%d1
311 move.l %a0,%a1
312 add.l #(icache_state_access_1+2 - CFG_MONITOR_BASE),%a1
313 move.l %d1,(%a1)
314 move.l %a0,%a1
315 add.l #(icache_state_access_2+2 - CFG_MONITOR_BASE),%a1
316 move.l %d1,(%a1)
317 move.l %a0,%a1
318 add.l #(icache_state_access_3+2 - CFG_MONITOR_BASE),%a1
319 move.l %d1,(%a1)
320#endif
321
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]322 /* calculate relative jump to board_init_r in ram */
323 move.l %a0, %a1
324 add.l #(board_init_r - CFG_MONITOR_BASE), %a1
325
326 /* set parameters for board_init_r */
327 move.l %a0,-(%sp) /* dest_addr */
328 move.l %d0,-(%sp) /* gd */
TsiChungLiew8cd73be2007-08-15 19:21:21 -0500[diff] [blame]329#if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \
330 defined(CFG_HALT_BEFOR_RAM_JUMP)
331 halt
332#endif
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]333 jsr (%a1)
334
335/*------------------------------------------------------------------------------*/
336/* exception code */
337 .globl _fault
338_fault:
339 jmp _fault
340
341 .globl _exc_handler
342_exc_handler:
343 SAVE_ALL
344 movel %sp,%sp@-
345 bsr exc_handler
346 addql #4,%sp
347 RESTORE_ALL
348
349 .globl _int_handler
350_int_handler:
351 SAVE_ALL
352 movel %sp,%sp@-
353 bsr int_handler
354 addql #4,%sp
355 RESTORE_ALL
356
357/*------------------------------------------------------------------------------*/
358/* cache functions */
TsiChungLiew8cd73be2007-08-15 19:21:21 -0500[diff] [blame]359#ifdef CONFIG_M5271
360 .globl icache_enable
361icache_enable:
362 move.l #0x01000000, %d0 /* Invalidate cache cmd */
363 movec %d0, %CACR /* Invalidate cache */
364 move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
365 movec %d0, %ACR0 /* Enable cache */
366
367 move.l #0x80000200, %d0 /* Setup cache mask */
368 movec %d0, %CACR /* Enable cache */
369 nop
370
371 move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
372 moveq #1, %d0
373 move.l %d0, (%a1)
374 rts
375#endif
376
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]377#ifdef CONFIG_M5272
378 .globl icache_enable
379icache_enable:
380 move.l #0x01000000, %d0 /* Invalidate cache cmd */
381 movec %d0, %CACR /* Invalidate cache */
382 move.l #0x0000c000, %d0 /* Setup cache mask */
383 movec %d0, %ACR0 /* Enable cache */
384 move.l #0xff00c000, %d0 /* Setup cache mask */
385 movec %d0, %ACR1 /* Enable cache */
386 move.l #0x80000100, %d0 /* Setup cache mask */
387 movec %d0, %CACR /* Enable cache */
388 moveq #1, %d0
389 move.l %d0, icache_state
390 rts
391#endif
392
393#ifdef CONFIG_M5282
394 .globl icache_enable
395icache_enable:
396 move.l #0x01000000, %d0 /* Invalidate cache cmd */
397 movec %d0, %CACR /* Invalidate cache */
398 move.l #0x0000c000, %d0 /* Setup cache mask */
399 movec %d0, %ACR0 /* Enable cache */
400 move.l #0xff00c000, %d0 /* Setup cache mask */
401 movec %d0, %ACR1 /* Enable cache */
402 move.l #0x80400100, %d0 /* Setup cache mask, data cache disabel*/
403 movec %d0, %CACR /* Enable cache */
404 moveq #1, %d0
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]405icache_state_access_1:
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]406 move.l %d0, icache_state
407 rts
408#endif
409
TsiChungLiew34674692007-08-16 13:20:50 -0500[diff] [blame]410#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
stroese53395a22004-12-16 18:09:49 +0000[diff] [blame]411 .globl icache_enable
412icache_enable:
413 /*
414 * Note: The 5249 Documentation doesn't give a bit position for CINV!
415 * From the 5272 and the 5307 documentation, I have deduced that it is
416 * probably CACR[24]. Should someone say something to Motorola?
417 * ~Jeremy
418 */
419 move.l #0x01000000, %d0 /* Invalidate whole cache */
420 move.c %d0,%CACR
421 move.l #0xff00c000, %d0 /* Set FLASH cachable: always match (SM=0b10) */
422 move.c %d0, %ACR0
423 move.l #0x0000c000, %d0 /* Set SDRAM cachable: always match (SM=0b10) */
424 move.c %d0, %ACR1
425 move.l #0x90000200, %d0 /* Set cache enable cmd */
426 move.c %d0,%CACR
427 moveq #1, %d0
428 move.l %d0, icache_state
429 rts
430#endif
431
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]432 .globl icache_disable
433icache_disable:
434 move.l #0x00000100, %d0 /* Setup cache mask */
435 movec %d0, %CACR /* Enable cache */
436 clr.l %d0 /* Setup cache mask */
437 movec %d0, %ACR0 /* Enable cache */
438 movec %d0, %ACR1 /* Enable cache */
439 moveq #0, %d0
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]440icache_state_access_2:
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]441 move.l %d0, icache_state
442 rts
443
444 .globl icache_status
445icache_status:
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]446icache_state_access_3:
TsiChungLiew8cd73be2007-08-15 19:21:21 -0500[diff] [blame]447 move.l #(icache_state), %a0
448 move.l (%a0), %d0
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]449 rts
450
451 .data
452icache_state:
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]453 .long 0 /* cache is diabled on inirialization */
stroese53395a22004-12-16 18:09:49 +0000[diff] [blame]454
TsiChungLiew8cd73be2007-08-15 19:21:21 -0500[diff] [blame]455 .globl dcache_enable
456dcache_enable:
457 /* dummy function */
458 rts
459
460 .globl dcache_disable
461dcache_disable:
462 /* dummy function */
463 rts
464
465 .globl dcache_status
466dcache_status:
467 /* dummy function */
468 rts
469
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]470/*------------------------------------------------------------------------------*/
471
472 .globl version_string
473version_string:
474 .ascii U_BOOT_VERSION
475 .ascii " (", __DATE__, " - ", __TIME__, ")"
476 .ascii CONFIG_IDENT_STRING, "\0"