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stroese9f53bf32003-05-23 11:35:47 +00001/*
stroesea9484a92004-12-16 18:05:42 +00002 * (C) Copyright 2001-2004
stroese9f53bf32003-05-23 11:35:47 +00003 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405 CPU */
wdenkda55c6e2004-01-20 23:12:12 +000037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_PMC405 1 /* ...on a PMC405 board */
stroese9f53bf32003-05-23 11:35:47 +000039
wdenkda55c6e2004-01-20 23:12:12 +000040#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
41#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
stroese9f53bf32003-05-23 11:35:47 +000042
stroesea9484a92004-12-16 18:05:42 +000043#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
stroese9f53bf32003-05-23 11:35:47 +000044
45#define CONFIG_BAUDRATE 9600
46#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
47
48#undef CONFIG_BOOTARGS
stroesea9484a92004-12-16 18:05:42 +000049#undef CONFIG_BOOTCOMMAND
50
51#define CONFIG_PREBOOT /* enable preboot variable */
stroese9f53bf32003-05-23 11:35:47 +000052
53#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020054#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
stroese9f53bf32003-05-23 11:35:47 +000055
Stefan Roese1c671a92006-01-18 20:03:15 +010056#define CONFIG_NET_MULTI 1
57#undef CONFIG_HAS_ETH1
58
stroese9f53bf32003-05-23 11:35:47 +000059#define CONFIG_MII 1 /* MII PHY management */
wdenkda55c6e2004-01-20 23:12:12 +000060#define CONFIG_PHY_ADDR 0 /* PHY address */
stroesea9484a92004-12-16 18:05:42 +000061#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
Stefan Roese1c671a92006-01-18 20:03:15 +010062#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
63
64#define CONFIG_NETCONSOLE /* include NetConsole support */
stroese9f53bf32003-05-23 11:35:47 +000065
Jon Loeligercc1f0bb2007-07-08 14:49:44 -050066
67/*
Jon Loeligerbeb9ff42007-07-10 09:22:23 -050068 * BOOTP options
69 */
70#define CONFIG_BOOTP_BOOTFILESIZE
71#define CONFIG_BOOTP_BOOTPATH
72#define CONFIG_BOOTP_GATEWAY
73#define CONFIG_BOOTP_HOSTNAME
74
75
76/*
Jon Loeligercc1f0bb2007-07-08 14:49:44 -050077 * Command line configuration.
78 */
79#include <config_cmd_default.h>
80
81#define CONFIG_CMD_BSP
82#define CONFIG_CMD_PCI
83#define CONFIG_CMD_IRQ
84#define CONFIG_CMD_ELF
85#define CONFIG_CMD_DATE
86#define CONFIG_CMD_JFFS2
87#define CONFIG_CMD_MII
88#define CONFIG_CMD_I2C
89#define CONFIG_CMD_PING
90#define CONFIG_CMD_UNIVERSE
91#define CONFIG_CMD_EEPROM
92
stroese9f53bf32003-05-23 11:35:47 +000093
94#define CONFIG_MAC_PARTITION
95#define CONFIG_DOS_PARTITION
96
wdenkda55c6e2004-01-20 23:12:12 +000097#undef CONFIG_WATCHDOG /* watchdog disabled */
stroese9f53bf32003-05-23 11:35:47 +000098
stroesea9484a92004-12-16 18:05:42 +000099#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200100#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
stroese9f53bf32003-05-23 11:35:47 +0000101
wdenkda55c6e2004-01-20 23:12:12 +0000102#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
stroese9f53bf32003-05-23 11:35:47 +0000103
104/*
105 * Miscellaneous configurable options
106 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200107#define CONFIG_SYS_LONGHELP /* undef to save memory */
108#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
stroese9f53bf32003-05-23 11:35:47 +0000109
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200110#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
111#ifdef CONFIG_SYS_HUSH_PARSER
112#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
stroese9f53bf32003-05-23 11:35:47 +0000113#endif
114
Jon Loeligercc1f0bb2007-07-08 14:49:44 -0500115#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200116#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
stroese9f53bf32003-05-23 11:35:47 +0000117#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200118#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
stroese9f53bf32003-05-23 11:35:47 +0000119#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200120#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
121#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
122#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
stroese9f53bf32003-05-23 11:35:47 +0000123
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200124#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
stroese9f53bf32003-05-23 11:35:47 +0000125
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200126#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
stroese9f53bf32003-05-23 11:35:47 +0000127
stroesea9484a92004-12-16 18:05:42 +0000128#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
129
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200130#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
131#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
stroese9f53bf32003-05-23 11:35:47 +0000132
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200133#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
134#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
135#define CONFIG_SYS_BASE_BAUD 691200
stroese9f53bf32003-05-23 11:35:47 +0000136
137/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200138#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk57b2d802003-06-27 21:31:46 +0000139 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
140 57600, 115200, 230400, 460800, 921600 }
stroese9f53bf32003-05-23 11:35:47 +0000141
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200142#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
143#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
stroese9f53bf32003-05-23 11:35:47 +0000144
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200145#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
stroese9f53bf32003-05-23 11:35:47 +0000146
stroesea9484a92004-12-16 18:05:42 +0000147#define CONFIG_LOOPW 1 /* enable loopw command */
148
stroese9f53bf32003-05-23 11:35:47 +0000149#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
150
wdenkda55c6e2004-01-20 23:12:12 +0000151#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
stroese94ef1cf2003-06-05 15:39:44 +0000152
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200153#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroese94ef1cf2003-06-05 15:39:44 +0000154
stroese9f53bf32003-05-23 11:35:47 +0000155/*-----------------------------------------------------------------------
156 * PCI stuff
157 *-----------------------------------------------------------------------
158 */
stroesea9484a92004-12-16 18:05:42 +0000159#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
160#define PCI_HOST_FORCE 1 /* configure as pci host */
161#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
stroese9f53bf32003-05-23 11:35:47 +0000162
stroesea9484a92004-12-16 18:05:42 +0000163#define CONFIG_PCI /* include pci support */
164#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
165#define CONFIG_PCI_PNP /* do pci plug-and-play */
166 /* resource configuration */
stroese9f53bf32003-05-23 11:35:47 +0000167
stroesea9484a92004-12-16 18:05:42 +0000168#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
stroese9f53bf32003-05-23 11:35:47 +0000169
stroesea9484a92004-12-16 18:05:42 +0000170#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
171
172#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
173
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200174#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
175#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID: Non-Monarch */
176#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID: Monarch */
177#define CONFIG_SYS_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid()
Stefan Roese1c671a92006-01-18 20:03:15 +0100178
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200179#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
Stefan Roese1c671a92006-01-18 20:03:15 +0100180
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200181#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
182#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
183#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
Stefan Roese1c671a92006-01-18 20:03:15 +0100184#if 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200185#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to internal regs */
186#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable */
187#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
Stefan Roese1c671a92006-01-18 20:03:15 +0100188#else /* old mapping */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200189#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
190#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
191#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
Stefan Roese1c671a92006-01-18 20:03:15 +0100192#endif
stroese9f53bf32003-05-23 11:35:47 +0000193/*-----------------------------------------------------------------------
194 * Start addresses for the final memory configuration
195 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200196 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
stroese9f53bf32003-05-23 11:35:47 +0000197 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200198#define CONFIG_SYS_SDRAM_BASE 0x00000000
199#define CONFIG_SYS_MONITOR_BASE 0xFFFC0000
200#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
201#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
stroese9f53bf32003-05-23 11:35:47 +0000202
203/*
204 * For booting Linux, the board info and command line data
205 * have to be in the first 8 MB of memory, since this is
206 * the maximum mapped by the Linux kernel during initialization.
207 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200208#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
stroese9f53bf32003-05-23 11:35:47 +0000209
210/*-----------------------------------------------------------------------
211 * FLASH organization
212 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200213#define CONFIG_SYS_FLASH_BASE 0xFE000000
214#define CONFIG_SYS_FLASH_INCREMENT 0x01000000
stroese9f53bf32003-05-23 11:35:47 +0000215
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200216#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200217#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200218#define CONFIG_SYS_FLASH_PROTECTION 1 /* don't use hardware protection */
219#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
220#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
221#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT }
222#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
Stefan Roese031dc5c2005-09-22 09:07:15 +0200223
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200224#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
stroese9f53bf32003-05-23 11:35:47 +0000225
Wolfgang Denk47f57792005-08-08 01:03:24 +0200226/*
227 * JFFS2 partitions - second bank contains u-boot
228 *
229 */
230/* No command line, one static partition, whole device */
231#undef CONFIG_JFFS2_CMDLINE
232#define CONFIG_JFFS2_DEV "nor0"
Stefan Roese031dc5c2005-09-22 09:07:15 +0200233#define CONFIG_JFFS2_PART_SIZE 0x01b00000
234#define CONFIG_JFFS2_PART_OFFSET 0x00400000
Wolfgang Denk47f57792005-08-08 01:03:24 +0200235
236/* mtdparts command line support */
237/* Note: fake mtd_id used, no linux mtd map file */
238/*
239#define CONFIG_JFFS2_CMDLINE
240#define MTDIDS_DEFAULT "nor0=pmc405-0"
241#define MTDPARTS_DEFAULT "mtdparts=pmc405-0:-(jffs2)"
242*/
stroese9f53bf32003-05-23 11:35:47 +0000243
244/*-----------------------------------------------------------------------
245 * Environment Variable setup
246 */
Jean-Christophe PLAGNIOL-VILLARDe46af642008-09-05 09:19:30 +0200247#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200248#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
249#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
wdenk57b2d802003-06-27 21:31:46 +0000250 /* total size of a CAT24WC16 is 2048 bytes */
stroese9f53bf32003-05-23 11:35:47 +0000251
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200252#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
253#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
stroese9f53bf32003-05-23 11:35:47 +0000254
255/*-----------------------------------------------------------------------
256 * I2C EEPROM (CAT24WC16) for environment
257 */
258#define CONFIG_HARD_I2C /* I2c with hardware support */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200259#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
260#define CONFIG_SYS_I2C_SLAVE 0x7F
stroese9f53bf32003-05-23 11:35:47 +0000261
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200262#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
263#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
wdenkda55c6e2004-01-20 23:12:12 +0000264/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200265#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
266#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
stroese9f53bf32003-05-23 11:35:47 +0000267 /* 16 byte page write mode using*/
wdenkda55c6e2004-01-20 23:12:12 +0000268 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200269#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
stroese9f53bf32003-05-23 11:35:47 +0000270
271/*-----------------------------------------------------------------------
stroese9f53bf32003-05-23 11:35:47 +0000272 * External Bus Controller (EBC) Setup
273 */
wdenkda55c6e2004-01-20 23:12:12 +0000274#define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */
275#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */
276#define CAN_BA 0xF0000000 /* CAN Base Address */
277#define RTC_BA 0xF0000500 /* RTC Base Address */
Stefan Roese1c671a92006-01-18 20:03:15 +0100278#define NVRAM_BA 0xF0200000 /* NVRAM Base Address */
stroese9f53bf32003-05-23 11:35:47 +0000279
wdenkda55c6e2004-01-20 23:12:12 +0000280/* Memory Bank 0 (Flash Bank 0) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200281#define CONFIG_SYS_EBC_PB0AP 0x92015480
282#define CONFIG_SYS_EBC_PB0CR FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
stroese9f53bf32003-05-23 11:35:47 +0000283
wdenkda55c6e2004-01-20 23:12:12 +0000284/* Memory Bank 1 (Flash Bank 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200285#define CONFIG_SYS_EBC_PB1AP 0x92015480
286#define CONFIG_SYS_EBC_PB1CR FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
stroese9f53bf32003-05-23 11:35:47 +0000287
wdenkda55c6e2004-01-20 23:12:12 +0000288/* Memory Bank 2 (CAN0, 1, RTC) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200289#define CONFIG_SYS_EBC_PB2AP 0x03000440 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
290#define CONFIG_SYS_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
stroese9f53bf32003-05-23 11:35:47 +0000291
Stefan Roese1c671a92006-01-18 20:03:15 +0100292/* Memory Bank 3 -> unused */
293
294/* Memory Bank 4 (NVRAM) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200295#define CONFIG_SYS_EBC_PB4AP 0x03000440 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
296#define CONFIG_SYS_EBC_PB4CR NVRAM_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
stroese9f53bf32003-05-23 11:35:47 +0000297
298/*-----------------------------------------------------------------------
stroese9b117ff2003-09-12 08:53:54 +0000299 * FPGA stuff
300 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200301#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
302#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
stroese9b117ff2003-09-12 08:53:54 +0000303
304/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200305#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
306#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */
307#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */
308#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */
309#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */
stroese9b117ff2003-09-12 08:53:54 +0000310
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200311#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
stroesea9484a92004-12-16 18:05:42 +0000312
stroese9b117ff2003-09-12 08:53:54 +0000313/*-----------------------------------------------------------------------
Stefan Roese1c671a92006-01-18 20:03:15 +0100314 * GPIOs
315 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200316#define CONFIG_SYS_NONMONARCH (0x80000000 >> 14) /* GPIO24 */
317#define CONFIG_SYS_XEREADY (0x80000000 >> 15) /* GPIO15 */
318#define CONFIG_SYS_INTA_FAKE (0x80000000 >> 19) /* GPIO19 */
319#define CONFIG_SYS_SELF_RST (0x80000000 >> 21) /* GPIO21 */
320#define CONFIG_SYS_REV1_2 (0x80000000 >> 23) /* GPIO23 */
Stefan Roese1c671a92006-01-18 20:03:15 +0100321
322/*-----------------------------------------------------------------------
stroese9f53bf32003-05-23 11:35:47 +0000323 * Definitions for initial stack pointer and data area (in data cache)
324 */
325
326/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200327#define CONFIG_SYS_TEMP_STACK_OCM 1
stroese9f53bf32003-05-23 11:35:47 +0000328
329/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200330#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
331#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
stroese9f53bf32003-05-23 11:35:47 +0000332
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200333#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
334#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
335#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
336#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
337#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
stroese9f53bf32003-05-23 11:35:47 +0000338
339/*
340 * Internal Definitions
341 *
342 * Boot Flags
343 */
344#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
345#define BOOTFLAG_WARM 0x02 /* Software reboot */
346
347#endif /* __CONFIG_H */