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wdenkc12081a2004-03-23 20:18:25 +00001/*
wdenk8d5d28a2005-04-02 22:37:54 +00002 * (C) Copyright 2003-2005
wdenkc12081a2004-03-23 20:18:25 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31
32#define CONFIG_MPC5200
wdenk50fc90c2004-05-05 08:31:53 +000033#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
wdenkc12081a2004-03-23 20:18:25 +000034#define CONFIG_PM520 1 /* ... on PM520 board */
35
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020036#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
wdenkc12081a2004-03-23 20:18:25 +000037
wdenk9e930b62004-06-19 21:19:10 +000038#define CONFIG_MISC_INIT_R
39
wdenkc12081a2004-03-23 20:18:25 +000040#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
41#define BOOTFLAG_WARM 0x02 /* Software reboot */
42
Becky Bruce03ea1be2008-05-08 19:02:12 -050043#define CONFIG_HIGH_BATS 1 /* High BATs supported */
44
wdenkc12081a2004-03-23 20:18:25 +000045/*
46 * Serial console configuration
47 */
48#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
49#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020050#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenkc12081a2004-03-23 20:18:25 +000051
52
53#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
54/*
55 * PCI Mapping:
56 * 0x40000000 - 0x4fffffff - PCI Memory
57 * 0x50000000 - 0x50ffffff - PCI IO Space
58 */
59#define CONFIG_PCI 1
60#define CONFIG_PCI_PNP 1
61#define CONFIG_PCI_SCAN_SHOW 1
TsiChung Liew521f97b2008-03-30 01:19:06 -050062#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
wdenkc12081a2004-03-23 20:18:25 +000063
64#define CONFIG_PCI_MEM_BUS 0x40000000
65#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
66#define CONFIG_PCI_MEM_SIZE 0x10000000
67
68#define CONFIG_PCI_IO_BUS 0x50000000
69#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
70#define CONFIG_PCI_IO_SIZE 0x01000000
71
72#define CONFIG_NET_MULTI 1
Marian Balakowiczaab8c492005-10-28 22:30:33 +020073#define CONFIG_MII 1
wdenkc12081a2004-03-23 20:18:25 +000074#define CONFIG_EEPRO100 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020075#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenkc12081a2004-03-23 20:18:25 +000076#undef CONFIG_NS8382X
77
wdenk9e930b62004-06-19 21:19:10 +000078#endif
79
80/* Partitions */
81#define CONFIG_DOS_PARTITION
82
83/* USB */
84#if 1
85#define CONFIG_USB_OHCI
wdenk9e930b62004-06-19 21:19:10 +000086#define CONFIG_USB_STORAGE
wdenk9e930b62004-06-19 21:19:10 +000087#endif
88
Jon Loeligercc1f0bb2007-07-08 14:49:44 -050089#if !defined(CONFIG_BOOT_ROM)
Bartlomiej Sieka582f1a32006-03-05 18:57:33 +010090/* DoC requires legacy NAND for now */
Jean-Christophe PLAGNIOL-VILLARD719bb5f2008-08-13 01:40:43 +020091#define CONFIG_NAND_LEGACY
wdenkc12081a2004-03-23 20:18:25 +000092#endif
93
Jon Loeligercc1f0bb2007-07-08 14:49:44 -050094
wdenkc12081a2004-03-23 20:18:25 +000095/*
Jon Loeligerbeb9ff42007-07-10 09:22:23 -050096 * BOOTP options
97 */
98#define CONFIG_BOOTP_BOOTFILESIZE
99#define CONFIG_BOOTP_BOOTPATH
100#define CONFIG_BOOTP_GATEWAY
101#define CONFIG_BOOTP_HOSTNAME
102
103
104/*
Jon Loeligercc1f0bb2007-07-08 14:49:44 -0500105 * Command line configuration.
wdenkc12081a2004-03-23 20:18:25 +0000106 */
Jon Loeligercc1f0bb2007-07-08 14:49:44 -0500107#include <config_cmd_default.h>
wdenkc12081a2004-03-23 20:18:25 +0000108
Jon Loeligercc1f0bb2007-07-08 14:49:44 -0500109#define CONFIG_CMD_BEDBUG
110#define CONFIG_CMD_DATE
111#define CONFIG_CMD_DHCP
112#define CONFIG_CMD_EEPROM
113#define CONFIG_CMD_FAT
114#define CONFIG_CMD_I2C
115#define CONFIG_CMD_IDE
116#define CONFIG_CMD_NFS
117#define CONFIG_CMD_SNTP
118#define CONFIG_CMD_USB
119
120#if !defined(CONFIG_BOOT_ROM)
121#define CONFIG_CMD_DOC
122#endif
123
124#if defined(CONFIG_MPC5200)
125#define CONFIG_CMD_PCI
126#endif
127
wdenkc12081a2004-03-23 20:18:25 +0000128
129/*
130 * Autobooting
131 */
132#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenk9e930b62004-06-19 21:19:10 +0000133
134#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk1baed662008-03-03 12:16:44 +0100135 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenk9e930b62004-06-19 21:19:10 +0000136 "echo"
137
138#undef CONFIG_BOOTARGS
139
140#define CONFIG_EXTRA_ENV_SETTINGS \
141 "netdev=eth0\0" \
142 "hostname=pm520\0" \
143 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +0100144 "nfsroot=${serverip}:${rootpath}\0" \
wdenk9e930b62004-06-19 21:19:10 +0000145 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +0100146 "addip=setenv bootargs ${bootargs} " \
147 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
148 ":${hostname}:${netdev}:off panic=1\0" \
wdenk9e930b62004-06-19 21:19:10 +0000149 "flash_nfs=run nfsargs addip;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +0100150 "bootm ${kernel_addr}\0" \
wdenk9e930b62004-06-19 21:19:10 +0000151 "flash_self=run ramargs addip;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +0100152 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
153 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk9e930b62004-06-19 21:19:10 +0000154 "rootpath=/opt/eldk30/ppc_82xx\0" \
155 "bootfile=/tftpboot/PM520/uImage\0" \
156 ""
157
158#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkc12081a2004-03-23 20:18:25 +0000159
160#if defined(CONFIG_MPC5200)
161/*
162 * IPB Bus clocking configuration.
163 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200164#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
wdenkc12081a2004-03-23 20:18:25 +0000165#endif
166/*
167 * I2C configuration
168 */
169#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200170#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
wdenkc12081a2004-03-23 20:18:25 +0000171
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200172#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
173#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenkc12081a2004-03-23 20:18:25 +0000174
175/*
176 * EEPROM configuration
177 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200178#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
179#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
180#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
181#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
wdenkc12081a2004-03-23 20:18:25 +0000182
183/*
184 * RTC configuration
185 */
186#define CONFIG_RTC_PCF8563
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200187#define CONFIG_SYS_I2C_RTC_ADDR 0x51
wdenkc12081a2004-03-23 20:18:25 +0000188
189/*
wdenk9e930b62004-06-19 21:19:10 +0000190 * Disk-On-Chip configuration
wdenkc12081a2004-03-23 20:18:25 +0000191 */
wdenk9e930b62004-06-19 21:19:10 +0000192
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200193#define CONFIG_SYS_DOC_SHORT_TIMEOUT
194#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
wdenk9e930b62004-06-19 21:19:10 +0000195
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200196#define CONFIG_SYS_DOC_SUPPORT_2000
197#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
198#define CONFIG_SYS_DOC_BASE 0xE0000000
199#define CONFIG_SYS_DOC_SIZE 0x00100000
wdenk9e930b62004-06-19 21:19:10 +0000200
201#if defined(CONFIG_BOOT_ROM)
202/*
203 * Flash configuration (8,16 or 32 MB)
204 * TEXT base always at 0xFFF00000
205 * ENV_ADDR always at 0xFFF40000
Wolfgang Denk618582e2005-12-29 15:12:09 +0100206 * FLASH_BASE at 0xFA000000 for 64 MB
207 * 0xFC000000 for 32 MB
wdenk9e930b62004-06-19 21:19:10 +0000208 * 0xFD000000 for 16 MB
209 * 0xFD800000 for 8 MB
210 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200211#define CONFIG_SYS_FLASH_BASE 0xFA000000
212#define CONFIG_SYS_FLASH_SIZE 0x04000000
213#define CONFIG_SYS_BOOTROM_BASE 0xFFF00000
214#define CONFIG_SYS_BOOTROM_SIZE 0x00080000
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200215#define CONFIG_ENV_ADDR (0xFDF00000 + 0x40000)
wdenk9e930b62004-06-19 21:19:10 +0000216#else
217/*
218 * Flash configuration (8,16 or 32 MB)
219 * TEXT base always at 0xFFF00000
220 * ENV_ADDR always at 0xFFF40000
Wolfgang Denk618582e2005-12-29 15:12:09 +0100221 * FLASH_BASE at 0xFC000000 for 64 MB
222 * 0xFE000000 for 32 MB
wdenk9e930b62004-06-19 21:19:10 +0000223 * 0xFF000000 for 16 MB
224 * 0xFF800000 for 8 MB
225 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200226#define CONFIG_SYS_FLASH_BASE 0xFC000000
227#define CONFIG_SYS_FLASH_SIZE 0x04000000
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200228#define CONFIG_ENV_ADDR (0xFFF00000 + 0x40000)
wdenk9e930b62004-06-19 21:19:10 +0000229#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200230#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
wdenkc12081a2004-03-23 20:18:25 +0000231
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200232#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
wdenkc12081a2004-03-23 20:18:25 +0000233
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200234#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
235#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
236#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
237#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
238#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
wdenkc12081a2004-03-23 20:18:25 +0000239
240#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
241
242#undef CONFIG_FLASH_16BIT /* Flash is 32-bit */
243
244
245/*
246 * Environment settings
247 */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200248#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200249#define CONFIG_ENV_SIZE 0x10000
250#define CONFIG_ENV_SECT_SIZE 0x40000
wdenkc12081a2004-03-23 20:18:25 +0000251#define CONFIG_ENV_OVERWRITE 1
252
253/*
254 * Memory map
255 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200256#define CONFIG_SYS_MBAR 0xf0000000
257#define CONFIG_SYS_SDRAM_BASE 0x00000000
258#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
wdenkc12081a2004-03-23 20:18:25 +0000259
260/* Use SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200261#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
262#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
wdenkc12081a2004-03-23 20:18:25 +0000263
264
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200265#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
266#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
267#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc12081a2004-03-23 20:18:25 +0000268
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200269#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
270#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
271# define CONFIG_SYS_RAMBOOT 1
wdenkc12081a2004-03-23 20:18:25 +0000272#endif
273
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200274#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
275#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
276#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc12081a2004-03-23 20:18:25 +0000277
278/*
279 * Ethernet configuration
280 */
wdenk50fc90c2004-05-05 08:31:53 +0000281#define CONFIG_MPC5xxx_FEC 1
282/*
283 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
284 */
285/* #define CONFIG_FEC_10MBIT 1 */
wdenkc12081a2004-03-23 20:18:25 +0000286#define CONFIG_PHY_ADDR 0x00
287
288/*
289 * GPIO configuration
290 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200291#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
wdenkc12081a2004-03-23 20:18:25 +0000292
293/*
294 * Miscellaneous configurable options
295 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200296#define CONFIG_SYS_LONGHELP /* undef to save memory */
297#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligercc1f0bb2007-07-08 14:49:44 -0500298#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200299#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc12081a2004-03-23 20:18:25 +0000300#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200301#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc12081a2004-03-23 20:18:25 +0000302#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200303#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
304#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
305#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkc12081a2004-03-23 20:18:25 +0000306
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200307#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
308#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
wdenkc12081a2004-03-23 20:18:25 +0000309
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200310#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkc12081a2004-03-23 20:18:25 +0000311
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200312#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkc12081a2004-03-23 20:18:25 +0000313
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200314#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeligercc1f0bb2007-07-08 14:49:44 -0500315#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200316# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeligercc1f0bb2007-07-08 14:49:44 -0500317#endif
318
wdenkc12081a2004-03-23 20:18:25 +0000319/*
320 * Various low-level settings
321 */
322#if defined(CONFIG_MPC5200)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200323#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
324#define CONFIG_SYS_HID0_FINAL HID0_ICE
wdenkc12081a2004-03-23 20:18:25 +0000325#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200326#define CONFIG_SYS_HID0_INIT 0
327#define CONFIG_SYS_HID0_FINAL 0
wdenkc12081a2004-03-23 20:18:25 +0000328#endif
329
wdenk9e930b62004-06-19 21:19:10 +0000330#if defined(CONFIG_BOOT_ROM)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200331#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_BOOTROM_BASE
332#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_BOOTROM_SIZE
333#define CONFIG_SYS_BOOTCS_CFG 0x00047800
334#define CONFIG_SYS_CS0_START CONFIG_SYS_BOOTROM_BASE
335#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_BOOTROM_SIZE
336#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
337#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
338#define CONFIG_SYS_CS1_CFG 0x0004FF00
wdenk9e930b62004-06-19 21:19:10 +0000339#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200340#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
341#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
342#define CONFIG_SYS_BOOTCS_CFG 0x0004FF00
343#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
344#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
345#define CONFIG_SYS_CS1_START CONFIG_SYS_DOC_BASE
346#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_DOC_SIZE
347#define CONFIG_SYS_CS1_CFG 0x00047800
wdenk9e930b62004-06-19 21:19:10 +0000348#endif
wdenkc12081a2004-03-23 20:18:25 +0000349
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200350#define CONFIG_SYS_CS_BURST 0x00000000
351#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
wdenkc12081a2004-03-23 20:18:25 +0000352
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200353#define CONFIG_SYS_RESET_ADDRESS 0xff000000
wdenkc12081a2004-03-23 20:18:25 +0000354
wdenk9e930b62004-06-19 21:19:10 +0000355/*-----------------------------------------------------------------------
356 * USB stuff
357 *-----------------------------------------------------------------------
358 */
359#define CONFIG_USB_CLOCK 0x0001BBBB
360#define CONFIG_USB_CONFIG 0x00005000
361
362/*-----------------------------------------------------------------------
363 * IDE/ATA stuff Supports IDE harddisk
364 *-----------------------------------------------------------------------
365 */
366
367#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
368
369#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
370#undef CONFIG_IDE_LED /* LED for ide not supported */
371
372#undef CONFIG_IDE_RESET /* reset for ide supported */
373#define CONFIG_IDE_PREINIT
374
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200375#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
376#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drive per IDE bus */
wdenk9e930b62004-06-19 21:19:10 +0000377
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200378#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenk9e930b62004-06-19 21:19:10 +0000379
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200380#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
wdenk9e930b62004-06-19 21:19:10 +0000381
382/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200383#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
wdenk9e930b62004-06-19 21:19:10 +0000384
385/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200386#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
wdenk9e930b62004-06-19 21:19:10 +0000387
388/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200389#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
wdenk9e930b62004-06-19 21:19:10 +0000390
391/* Interval between registers */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200392#define CONFIG_SYS_ATA_STRIDE 4
wdenk9e930b62004-06-19 21:19:10 +0000393
wdenkc12081a2004-03-23 20:18:25 +0000394#endif /* __CONFIG_H */