wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2004 Freescale Semiconductor. |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | /* |
| 24 | * mpc8555cds board configuration file |
| 25 | * |
| 26 | * Please refer to doc/README.mpc85xxcds for more info. |
| 27 | * |
| 28 | */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 29 | #ifndef __CONFIG_H |
| 30 | #define __CONFIG_H |
| 31 | |
| 32 | /* High Level Configuration Options */ |
| 33 | #define CONFIG_BOOKE 1 /* BOOKE */ |
| 34 | #define CONFIG_E500 1 /* BOOKE e500 family */ |
| 35 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ |
Jon Loeliger | f5ad378 | 2005-07-23 10:37:35 -0500 | [diff] [blame] | 36 | #define CONFIG_CPM2 1 /* has CPM2 */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 37 | #define CONFIG_MPC8555 1 /* MPC8555 specific */ |
| 38 | #define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */ |
| 39 | |
| 40 | #define CONFIG_PCI |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 41 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 42 | #define CONFIG_ENV_OVERWRITE |
Kumar Gala | 35b2b09 | 2008-01-16 01:45:10 -0600 | [diff] [blame] | 43 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 44 | |
Jon Loeliger | 6bcdb40 | 2008-03-19 15:02:07 -0500 | [diff] [blame] | 45 | #define CONFIG_FSL_VIA |
Timur Tabi | 0b87d3f | 2008-07-18 16:52:23 +0200 | [diff] [blame] | 46 | |
Jon Loeliger | 6bcdb40 | 2008-03-19 15:02:07 -0500 | [diff] [blame] | 47 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 48 | /* |
| 49 | * When initializing flash, if we cannot find the manufacturer ID, |
| 50 | * assume this is the AMD flash associated with the CDS board. |
| 51 | * This allows booting from a promjet. |
| 52 | */ |
| 53 | #define CONFIG_ASSUME_AMD_FLASH |
| 54 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 55 | #ifndef __ASSEMBLY__ |
| 56 | extern unsigned long get_clock_freq(void); |
| 57 | #endif |
| 58 | #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ |
| 59 | |
| 60 | /* |
| 61 | * These can be toggled for performance analysis, otherwise use default. |
| 62 | */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 63 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 64 | #define CONFIG_BTB /* toggle branch predition */ |
| 65 | #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ |
| 66 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 67 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
| 68 | #define CONFIG_SYS_MEMTEST_END 0x00400000 |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 69 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 70 | /* |
| 71 | * Base addresses -- Note these are effective addresses where the |
| 72 | * actual resources get mapped (not physical addresses) |
| 73 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 74 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
| 75 | #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ |
| 76 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ |
| 77 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 78 | |
Jon Loeliger | c63209f | 2008-03-18 11:12:42 -0500 | [diff] [blame] | 79 | /* DDR Setup */ |
| 80 | #define CONFIG_FSL_DDR1 |
| 81 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ |
| 82 | #define CONFIG_DDR_SPD |
| 83 | #undef CONFIG_FSL_DDR_INTERACTIVE |
| 84 | |
| 85 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| 86 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 87 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
| 88 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 89 | |
Jon Loeliger | c63209f | 2008-03-18 11:12:42 -0500 | [diff] [blame] | 90 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
| 91 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 92 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 93 | |
Jon Loeliger | c63209f | 2008-03-18 11:12:42 -0500 | [diff] [blame] | 94 | /* I2C addresses of SPD EEPROMs */ |
| 95 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
| 96 | |
| 97 | /* Make sure required options are set */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 98 | #ifndef CONFIG_SPD_EEPROM |
| 99 | #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") |
| 100 | #endif |
| 101 | |
Jon Loeliger | 3f34a40 | 2005-07-25 11:13:26 -0500 | [diff] [blame] | 102 | #undef CONFIG_CLOCKS_IN_MHZ |
| 103 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 104 | /* |
Jon Loeliger | 3f34a40 | 2005-07-25 11:13:26 -0500 | [diff] [blame] | 105 | * Local Bus Definitions |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 106 | */ |
Jon Loeliger | 3f34a40 | 2005-07-25 11:13:26 -0500 | [diff] [blame] | 107 | |
| 108 | /* |
| 109 | * FLASH on the Local Bus |
| 110 | * Two banks, 8M each, using the CFI driver. |
| 111 | * Boot from BR0/OR0 bank at 0xff00_0000 |
| 112 | * Alternate BR1/OR1 bank at 0xff80_0000 |
| 113 | * |
| 114 | * BR0, BR1: |
| 115 | * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 |
| 116 | * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 |
| 117 | * Port Size = 16 bits = BRx[19:20] = 10 |
| 118 | * Use GPCM = BRx[24:26] = 000 |
| 119 | * Valid = BRx[31] = 1 |
| 120 | * |
| 121 | * 0 4 8 12 16 20 24 28 |
| 122 | * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 |
| 123 | * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 |
| 124 | * |
| 125 | * OR0, OR1: |
| 126 | * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 |
| 127 | * Reserved ORx[17:18] = 11, confusion here? |
| 128 | * CSNT = ORx[20] = 1 |
| 129 | * ACS = half cycle delay = ORx[21:22] = 11 |
| 130 | * SCY = 6 = ORx[24:27] = 0110 |
| 131 | * TRLX = use relaxed timing = ORx[29] = 1 |
| 132 | * EAD = use external address latch delay = OR[31] = 1 |
| 133 | * |
| 134 | * 0 4 8 12 16 20 24 28 |
| 135 | * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx |
| 136 | */ |
| 137 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 138 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 139 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 140 | #define CONFIG_SYS_BR0_PRELIM 0xff801001 |
| 141 | #define CONFIG_SYS_BR1_PRELIM 0xff001001 |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 142 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 143 | #define CONFIG_SYS_OR0_PRELIM 0xff806e65 |
| 144 | #define CONFIG_SYS_OR1_PRELIM 0xff806e65 |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 145 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 146 | #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} |
| 147 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
| 148 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ |
| 149 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 150 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 151 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 152 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 153 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 154 | |
Jean-Christophe PLAGNIOL-VILLARD | 8d94c23 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 155 | #define CONFIG_FLASH_CFI_DRIVER |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 156 | #define CONFIG_SYS_FLASH_CFI |
| 157 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 158 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 159 | |
| 160 | /* |
Jon Loeliger | 3f34a40 | 2005-07-25 11:13:26 -0500 | [diff] [blame] | 161 | * SDRAM on the Local Bus |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 162 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 163 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
| 164 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 165 | |
| 166 | /* |
| 167 | * Base Register 2 and Option Register 2 configure SDRAM. |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 168 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 169 | * |
| 170 | * For BR2, need: |
| 171 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 |
| 172 | * port-size = 32-bits = BR2[19:20] = 11 |
| 173 | * no parity checking = BR2[21:22] = 00 |
| 174 | * SDRAM for MSEL = BR2[24:26] = 011 |
| 175 | * Valid = BR[31] = 1 |
| 176 | * |
| 177 | * 0 4 8 12 16 20 24 28 |
| 178 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 |
| 179 | * |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 180 | * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 181 | * FIXME: the top 17 bits of BR2. |
| 182 | */ |
| 183 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 184 | #define CONFIG_SYS_BR2_PRELIM 0xf0001861 |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 185 | |
| 186 | /* |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 187 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 188 | * |
| 189 | * For OR2, need: |
| 190 | * 64MB mask for AM, OR2[0:7] = 1111 1100 |
| 191 | * XAM, OR2[17:18] = 11 |
| 192 | * 9 columns OR2[19-21] = 010 |
| 193 | * 13 rows OR2[23-25] = 100 |
| 194 | * EAD set for extra time OR[31] = 1 |
| 195 | * |
| 196 | * 0 4 8 12 16 20 24 28 |
| 197 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 |
| 198 | */ |
| 199 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 200 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 201 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 202 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
| 203 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ |
| 204 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ |
| 205 | #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 206 | |
| 207 | /* |
| 208 | * LSDMR masks |
| 209 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 210 | #define CONFIG_SYS_LBC_LSDMR_RFEN (1 << (31 - 1)) |
| 211 | #define CONFIG_SYS_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) |
| 212 | #define CONFIG_SYS_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) |
| 213 | #define CONFIG_SYS_LBC_LSDMR_RFCR16 (7 << (31 - 16)) |
| 214 | #define CONFIG_SYS_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) |
| 215 | #define CONFIG_SYS_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) |
| 216 | #define CONFIG_SYS_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) |
| 217 | #define CONFIG_SYS_LBC_LSDMR_BL8 (1 << (31 - 23)) |
| 218 | #define CONFIG_SYS_LBC_LSDMR_WRC4 (0 << (31 - 27)) |
| 219 | #define CONFIG_SYS_LBC_LSDMR_CL3 (3 << (31 - 31)) |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 220 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 221 | #define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) |
| 222 | #define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) |
| 223 | #define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) |
| 224 | #define CONFIG_SYS_LBC_LSDMR_OP_MRW (3 << (31 - 4)) |
| 225 | #define CONFIG_SYS_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) |
| 226 | #define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) |
| 227 | #define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) |
| 228 | #define CONFIG_SYS_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 229 | |
| 230 | /* |
| 231 | * Common settings for all Local Bus SDRAM commands. |
| 232 | * At run time, either BSMA1516 (for CPU 1.1) |
| 233 | * or BSMA1617 (for CPU 1.0) (old) |
| 234 | * is OR'ed in too. |
| 235 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 236 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( CONFIG_SYS_LBC_LSDMR_RFCR16 \ |
| 237 | | CONFIG_SYS_LBC_LSDMR_PRETOACT7 \ |
| 238 | | CONFIG_SYS_LBC_LSDMR_ACTTORW7 \ |
| 239 | | CONFIG_SYS_LBC_LSDMR_BL8 \ |
| 240 | | CONFIG_SYS_LBC_LSDMR_WRC4 \ |
| 241 | | CONFIG_SYS_LBC_LSDMR_CL3 \ |
| 242 | | CONFIG_SYS_LBC_LSDMR_RFEN \ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 243 | ) |
| 244 | |
| 245 | /* |
| 246 | * The CADMUS registers are connected to CS3 on CDS. |
| 247 | * The new memory map places CADMUS at 0xf8000000. |
| 248 | * |
| 249 | * For BR3, need: |
| 250 | * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 |
| 251 | * port-size = 8-bits = BR[19:20] = 01 |
| 252 | * no parity checking = BR[21:22] = 00 |
| 253 | * GPMC for MSEL = BR[24:26] = 000 |
| 254 | * Valid = BR[31] = 1 |
| 255 | * |
| 256 | * 0 4 8 12 16 20 24 28 |
| 257 | * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 |
| 258 | * |
| 259 | * For OR3, need: |
| 260 | * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 |
| 261 | * disable buffer ctrl OR[19] = 0 |
| 262 | * CSNT OR[20] = 1 |
| 263 | * ACS OR[21:22] = 11 |
| 264 | * XACS OR[23] = 1 |
| 265 | * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe |
| 266 | * SETA OR[28] = 0 |
| 267 | * TRLX OR[29] = 1 |
| 268 | * EHTR OR[30] = 1 |
| 269 | * EAD extra time OR[31] = 1 |
| 270 | * |
| 271 | * 0 4 8 12 16 20 24 28 |
| 272 | * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 |
| 273 | */ |
| 274 | |
Jon Loeliger | 6bcdb40 | 2008-03-19 15:02:07 -0500 | [diff] [blame] | 275 | #define CONFIG_FSL_CADMUS |
| 276 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 277 | #define CADMUS_BASE_ADDR 0xf8000000 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 278 | #define CONFIG_SYS_BR3_PRELIM 0xf8000801 |
| 279 | #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 280 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 281 | #define CONFIG_L1_INIT_RAM |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 282 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 283 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ |
| 284 | #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 285 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 286 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ |
| 287 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) |
| 288 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 289 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 290 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 291 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 292 | |
| 293 | /* Serial Port */ |
| 294 | #define CONFIG_CONS_INDEX 2 |
| 295 | #undef CONFIG_SERIAL_SOFTWARE_FIFO |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 296 | #define CONFIG_SYS_NS16550 |
| 297 | #define CONFIG_SYS_NS16550_SERIAL |
| 298 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 299 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 300 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 301 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 302 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 303 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 304 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| 305 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 306 | |
| 307 | /* Use the HUSH parser */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 308 | #define CONFIG_SYS_HUSH_PARSER |
| 309 | #ifdef CONFIG_SYS_HUSH_PARSER |
| 310 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 311 | #endif |
| 312 | |
Matthew McClintock | 3d40317 | 2006-06-28 10:43:36 -0500 | [diff] [blame] | 313 | /* pass open firmware flat tree */ |
Kumar Gala | d28ced3 | 2007-11-29 00:11:44 -0600 | [diff] [blame] | 314 | #define CONFIG_OF_LIBFDT 1 |
| 315 | #define CONFIG_OF_BOARD_SETUP 1 |
| 316 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
Matthew McClintock | 3d40317 | 2006-06-28 10:43:36 -0500 | [diff] [blame] | 317 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 318 | #define CONFIG_SYS_64BIT_VSPRINTF 1 |
| 319 | #define CONFIG_SYS_64BIT_STRTOUL 1 |
Jon Loeliger | c63209f | 2008-03-18 11:12:42 -0500 | [diff] [blame] | 320 | |
Jon Loeliger | 43d818f | 2006-10-20 15:50:15 -0500 | [diff] [blame] | 321 | /* |
| 322 | * I2C |
| 323 | */ |
| 324 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
| 325 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 326 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 327 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 328 | #define CONFIG_SYS_I2C_SLAVE 0x7F |
| 329 | #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ |
| 330 | #define CONFIG_SYS_I2C_OFFSET 0x3000 |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 331 | |
Timur Tabi | 0b87d3f | 2008-07-18 16:52:23 +0200 | [diff] [blame] | 332 | /* EEPROM */ |
| 333 | #define CONFIG_ID_EEPROM |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 334 | #define CONFIG_SYS_I2C_EEPROM_CCID |
| 335 | #define CONFIG_SYS_ID_EEPROM |
| 336 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| 337 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
Timur Tabi | 0b87d3f | 2008-07-18 16:52:23 +0200 | [diff] [blame] | 338 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 339 | /* |
| 340 | * General PCI |
| 341 | * Addresses are mapped 1-1. |
| 342 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 343 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
| 344 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE |
| 345 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
| 346 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 |
| 347 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 |
| 348 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 349 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 350 | #define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000 |
| 351 | #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE |
| 352 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ |
| 353 | #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 |
| 354 | #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 |
| 355 | #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 356 | |
Randy Vinson | 1dfd6d9 | 2007-02-27 19:42:22 -0700 | [diff] [blame] | 357 | #ifdef CONFIG_LEGACY |
| 358 | #define BRIDGE_ID 17 |
| 359 | #define VIA_ID 2 |
| 360 | #else |
| 361 | #define BRIDGE_ID 28 |
| 362 | #define VIA_ID 4 |
| 363 | #endif |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 364 | |
| 365 | #if defined(CONFIG_PCI) |
| 366 | |
| 367 | #define CONFIG_NET_MULTI |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 368 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
Matthew McClintock | aa6dd06 | 2006-06-28 10:46:13 -0500 | [diff] [blame] | 369 | #define CONFIG_MPC85XX_PCI2 |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 370 | |
| 371 | #undef CONFIG_EEPRO100 |
| 372 | #undef CONFIG_TULIP |
| 373 | |
Matthew McClintock | aa6dd06 | 2006-06-28 10:46:13 -0500 | [diff] [blame] | 374 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 375 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 376 | |
| 377 | #endif /* CONFIG_PCI */ |
| 378 | |
| 379 | |
| 380 | #if defined(CONFIG_TSEC_ENET) |
| 381 | |
| 382 | #ifndef CONFIG_NET_MULTI |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 383 | #define CONFIG_NET_MULTI 1 |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 384 | #endif |
| 385 | |
| 386 | #define CONFIG_MII 1 /* MII PHY management */ |
Kim Phillips | 177e58f | 2007-05-16 16:52:19 -0500 | [diff] [blame] | 387 | #define CONFIG_TSEC1 1 |
| 388 | #define CONFIG_TSEC1_NAME "TSEC0" |
| 389 | #define CONFIG_TSEC2 1 |
| 390 | #define CONFIG_TSEC2_NAME "TSEC1" |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 391 | #define TSEC1_PHY_ADDR 0 |
| 392 | #define TSEC2_PHY_ADDR 1 |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 393 | #define TSEC1_PHYIDX 0 |
| 394 | #define TSEC2_PHYIDX 0 |
Andy Fleming | 09b88df | 2007-08-15 20:03:25 -0500 | [diff] [blame] | 395 | #define TSEC1_FLAGS TSEC_GIGABIT |
| 396 | #define TSEC2_FLAGS TSEC_GIGABIT |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 397 | |
| 398 | /* Options are: TSEC[0-1] */ |
| 399 | #define CONFIG_ETHPRIME "TSEC0" |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 400 | |
| 401 | #endif /* CONFIG_TSEC_ENET */ |
| 402 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 403 | /* |
| 404 | * Environment |
| 405 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 406 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 407 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 408 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
| 409 | #define CONFIG_ENV_SIZE 0x2000 |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 410 | |
| 411 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 412 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 413 | |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 414 | /* |
Jon Loeliger | ed26c74 | 2007-07-10 09:10:49 -0500 | [diff] [blame] | 415 | * BOOTP options |
| 416 | */ |
| 417 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 418 | #define CONFIG_BOOTP_BOOTPATH |
| 419 | #define CONFIG_BOOTP_GATEWAY |
| 420 | #define CONFIG_BOOTP_HOSTNAME |
| 421 | |
| 422 | |
| 423 | /* |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 424 | * Command line configuration. |
| 425 | */ |
| 426 | #include <config_cmd_default.h> |
| 427 | |
| 428 | #define CONFIG_CMD_PING |
| 429 | #define CONFIG_CMD_I2C |
| 430 | #define CONFIG_CMD_MII |
Kumar Gala | 260fac3 | 2007-12-07 12:04:30 -0600 | [diff] [blame] | 431 | #define CONFIG_CMD_ELF |
Kumar Gala | 489675d | 2008-09-22 23:40:42 -0500 | [diff] [blame] | 432 | #define CONFIG_CMD_IRQ |
| 433 | #define CONFIG_CMD_SETEXPR |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 434 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 435 | #if defined(CONFIG_PCI) |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 436 | #define CONFIG_CMD_PCI |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 437 | #endif |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 438 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 439 | |
| 440 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 441 | |
| 442 | /* |
| 443 | * Miscellaneous configurable options |
| 444 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 445 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
Kumar Gala | 99da1d9 | 2007-11-29 10:34:28 -0600 | [diff] [blame] | 446 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 447 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| 448 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 449 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 450 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 451 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 452 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 453 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 454 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 455 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 456 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
| 457 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 458 | |
| 459 | /* |
| 460 | * For booting Linux, the board info and command line data |
| 461 | * have to be in the first 8 MB of memory, since this is |
| 462 | * the maximum mapped by the Linux kernel during initialization. |
| 463 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 464 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 465 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 466 | /* |
| 467 | * Internal Definitions |
| 468 | * |
| 469 | * Boot Flags |
| 470 | */ |
| 471 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
| 472 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
| 473 | |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 474 | #if defined(CONFIG_CMD_KGDB) |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 475 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| 476 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
| 477 | #endif |
| 478 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 479 | /* |
| 480 | * Environment Configuration |
| 481 | */ |
| 482 | |
| 483 | /* The mac addresses for all ethernet interface */ |
| 484 | #if defined(CONFIG_TSEC_ENET) |
Andy Fleming | 458c389 | 2007-08-16 16:35:02 -0500 | [diff] [blame] | 485 | #define CONFIG_HAS_ETH0 |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 486 | #define CONFIG_ETHADDR 00:E0:0C:00:00:FD |
wdenk | 54070ab | 2004-12-31 09:32:47 +0000 | [diff] [blame] | 487 | #define CONFIG_HAS_ETH1 |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 488 | #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD |
wdenk | 54070ab | 2004-12-31 09:32:47 +0000 | [diff] [blame] | 489 | #define CONFIG_HAS_ETH2 |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 490 | #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD |
| 491 | #endif |
| 492 | |
| 493 | #define CONFIG_IPADDR 192.168.1.253 |
| 494 | |
| 495 | #define CONFIG_HOSTNAME unknown |
| 496 | #define CONFIG_ROOTPATH /nfsroot |
| 497 | #define CONFIG_BOOTFILE your.uImage |
| 498 | |
| 499 | #define CONFIG_SERVERIP 192.168.1.1 |
| 500 | #define CONFIG_GATEWAYIP 192.168.1.1 |
| 501 | #define CONFIG_NETMASK 255.255.255.0 |
| 502 | |
| 503 | #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ |
| 504 | |
| 505 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
| 506 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ |
| 507 | |
| 508 | #define CONFIG_BAUDRATE 115200 |
| 509 | |
| 510 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 511 | "netdev=eth0\0" \ |
| 512 | "consoledev=ttyS1\0" \ |
Andy Fleming | 7243f97 | 2006-09-13 10:33:35 -0500 | [diff] [blame] | 513 | "ramdiskaddr=600000\0" \ |
| 514 | "ramdiskfile=your.ramdisk.u-boot\0" \ |
| 515 | "fdtaddr=400000\0" \ |
| 516 | "fdtfile=your.fdt.dtb\0" |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 517 | |
| 518 | #define CONFIG_NFSBOOTCOMMAND \ |
| 519 | "setenv bootargs root=/dev/nfs rw " \ |
| 520 | "nfsroot=$serverip:$rootpath " \ |
| 521 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| 522 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 523 | "tftp $loadaddr $bootfile;" \ |
Andy Fleming | 7243f97 | 2006-09-13 10:33:35 -0500 | [diff] [blame] | 524 | "tftp $fdtaddr $fdtfile;" \ |
| 525 | "bootm $loadaddr - $fdtaddr" |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 526 | |
| 527 | #define CONFIG_RAMBOOTCOMMAND \ |
| 528 | "setenv bootargs root=/dev/ram rw " \ |
| 529 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 530 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| 531 | "tftp $loadaddr $bootfile;" \ |
| 532 | "bootm $loadaddr $ramdiskaddr" |
| 533 | |
| 534 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
| 535 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 536 | #endif /* __CONFIG_H */ |