Martyn Welch | 56f96e6 | 2022-10-25 10:55:02 +0100 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Based on vendor support provided by AVNET Embedded |
| 4 | * |
| 5 | * Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH |
| 6 | * Copyright 2021 General Electric Company |
| 7 | * Copyright 2021 Collabora Ltd. |
| 8 | */ |
| 9 | |
| 10 | #ifndef __MSC_SM2S_IMX8MP_H |
| 11 | #define __MSC_SM2S_IMX8MP_H |
| 12 | |
| 13 | #include <linux/sizes.h> |
| 14 | #include <linux/stringify.h> |
| 15 | #include <asm/arch/imx-regs.h> |
| 16 | |
| 17 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) |
| 18 | #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) |
| 19 | |
| 20 | #if defined(CONFIG_CMD_NET) |
| 21 | #define CONFIG_FEC_MXC_PHYADDR 1 |
| 22 | #define PHY_ANEG_TIMEOUT 20000 |
| 23 | #endif |
| 24 | |
| 25 | #ifndef CONFIG_SPL_BUILD |
| 26 | #define BOOT_TARGET_DEVICES(func) \ |
| 27 | func(MMC, mmc, 1) \ |
| 28 | func(MMC, mmc, 2) |
| 29 | |
| 30 | #include <config_distro_bootcmd.h> |
| 31 | #endif |
| 32 | |
| 33 | /* Initial environment variables */ |
| 34 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 35 | BOOTENV \ |
| 36 | "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ |
| 37 | "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ |
| 38 | "image=Image\0" \ |
| 39 | "console=ttymxc1,115200\0" \ |
| 40 | "fdt_addr_r=0x43000000\0" \ |
| 41 | "boot_fdt=try\0" \ |
| 42 | "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ |
| 43 | "initrd_addr=0x43800000\0" \ |
| 44 | "bootm_size=0x10000000\0" \ |
| 45 | "mmcpart=1\0" \ |
| 46 | "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ |
| 47 | |
| 48 | /* Link Definitions */ |
| 49 | |
| 50 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 |
| 51 | #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 |
| 52 | |
| 53 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
| 54 | #define PHYS_SDRAM 0x40000000 |
| 55 | #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ |
| 56 | #define PHYS_SDRAM_2 0xc0000000 |
| 57 | #define PHYS_SDRAM_2_SIZE 0x0 |
| 58 | |
| 59 | #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR |
| 60 | |
| 61 | #define CONFIG_SYS_FSL_USDHC_NUM 2 |
| 62 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
| 63 | |
| 64 | #endif |