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Matthew Fettke9f3b3bb2008-01-24 14:02:32 -06001/*
2 * Configuation settings for the Motorola MC5275EVB board.
3 *
4 * By Arthur Shipkowski <art@videon-central.com>
5 * Copyright (C) 2005 Videon Central, Inc.
6 *
7 * Based off of M5272C3 board code by Josef Baumgartner
8 * <josef.baumgartner@telex.de>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29/*
30 * board/config.h - configuration options, board specific
31 */
32
33#ifndef _M5275EVB_H
34#define _M5275EVB_H
35
36/*
37 * High Level Configuration Options
38 * (easy to change)
39 */
40#define CONFIG_MCF52x2 /* define processor family */
41#define CONFIG_M5275 /* define processor type */
42#define CONFIG_M5275EVB /* define board type */
43
44#define CONFIG_MCFTMR
45
46#define CONFIG_MCFUART
47#define CFG_UART_PORT (0)
TsiChung Liewbd05c6d2008-08-15 16:50:07 +000048#define CONFIG_BAUDRATE 115200
Matthew Fettke9f3b3bb2008-01-24 14:02:32 -060049#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
50
51/* Configuration for environment
52 * Environment is embedded in u-boot in the second sector of the flash
53 */
54#ifndef CONFIG_MONITOR_IS_IN_RAM
55#define CFG_ENV_OFFSET 0x4000
56#define CFG_ENV_SECT_SIZE 0x2000
57#define CFG_ENV_IS_IN_FLASH 1
58#define CFG_ENV_IS_EMBEDDED 1
59#else
60#define CFG_ENV_ADDR 0xffe04000
61#define CFG_ENV_SECT_SIZE 0x2000
62#define CFG_ENV_IS_IN_FLASH 1
63#endif
64
65/*
66 * BOOTP options
67 */
68#define CONFIG_BOOTP_BOOTFILESIZE
69#define CONFIG_BOOTP_BOOTPATH
70#define CONFIG_BOOTP_GATEWAY
71#define CONFIG_BOOTP_HOSTNAME
72
73/* Available command configuration */
74#include <config_cmd_default.h>
75
76#define CONFIG_CMD_PING
77#define CONFIG_CMD_MII
78#define CONFIG_CMD_NET
79#define CONFIG_CMD_ELF
80#define CONFIG_CMD_FLASH
81#define CONFIG_CMD_I2C
82#define CONFIG_CMD_MEMORY
83#define CONFIG_CMD_DHCP
84
85#undef CONFIG_CMD_LOADS
86#undef CONFIG_CMD_LOADB
87
88#define CONFIG_MCFFEC
89#ifdef CONFIG_MCFFEC
90#define CONFIG_NET_MULTI 1
91#define CONFIG_MII 1
TsiChung Liewb3162452008-03-30 01:22:13 -050092#define CONFIG_MII_INIT 1
Matthew Fettke9f3b3bb2008-01-24 14:02:32 -060093#define CFG_DISCOVER_PHY
94#define CFG_RX_ETH_BUFFER 8
95#define CFG_FAULT_ECHO_LINK_DOWN
96#define CFG_FEC0_PINMUX 0
97#define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
98#define CFG_FEC1_PINMUX 0
99#define CFG_FEC1_MIIBASE CFG_FEC1_IOBASE
100#define MCFFEC_TOUT_LOOP 50000
101#define CONFIG_HAS_ETH1
102/* If CFG_DISCOVER_PHY is not defined - hardcoded */
103#ifndef CFG_DISCOVER_PHY
104#define FECDUPLEX FULL
105#define FECSPEED _100BASET
106#else
107#ifndef CFG_FAULT_ECHO_LINK_DOWN
108#define CFG_FAULT_ECHO_LINK_DOWN
109#endif
110#endif
111#endif
112
113/* I2C */
114#define CONFIG_FSL_I2C
115#define CONFIG_HARD_I2C /* I2C with hw support */
116#undef CONFIG_SOFT_I2C
117#define CFG_I2C_SPEED 80000
118#define CFG_I2C_SLAVE 0x7F
119#define CFG_I2C_OFFSET 0x00000300
120#define CFG_IMMR CFG_MBAR
121
122#ifdef CONFIG_MCFFEC
123#define CONFIG_ETHADDR 00:06:3b:01:41:55
124#define CONFIG_ETH1ADDR 00:0e:0c:bc:e5:60
125#endif
126
127#define CFG_PROMPT "-> "
128#define CFG_LONGHELP /* undef to save memory */
129
130#if (CONFIG_CMD_KGDB)
131# define CFG_CBSIZE 1024
132#else
133# define CFG_CBSIZE 256
134#endif
135#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
136#define CFG_MAXARGS 16
137#define CFG_BARGSIZE CFG_CBSIZE
138
139#define CFG_LOAD_ADDR 0x800000
140
141#define CONFIG_BOOTDELAY 5
142#define CONFIG_BOOTCOMMAND "bootm ffe40000"
143#define CFG_MEMTEST_START 0x400
144#define CFG_MEMTEST_END 0x380000
145
146#define CFG_HZ 1000
147#define CFG_CLK 150000000
148
149/*
150 * Low Level Configuration Settings
151 * (address mappings, register initial values, etc.)
152 * You should know what you are doing if you make changes here.
153 */
154
155#define CFG_MBAR 0x40000000
156
157/*-----------------------------------------------------------------------
158 * Definitions for initial stack pointer and data area (in DPRAM)
159 */
160#define CFG_INIT_RAM_ADDR 0x20000000
161#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
162#define CFG_GBL_DATA_SIZE 1000 /* bytes reserved for initial data */
163#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
164#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
165
166/*-----------------------------------------------------------------------
167 * Start addresses for the final memory configuration
168 * (Set up by the startup code)
169 * Please note that CFG_SDRAM_BASE _must_ start at 0
170 */
171#define CFG_SDRAM_BASE 0x00000000
172#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
173#define CFG_FLASH_BASE 0xffe00000
174
175#ifdef CONFIG_MONITOR_IS_IN_RAM
176#define CFG_MONITOR_BASE 0x20000
177#else
178#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
179#endif
180
181#define CFG_MONITOR_LEN 0x20000
182#define CFG_MALLOC_LEN (256 << 10)
183#define CFG_BOOTPARAMS_LEN 64*1024
184
185/*
186 * For booting Linux, the board info and command line data
187 * have to be in the first 8 MB of memory, since this is
188 * the maximum mapped by the Linux kernel during initialization ??
189 */
190#define CFG_BOOTMAPSZ (8 << 20) /* Initial mmap for Linux */
191
192/*-----------------------------------------------------------------------
193 * FLASH organization
194 */
195#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
196#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
197#define CFG_FLASH_ERASE_TOUT 1000
198
199#define CFG_FLASH_CFI 1
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200200#define CONFIG_FLASH_CFI_DRIVER 1
Matthew Fettke9f3b3bb2008-01-24 14:02:32 -0600201#define CFG_FLASH_SIZE 0x200000
202
203/*-----------------------------------------------------------------------
204 * Cache Configuration
205 */
206#define CFG_CACHELINE_SIZE 16
207
208/*-----------------------------------------------------------------------
209 * Memory bank definitions
210 */
211#define CFG_AR0_PRELIM (CFG_FLASH_BASE >> 16)
212#define CFG_CR0_PRELIM 0x1980
213#define CFG_MR0_PRELIM 0x001F0001
214
215#define CFG_AR1_PRELIM 0x3000
216#define CFG_CR1_PRELIM 0x1900
217#define CFG_MR1_PRELIM 0x00070001
218
219/*-----------------------------------------------------------------------
220 * Port configuration
221 */
222#define CFG_FECI2C 0x0FA0
223
224#endif /* _M5275EVB_H */