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git01.mediatek.com / filogic / uboot / 56d150e51a51b9e71e6d1dd4e5f9c33108587853 / . / cpu / mpc85xx / release.S
blob: fbefc2c31e1784bde7dfe9cdf5856b8447604ddb [file] [log] [blame]
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600[diff] [blame]1#include <config.h>
2#include <mpc85xx.h>
3#include <version.h>
4
5#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
6
7#include <ppc_asm.tmpl>
8#include <ppc_defs.h>
9
10#include <asm/cache.h>
11#include <asm/mmu.h>
12
13/* To boot secondary cpus, we need a place for them to start up.
14 * Normally, they start at 0xfffffffc, but that's usually the
15 * firmware, and we don't want to have to run the firmware again.
16 * Instead, the primary cpu will set the BPTR to point here to
17 * this page. We then set up the core, and head to
18 * start_secondary. Note that this means that the code below
19 * must never exceed 1023 instructions (the branch at the end
20 * would then be the 1024th).
21 */
22 .globl __secondary_start_page
23 .align 12
24__secondary_start_page:
25/* First do some preliminary setup */
26 lis r3, HID0_EMCP@h /* enable machine check */
Kumar Gala9f4a6892008-10-23 01:47:38 -0500[diff] [blame]27#ifndef CONFIG_E500MC
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600[diff] [blame]28 ori r3,r3,HID0_TBEN@l /* enable Timebase */
Kumar Gala9f4a6892008-10-23 01:47:38 -0500[diff] [blame]29#endif
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600[diff] [blame]30#ifdef CONFIG_PHYS_64BIT
31 ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
32#endif
33 mtspr SPRN_HID0,r3
34
Kumar Gala9f4a6892008-10-23 01:47:38 -0500[diff] [blame]35#ifndef CONFIG_E500MC
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600[diff] [blame]36 li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
37 mtspr SPRN_HID1,r3
Kumar Gala9f4a6892008-10-23 01:47:38 -0500[diff] [blame]38#endif
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600[diff] [blame]39
40 /* Enable branch prediction */
41 li r3,0x201
42 mtspr SPRN_BUCSR,r3
43
Kumar Galab937cc52008-09-08 08:51:29 -0500[diff] [blame]44 /* Ensure TB is 0 */
45 li r3,0
46 mttbl r3
47 mttbu r3
48
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600[diff] [blame]49 /* Enable/invalidate the I-Cache */
50 mfspr r0,SPRN_L1CSR1
51 ori r0,r0,(L1CSR1_ICFI|L1CSR1_ICE)
52 mtspr SPRN_L1CSR1,r0
53 isync
54
55 /* Enable/invalidate the D-Cache */
56 mfspr r0,SPRN_L1CSR0
57 ori r0,r0,(L1CSR0_DCFI|L1CSR0_DCE)
58 msync
59 isync
60 mtspr SPRN_L1CSR0,r0
61 isync
62
63#define toreset(x) (x - __secondary_start_page + 0xfffff000)
64
65 /* get our PIR to figure out our table entry */
66 lis r3,toreset(__spin_table)@h
67 ori r3,r3,toreset(__spin_table)@l
68
Kumar Galadeeac572008-03-26 08:34:25 -0500[diff] [blame]69 /* r10 has the base address for the entry */
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600[diff] [blame]70 mfspr r0,SPRN_PIR
Kumar Gala9f4a6892008-10-23 01:47:38 -0500[diff] [blame]71#ifdef CONFIG_E500MC
72 rlwinm r4,r0,27,27,31
73#else
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600[diff] [blame]74 mr r4,r0
Kumar Gala9f4a6892008-10-23 01:47:38 -0500[diff] [blame]75#endif
Kumar Galadeeac572008-03-26 08:34:25 -0500[diff] [blame]76 slwi r8,r4,5
77 add r10,r3,r8
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600[diff] [blame]78
Kumar Galae56f2c52009-03-19 09:16:10 -0500[diff] [blame]79#ifdef CONFIG_BACKSIDE_L2_CACHE
80 /* Enable/invalidate the L2 cache */
81 msync
82 lis r3,L2CSR0_L2FI@h
83 mtspr SPRN_L2CSR0,r3
841:
85 mfspr r3,SPRN_L2CSR0
86 andis. r1,r3,L2CSR0_L2FI@h
87 bne 1b
88
89 lis r3,CONFIG_SYS_INIT_L2CSR0@h
90 ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l
91 mtspr SPRN_L2CSR0,r3
92 isync
93#endif
94
Kumar Galadeeac572008-03-26 08:34:25 -0500[diff] [blame]95#define EPAPR_MAGIC (0x45504150)
96#define ENTRY_ADDR_UPPER 0
97#define ENTRY_ADDR_LOWER 4
98#define ENTRY_R3_UPPER 8
99#define ENTRY_R3_LOWER 12
100#define ENTRY_RESV 16
101#define ENTRY_PIR 20
102#define ENTRY_R6_UPPER 24
103#define ENTRY_R6_LOWER 28
104#define ENTRY_SIZE 32
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600[diff] [blame]105
106 /* setup the entry */
Kumar Galadeeac572008-03-26 08:34:25 -0500[diff] [blame]107 li r3,0
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600[diff] [blame]108 li r8,1
Kumar Galadeeac572008-03-26 08:34:25 -0500[diff] [blame]109 stw r0,ENTRY_PIR(r10)
110 stw r3,ENTRY_ADDR_UPPER(r10)
111 stw r8,ENTRY_ADDR_LOWER(r10)
112 stw r3,ENTRY_R3_UPPER(r10)
113 stw r4,ENTRY_R3_LOWER(r10)
114 stw r3,ENTRY_R6_UPPER(r10)
115 stw r3,ENTRY_R6_LOWER(r10)
116
117 /* setup mapping for AS = 1, and jump there */
118 lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
119 mtspr SPRN_MAS0,r11
120 lis r11,(MAS1_VALID|MAS1_IPROT)@h
121 ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
122 mtspr SPRN_MAS1,r11
123 lis r11,(0xfffff000|MAS2_I)@h
124 ori r11,r11,(0xfffff000|MAS2_I)@l
125 mtspr SPRN_MAS2,r11
126 lis r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@h
127 ori r11,r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@l
128 mtspr SPRN_MAS3,r11
129 tlbwe
130
131 bl 1f
1321: mflr r11
133 addi r11,r11,28
134 mfmsr r13
135 ori r12,r13,MSR_IS|MSR_DS@l
136
137 mtspr SPRN_SRR0,r11
138 mtspr SPRN_SRR1,r12
139 rfi
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600[diff] [blame]140
141 /* spin waiting for addr */
Kumar Galadeeac572008-03-26 08:34:25 -0500[diff] [blame]1422:
143 lwz r4,ENTRY_ADDR_LOWER(r10)
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600[diff] [blame]144 andi. r11,r4,1
Kumar Galadeeac572008-03-26 08:34:25 -0500[diff] [blame]145 bne 2b
Kumar Gala398dcd62008-04-28 02:24:04 -0500[diff] [blame]146 isync
Kumar Galadeeac572008-03-26 08:34:25 -0500[diff] [blame]147
148 /* get the upper bits of the addr */
149 lwz r11,ENTRY_ADDR_UPPER(r10)
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600[diff] [blame]150
151 /* setup branch addr */
Kumar Galadeeac572008-03-26 08:34:25 -0500[diff] [blame]152 mtspr SPRN_SRR0,r4
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600[diff] [blame]153
154 /* mark the entry as released */
155 li r8,3
Kumar Galadeeac572008-03-26 08:34:25 -0500[diff] [blame]156 stw r8,ENTRY_ADDR_LOWER(r10)
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600[diff] [blame]157
158 /* mask by ~64M to setup our tlb we will jump to */
Kumar Galadeeac572008-03-26 08:34:25 -0500[diff] [blame]159 rlwinm r12,r4,0,0,5
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600[diff] [blame]160
Kumar Galadeeac572008-03-26 08:34:25 -0500[diff] [blame]161 /* setup r3, r4, r5, r6, r7, r8, r9 */
162 lwz r3,ENTRY_R3_LOWER(r10)
163 li r4,0
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600[diff] [blame]164 li r5,0
Kumar Galadeeac572008-03-26 08:34:25 -0500[diff] [blame]165 lwz r6,ENTRY_R6_LOWER(r10)
166 lis r7,(64*1024*1024)@h
167 li r8,0
168 li r9,0
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600[diff] [blame]169
170 /* load up the pir */
Kumar Galadeeac572008-03-26 08:34:25 -0500[diff] [blame]171 lwz r0,ENTRY_PIR(r10)
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600[diff] [blame]172 mtspr SPRN_PIR,r0
173 mfspr r0,SPRN_PIR
Kumar Galadeeac572008-03-26 08:34:25 -0500[diff] [blame]174 stw r0,ENTRY_PIR(r10)
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600[diff] [blame]175
Haiying Wangf4745512008-12-03 10:08:19 -0500[diff] [blame]176 mtspr IVPR,r12
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600[diff] [blame]177/*
178 * Coming here, we know the cpu has one TLB mapping in TLB1[0]
179 * which maps 0xfffff000-0xffffffff one-to-one. We set up a
180 * second mapping that maps addr 1:1 for 64M, and then we jump to
181 * addr
182 */
Kumar Galadeeac572008-03-26 08:34:25 -0500[diff] [blame]183 lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
184 mtspr SPRN_MAS0,r10
185 lis r10,(MAS1_VALID|MAS1_IPROT)@h
186 ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
187 mtspr SPRN_MAS1,r10
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600[diff] [blame]188 /* WIMGE = 0b00000 for now */
Kumar Galadeeac572008-03-26 08:34:25 -0500[diff] [blame]189 mtspr SPRN_MAS2,r12
190 ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
191 mtspr SPRN_MAS3,r12
192#ifdef CONFIG_ENABLE_36BIT_PHYS
193 mtspr SPRN_MAS7,r11
194#endif
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600[diff] [blame]195 tlbwe
196
197/* Now we have another mapping for this page, so we jump to that
198 * mapping
199 */
Kumar Galadeeac572008-03-26 08:34:25 -0500[diff] [blame]200 mtspr SPRN_SRR1,r13
201 rfi
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600[diff] [blame]202
Kumar Gala398dcd62008-04-28 02:24:04 -0500[diff] [blame]203 .align L1_CACHE_SHIFT
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600[diff] [blame]204 .globl __spin_table
205__spin_table:
Kumar Galaccdeac72008-08-11 11:29:28 -0500[diff] [blame]206 .space CONFIG_NUM_CPUS*ENTRY_SIZE
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600[diff] [blame]207
208 /* Fill in the empty space. The actual reset vector is
209 * the last word of the page */
210__secondary_start_code_end:
211 .space 4092 - (__secondary_start_code_end - __secondary_start_page)
212__secondary_reset_vector:
213 b __secondary_start_page