| York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright 2014, Freescale Semiconductor |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #ifndef _FSL_CH3_MP_H |
| 8 | #define _FSL_CH3_MP_H |
| 9 | |
| 10 | /* |
| 11 | * Each spin table element is defined as |
| 12 | * struct { |
| 13 | * uint64_t entry_addr; |
| 14 | * uint64_t status; |
| 15 | * uint64_t lpid; |
| 16 | * }; |
| 17 | * we pad this struct to 64 bytes so each entry is in its own cacheline |
| 18 | * the actual spin table is an array of these structures |
| 19 | */ |
| 20 | #define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX 0 |
| 21 | #define SPIN_TABLE_ELEM_STATUS_IDX 1 |
| 22 | #define SPIN_TABLE_ELEM_LPID_IDX 2 |
| 23 | #define WORDS_PER_SPIN_TABLE_ENTRY 8 /* pad to 64 bytes */ |
| 24 | #define SPIN_TABLE_ELEM_SIZE 64 |
| 25 | |
| 26 | #define id_to_core(x) ((x & 3) | (x >> 6)) |
| 27 | #ifndef __ASSEMBLY__ |
| 28 | extern u64 __spin_table[]; |
| 29 | extern u64 *secondary_boot_code; |
| 30 | extern size_t __secondary_boot_code_size; |
| 31 | int fsl_lsch3_wake_seconday_cores(void); |
| 32 | void *get_spin_tbl_addr(void); |
| 33 | phys_addr_t determine_mp_bootpg(void); |
| 34 | void secondary_boot_func(void); |
| 35 | #endif |
| 36 | #endif /* _FSL_CH3_MP_H */ |