Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 1 | /* |
| 2 | * initcode.c - Initialize the processor. This is usually entails things |
| 3 | * like external memory, voltage regulators, etc... Note that this file |
| 4 | * cannot make any function calls as it may be executed all by itself by |
| 5 | * the Blackfin's bootrom in LDR format. |
| 6 | * |
Mike Frysinger | 31c7c50 | 2011-05-30 13:47:38 -0400 | [diff] [blame] | 7 | * Copyright (c) 2004-2011 Analog Devices Inc. |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 8 | * |
| 9 | * Licensed under the GPL-2 or later. |
| 10 | */ |
| 11 | |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 12 | #define BFIN_IN_INITCODE |
| 13 | |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 14 | #include <config.h> |
| 15 | #include <asm/blackfin.h> |
| 16 | #include <asm/mach-common/bits/bootrom.h> |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 17 | #include <asm/mach-common/bits/core.h> |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 18 | |
Mike Frysinger | f05105c | 2011-06-06 16:47:31 -0400 | [diff] [blame] | 19 | #define BUG() while (1) { asm volatile("emuexcpt;"); } |
| 20 | |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 21 | #include "serial.h" |
| 22 | |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 23 | #ifndef __ADSPBF60x__ |
| 24 | #include <asm/mach-common/bits/ebiu.h> |
| 25 | #include <asm/mach-common/bits/pll.h> |
| 26 | #else /* __ADSPBF60x__ */ |
| 27 | #include <asm/mach-common/bits/cgu.h> |
| 28 | |
| 29 | #define CONFIG_BFIN_GET_DCLK_M \ |
| 30 | ((CONFIG_CLKIN_HZ*CONFIG_VCO_MULT)/(CONFIG_DCLK_DIV*1000000)) |
| 31 | |
| 32 | #ifndef CONFIG_DMC_DDRCFG |
| 33 | #if ((CONFIG_BFIN_GET_DCLK_M != 125) && \ |
| 34 | (CONFIG_BFIN_GET_DCLK_M != 133) && \ |
| 35 | (CONFIG_BFIN_GET_DCLK_M != 150) && \ |
| 36 | (CONFIG_BFIN_GET_DCLK_M != 166) && \ |
| 37 | (CONFIG_BFIN_GET_DCLK_M != 200) && \ |
| 38 | (CONFIG_BFIN_GET_DCLK_M != 225) && \ |
| 39 | (CONFIG_BFIN_GET_DCLK_M != 250)) |
| 40 | #error "DDR2 CLK must be in (125, 133, 150, 166, 200, 225, 250)MHz" |
| 41 | #endif |
| 42 | #endif |
| 43 | |
| 44 | /* DMC control bits */ |
| 45 | #define SRREQ 0x8 |
| 46 | |
| 47 | /* DMC status bits */ |
| 48 | #define IDLE 0x1 |
| 49 | #define MEMINITDONE 0x4 |
| 50 | #define SRACK 0x8 |
| 51 | #define PDACK 0x10 |
| 52 | #define DPDACK 0x20 |
| 53 | #define DLLCALDONE 0x2000 |
| 54 | #define PENDREF 0xF0000 |
| 55 | #define PHYRDPHASE 0xF00000 |
| 56 | #define PHYRDPHASE_OFFSET 20 |
| 57 | |
| 58 | /* DMC DLL control bits */ |
| 59 | #define DLLCALRDCNT 0xFF |
| 60 | #define DATACYC_OFFSET 8 |
| 61 | |
| 62 | struct ddr_config { |
| 63 | u32 ddr_clk; |
| 64 | u32 dmc_ddrctl; |
| 65 | u32 dmc_ddrcfg; |
| 66 | u32 dmc_ddrtr0; |
| 67 | u32 dmc_ddrtr1; |
| 68 | u32 dmc_ddrtr2; |
| 69 | u32 dmc_ddrmr; |
| 70 | u32 dmc_ddrmr1; |
| 71 | }; |
| 72 | |
| 73 | static struct ddr_config ddr_config_table[] = { |
| 74 | [0] = { |
| 75 | .ddr_clk = 125, /* 125MHz */ |
| 76 | .dmc_ddrctl = 0x00000904, |
| 77 | .dmc_ddrcfg = 0x00000422, |
| 78 | .dmc_ddrtr0 = 0x20705212, |
| 79 | .dmc_ddrtr1 = 0x201003CF, |
| 80 | .dmc_ddrtr2 = 0x00320107, |
| 81 | .dmc_ddrmr = 0x00000422, |
| 82 | .dmc_ddrmr1 = 0x4, |
| 83 | }, |
| 84 | [1] = { |
| 85 | .ddr_clk = 133, /* 133MHz */ |
| 86 | .dmc_ddrctl = 0x00000904, |
| 87 | .dmc_ddrcfg = 0x00000422, |
| 88 | .dmc_ddrtr0 = 0x20806313, |
| 89 | .dmc_ddrtr1 = 0x2013040D, |
| 90 | .dmc_ddrtr2 = 0x00320108, |
| 91 | .dmc_ddrmr = 0x00000632, |
| 92 | .dmc_ddrmr1 = 0x4, |
| 93 | }, |
| 94 | [2] = { |
| 95 | .ddr_clk = 150, /* 150MHz */ |
| 96 | .dmc_ddrctl = 0x00000904, |
| 97 | .dmc_ddrcfg = 0x00000422, |
| 98 | .dmc_ddrtr0 = 0x20A07323, |
| 99 | .dmc_ddrtr1 = 0x20160492, |
| 100 | .dmc_ddrtr2 = 0x00320209, |
| 101 | .dmc_ddrmr = 0x00000632, |
| 102 | .dmc_ddrmr1 = 0x4, |
| 103 | }, |
| 104 | [3] = { |
| 105 | .ddr_clk = 166, /* 166MHz */ |
| 106 | .dmc_ddrctl = 0x00000904, |
| 107 | .dmc_ddrcfg = 0x00000422, |
| 108 | .dmc_ddrtr0 = 0x20A07323, |
| 109 | .dmc_ddrtr1 = 0x2016050E, |
| 110 | .dmc_ddrtr2 = 0x00320209, |
| 111 | .dmc_ddrmr = 0x00000632, |
| 112 | .dmc_ddrmr1 = 0x4, |
| 113 | }, |
| 114 | [4] = { |
| 115 | .ddr_clk = 200, /* 200MHz */ |
| 116 | .dmc_ddrctl = 0x00000904, |
| 117 | .dmc_ddrcfg = 0x00000422, |
| 118 | .dmc_ddrtr0 = 0x20a07323, |
| 119 | .dmc_ddrtr1 = 0x2016050f, |
| 120 | .dmc_ddrtr2 = 0x00320509, |
| 121 | .dmc_ddrmr = 0x00000632, |
| 122 | .dmc_ddrmr1 = 0x4, |
| 123 | }, |
| 124 | [5] = { |
| 125 | .ddr_clk = 225, /* 225MHz */ |
| 126 | .dmc_ddrctl = 0x00000904, |
| 127 | .dmc_ddrcfg = 0x00000422, |
| 128 | .dmc_ddrtr0 = 0x20E0A424, |
| 129 | .dmc_ddrtr1 = 0x302006DB, |
| 130 | .dmc_ddrtr2 = 0x0032020D, |
| 131 | .dmc_ddrmr = 0x00000842, |
| 132 | .dmc_ddrmr1 = 0x4, |
| 133 | }, |
| 134 | [6] = { |
| 135 | .ddr_clk = 250, /* 250MHz */ |
| 136 | .dmc_ddrctl = 0x00000904, |
| 137 | .dmc_ddrcfg = 0x00000422, |
| 138 | .dmc_ddrtr0 = 0x20E0A424, |
| 139 | .dmc_ddrtr1 = 0x3020079E, |
| 140 | .dmc_ddrtr2 = 0x0032050D, |
| 141 | .dmc_ddrmr = 0x00000842, |
| 142 | .dmc_ddrmr1 = 0x4, |
| 143 | }, |
| 144 | }; |
| 145 | #endif /* __ADSPBF60x__ */ |
| 146 | |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 147 | __attribute__((always_inline)) |
Mike Frysinger | 8445130 | 2008-12-10 12:33:54 -0500 | [diff] [blame] | 148 | static inline void serial_init(void) |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 149 | { |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 150 | uint32_t uart_base = UART_BASE; |
Mike Frysinger | 53ba322 | 2011-04-29 23:23:28 -0400 | [diff] [blame] | 151 | |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 152 | #if defined(__ADSPBF54x__) || defined(__ADSPBF60x__) |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 153 | # ifdef BFIN_BOOT_UART_USE_RTS |
| 154 | # define BFIN_UART_USE_RTS 1 |
| 155 | # else |
| 156 | # define BFIN_UART_USE_RTS 0 |
| 157 | # endif |
| 158 | if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) { |
| 159 | size_t i; |
| 160 | |
| 161 | /* force RTS rather than relying on auto RTS */ |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 162 | #if BFIN_UART_HW_VER < 4 |
Mike Frysinger | 3b7ed5a | 2009-11-12 18:42:53 -0500 | [diff] [blame] | 163 | bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) | FCPOL); |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 164 | #else |
| 165 | bfin_write32(&pUART->control, bfin_read32(&pUART->control) | |
| 166 | FCPOL); |
| 167 | #endif |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 168 | |
| 169 | /* Wait for the line to clear up. We cannot rely on UART |
| 170 | * registers as none of them reflect the status of the RSR. |
| 171 | * Instead, we'll sleep for ~10 bit times at 9600 baud. |
| 172 | * We can precalc things here by assuming boot values for |
| 173 | * PLL rather than loading registers and calculating. |
| 174 | * baud = SCLK / (16 ^ (1 - EDBO) * Divisor) |
| 175 | * EDB0 = 0 |
| 176 | * Divisor = (SCLK / baud) / 16 |
| 177 | * SCLK = baud * 16 * Divisor |
| 178 | * SCLK = (0x14 * CONFIG_CLKIN_HZ) / 5 |
| 179 | * CCLK = (16 * Divisor * 5) * (9600 / 10) |
| 180 | * In reality, this will probably be just about 1 second delay, |
| 181 | * so assuming 9600 baud is OK (both as a very low and too high |
| 182 | * speed as this will buffer things enough). |
| 183 | */ |
| 184 | #define _NUMBITS (10) /* how many bits to delay */ |
| 185 | #define _LOWBAUD (9600) /* low baud rate */ |
| 186 | #define _SCLK ((0x14 * CONFIG_CLKIN_HZ) / 5) /* SCLK based on PLL */ |
| 187 | #define _DIVISOR ((_SCLK / _LOWBAUD) / 16) /* UART DLL/DLH */ |
| 188 | #define _NUMINS (3) /* how many instructions in loop */ |
| 189 | #define _CCLK (((16 * _DIVISOR * 5) * (_LOWBAUD / _NUMBITS)) / _NUMINS) |
| 190 | i = _CCLK; |
| 191 | while (i--) |
| 192 | asm volatile("" : : : "memory"); |
| 193 | } |
| 194 | #endif |
| 195 | |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 196 | if (BFIN_DEBUG_EARLY_SERIAL) { |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 197 | int enabled = serial_early_enabled(uart_base); |
| 198 | |
Mike Frysinger | 53ba322 | 2011-04-29 23:23:28 -0400 | [diff] [blame] | 199 | serial_early_init(uart_base); |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 200 | |
| 201 | /* If the UART is off, that means we need to program |
| 202 | * the baud rate ourselves initially. |
| 203 | */ |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 204 | if (!enabled) |
Mike Frysinger | 53ba322 | 2011-04-29 23:23:28 -0400 | [diff] [blame] | 205 | serial_early_set_baud(uart_base, CONFIG_BAUDRATE); |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 206 | } |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 207 | } |
| 208 | |
| 209 | __attribute__((always_inline)) |
| 210 | static inline void serial_deinit(void) |
| 211 | { |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 212 | #if defined(__ADSPBF54x__) || defined(__ADSPBF60x__) |
| 213 | uint32_t uart_base = UART_BASE; |
Mike Frysinger | 53ba322 | 2011-04-29 23:23:28 -0400 | [diff] [blame] | 214 | |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 215 | if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) { |
| 216 | /* clear forced RTS rather than relying on auto RTS */ |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 217 | #if BFIN_UART_HW_VER < 4 |
Mike Frysinger | 3b7ed5a | 2009-11-12 18:42:53 -0500 | [diff] [blame] | 218 | bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL); |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 219 | #else |
| 220 | bfin_write32(&pUART->control, bfin_read32(&pUART->control) & |
| 221 | ~FCPOL); |
| 222 | #endif |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 223 | } |
| 224 | #endif |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 225 | } |
| 226 | |
| 227 | __attribute__((always_inline)) |
| 228 | static inline void serial_putc(char c) |
| 229 | { |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 230 | uint32_t uart_base = UART_BASE; |
Mike Frysinger | 53ba322 | 2011-04-29 23:23:28 -0400 | [diff] [blame] | 231 | |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 232 | if (!BFIN_DEBUG_EARLY_SERIAL) |
| 233 | return; |
| 234 | |
| 235 | if (c == '\n') |
Mike Frysinger | e7851d0 | 2009-04-24 23:22:48 -0400 | [diff] [blame] | 236 | serial_putc('\r'); |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 237 | |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 238 | bfin_write(&pUART->thr, c); |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 239 | |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 240 | while (!(_lsr_read(pUART) & TEMT)) |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 241 | continue; |
| 242 | } |
| 243 | |
Mike Frysinger | 31c7c50 | 2011-05-30 13:47:38 -0400 | [diff] [blame] | 244 | #include "initcode.h" |
| 245 | |
Mike Frysinger | eb2a399 | 2010-05-05 02:07:44 -0400 | [diff] [blame] | 246 | __attribute__((always_inline)) static inline void |
| 247 | program_nmi_handler(void) |
| 248 | { |
| 249 | u32 tmp1, tmp2; |
| 250 | |
| 251 | /* Older bootroms don't create a dummy NMI handler, |
| 252 | * so make one ourselves ASAP in case it fires. |
| 253 | */ |
| 254 | if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS && !ANOMALY_05000219) |
| 255 | return; |
| 256 | |
| 257 | asm volatile ( |
| 258 | "%0 = RETS;" /* Save current RETS */ |
| 259 | "CALL 1f;" /* Figure out current PC */ |
| 260 | "RTN;" /* The simple NMI handler */ |
| 261 | "1:" |
| 262 | "%1 = RETS;" /* Load addr of NMI handler */ |
| 263 | "RETS = %0;" /* Restore RETS */ |
| 264 | "[%2] = %1;" /* Write NMI handler */ |
| 265 | : "=r"(tmp1), "=r"(tmp2) : "ab"(EVT2) |
| 266 | ); |
| 267 | } |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 268 | |
Mike Frysinger | 2c00197 | 2008-12-09 17:21:08 -0500 | [diff] [blame] | 269 | /* Max SCLK can be 133MHz ... dividing that by (2*4) gives |
| 270 | * us a freq of 16MHz for SPI which should generally be |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 271 | * slow enough for the slow reads the bootrom uses. |
| 272 | */ |
Mike Frysinger | 2c00197 | 2008-12-09 17:21:08 -0500 | [diff] [blame] | 273 | #if !defined(CONFIG_SPI_FLASH_SLOW_READ) && \ |
| 274 | ((defined(__ADSPBF52x__) && __SILICON_REVISION__ >= 2) || \ |
| 275 | (defined(__ADSPBF54x__) && __SILICON_REVISION__ >= 1)) |
| 276 | # define BOOTROM_SUPPORTS_SPI_FAST_READ 1 |
| 277 | #else |
| 278 | # define BOOTROM_SUPPORTS_SPI_FAST_READ 0 |
| 279 | #endif |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 280 | #ifndef CONFIG_SPI_BAUD_INITBLOCK |
Mike Frysinger | 2c00197 | 2008-12-09 17:21:08 -0500 | [diff] [blame] | 281 | # define CONFIG_SPI_BAUD_INITBLOCK (BOOTROM_SUPPORTS_SPI_FAST_READ ? 2 : 4) |
| 282 | #endif |
| 283 | #ifdef SPI0_BAUD |
| 284 | # define bfin_write_SPI_BAUD bfin_write_SPI0_BAUD |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 285 | #endif |
| 286 | |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 287 | #ifdef __ADSPBF60x__ |
| 288 | |
| 289 | #ifndef CONFIG_CGU_CTL_VAL |
| 290 | # define CONFIG_CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CONFIG_CLKIN_HALF) |
| 291 | #endif |
| 292 | |
| 293 | #ifndef CONFIG_CGU_DIV_VAL |
| 294 | # define CONFIG_CGU_DIV_VAL \ |
| 295 | ((CONFIG_CCLK_DIV << CSEL_P) | \ |
| 296 | (CONFIG_SCLK0_DIV << S0SEL_P) | \ |
| 297 | (CONFIG_SCLK_DIV << SYSSEL_P) | \ |
| 298 | (CONFIG_SCLK1_DIV << S1SEL_P) | \ |
| 299 | (CONFIG_DCLK_DIV << DSEL_P) | \ |
| 300 | (CONFIG_OCLK_DIV << OSEL_P)) |
| 301 | #endif |
| 302 | |
| 303 | #else /* __ADSPBF60x__ */ |
| 304 | |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 305 | /* PLL_DIV defines */ |
| 306 | #ifndef CONFIG_PLL_DIV_VAL |
| 307 | # if (CONFIG_CCLK_DIV == 1) |
| 308 | # define CONFIG_CCLK_ACT_DIV CCLK_DIV1 |
| 309 | # elif (CONFIG_CCLK_DIV == 2) |
| 310 | # define CONFIG_CCLK_ACT_DIV CCLK_DIV2 |
| 311 | # elif (CONFIG_CCLK_DIV == 4) |
| 312 | # define CONFIG_CCLK_ACT_DIV CCLK_DIV4 |
| 313 | # elif (CONFIG_CCLK_DIV == 8) |
| 314 | # define CONFIG_CCLK_ACT_DIV CCLK_DIV8 |
| 315 | # else |
| 316 | # define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly |
| 317 | # endif |
| 318 | # define CONFIG_PLL_DIV_VAL (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV) |
| 319 | #endif |
| 320 | |
| 321 | #ifndef CONFIG_PLL_LOCKCNT_VAL |
| 322 | # define CONFIG_PLL_LOCKCNT_VAL 0x0300 |
| 323 | #endif |
| 324 | |
| 325 | #ifndef CONFIG_PLL_CTL_VAL |
Mike Frysinger | c13fc44 | 2008-06-01 01:26:29 -0400 | [diff] [blame] | 326 | # define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF) |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 327 | #endif |
| 328 | |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 329 | /* Make sure our voltage value is sane so we don't blow up! */ |
| 330 | #ifndef CONFIG_VR_CTL_VAL |
| 331 | # define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV) |
| 332 | # if defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__) |
| 333 | # define CCLK_VLEV_120 400000000 |
| 334 | # define CCLK_VLEV_125 533000000 |
| 335 | # elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) |
| 336 | # define CCLK_VLEV_120 401000000 |
| 337 | # define CCLK_VLEV_125 401000000 |
| 338 | # elif defined(__ADSPBF561__) |
| 339 | # define CCLK_VLEV_120 300000000 |
| 340 | # define CCLK_VLEV_125 501000000 |
| 341 | # endif |
| 342 | # if BFIN_CCLK < CCLK_VLEV_120 |
| 343 | # define CONFIG_VR_CTL_VLEV VLEV_120 |
| 344 | # elif BFIN_CCLK < CCLK_VLEV_125 |
| 345 | # define CONFIG_VR_CTL_VLEV VLEV_125 |
| 346 | # else |
| 347 | # define CONFIG_VR_CTL_VLEV VLEV_130 |
| 348 | # endif |
| 349 | # if defined(__ADSPBF52x__) /* TBD; use default */ |
| 350 | # undef CONFIG_VR_CTL_VLEV |
| 351 | # define CONFIG_VR_CTL_VLEV VLEV_110 |
| 352 | # elif defined(__ADSPBF54x__) /* TBD; use default */ |
| 353 | # undef CONFIG_VR_CTL_VLEV |
| 354 | # define CONFIG_VR_CTL_VLEV VLEV_120 |
Mike Frysinger | a7ab10a | 2008-10-11 21:54:00 -0400 | [diff] [blame] | 355 | # elif defined(__ADSPBF538__) || defined(__ADSPBF539__) /* TBD; use default */ |
| 356 | # undef CONFIG_VR_CTL_VLEV |
| 357 | # define CONFIG_VR_CTL_VLEV VLEV_125 |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 358 | # endif |
| 359 | |
| 360 | # ifdef CONFIG_BFIN_MAC |
| 361 | # define CONFIG_VR_CTL_CLKBUF CLKBUFOE |
| 362 | # else |
| 363 | # define CONFIG_VR_CTL_CLKBUF 0 |
| 364 | # endif |
| 365 | |
| 366 | # if defined(__ADSPBF52x__) |
| 367 | # define CONFIG_VR_CTL_FREQ FREQ_1000 |
| 368 | # else |
| 369 | # define CONFIG_VR_CTL_FREQ (GAIN_20 | FREQ_1000) |
| 370 | # endif |
| 371 | |
| 372 | # define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ) |
| 373 | #endif |
| 374 | |
Mike Frysinger | 446d570 | 2008-10-11 21:56:08 -0400 | [diff] [blame] | 375 | /* some parts do not have an on-chip voltage regulator */ |
| 376 | #if defined(__ADSPBF51x__) |
| 377 | # define CONFIG_HAS_VR 0 |
| 378 | # undef CONFIG_VR_CTL_VAL |
| 379 | # define CONFIG_VR_CTL_VAL 0 |
| 380 | #else |
| 381 | # define CONFIG_HAS_VR 1 |
| 382 | #endif |
| 383 | |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 384 | #if CONFIG_MEM_SIZE |
Mike Frysinger | b0f1468 | 2008-06-01 01:28:24 -0400 | [diff] [blame] | 385 | #ifndef EBIU_RSTCTL |
| 386 | /* Blackfin with SDRAM */ |
| 387 | #ifndef CONFIG_EBIU_SDBCTL_VAL |
| 388 | # if CONFIG_MEM_SIZE == 16 |
| 389 | # define CONFIG_EBSZ_VAL EBSZ_16 |
| 390 | # elif CONFIG_MEM_SIZE == 32 |
| 391 | # define CONFIG_EBSZ_VAL EBSZ_32 |
| 392 | # elif CONFIG_MEM_SIZE == 64 |
| 393 | # define CONFIG_EBSZ_VAL EBSZ_64 |
| 394 | # elif CONFIG_MEM_SIZE == 128 |
| 395 | # define CONFIG_EBSZ_VAL EBSZ_128 |
| 396 | # elif CONFIG_MEM_SIZE == 256 |
| 397 | # define CONFIG_EBSZ_VAL EBSZ_256 |
| 398 | # elif CONFIG_MEM_SIZE == 512 |
| 399 | # define CONFIG_EBSZ_VAL EBSZ_512 |
| 400 | # else |
| 401 | # error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_SIZE |
| 402 | # endif |
| 403 | # if CONFIG_MEM_ADD_WDTH == 8 |
| 404 | # define CONFIG_EBCAW_VAL EBCAW_8 |
| 405 | # elif CONFIG_MEM_ADD_WDTH == 9 |
| 406 | # define CONFIG_EBCAW_VAL EBCAW_9 |
| 407 | # elif CONFIG_MEM_ADD_WDTH == 10 |
| 408 | # define CONFIG_EBCAW_VAL EBCAW_10 |
| 409 | # elif CONFIG_MEM_ADD_WDTH == 11 |
| 410 | # define CONFIG_EBCAW_VAL EBCAW_11 |
| 411 | # else |
| 412 | # error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_ADD_WDTH |
| 413 | # endif |
| 414 | # define CONFIG_EBIU_SDBCTL_VAL (CONFIG_EBCAW_VAL | CONFIG_EBSZ_VAL | EBE) |
| 415 | #endif |
| 416 | #endif |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 417 | #endif |
Mike Frysinger | b0f1468 | 2008-06-01 01:28:24 -0400 | [diff] [blame] | 418 | |
Mike Frysinger | 8c10be4 | 2009-04-04 08:40:13 -0400 | [diff] [blame] | 419 | /* Conflicting Column Address Widths Causes SDRAM Errors: |
| 420 | * EB2CAW and EB3CAW must be the same |
| 421 | */ |
| 422 | #if ANOMALY_05000362 |
| 423 | # if ((CONFIG_EBIU_SDBCTL_VAL & 0x30000000) >> 8) != (CONFIG_EBIU_SDBCTL_VAL & 0x00300000) |
| 424 | # error "Anomaly 05000362: EB2CAW and EB3CAW must be the same" |
| 425 | # endif |
| 426 | #endif |
| 427 | |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 428 | #endif /* __ADSPBF60x__ */ |
| 429 | |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 430 | __attribute__((always_inline)) static inline void |
| 431 | program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB) |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 432 | { |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 433 | serial_putc('a'); |
Mike Frysinger | 0198676 | 2009-02-13 17:10:58 -0500 | [diff] [blame] | 434 | |
Mike Frysinger | 8445130 | 2008-12-10 12:33:54 -0500 | [diff] [blame] | 435 | /* Save the clock pieces that are used in baud rate calculation */ |
Mike Frysinger | 8445130 | 2008-12-10 12:33:54 -0500 | [diff] [blame] | 436 | if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) { |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 437 | serial_putc('b'); |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 438 | #ifdef __ADSPBF60x__ |
| 439 | *sdivB = bfin_read_CGU_DIV(); |
| 440 | *sdivB = ((*sdivB >> 8) & 0x1f) * ((*sdivB >> 5) & 0x7); |
| 441 | *vcoB = (bfin_read_CGU_CTL() >> 8) & 0x7f; |
| 442 | #else |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 443 | *sdivB = bfin_read_PLL_DIV() & 0xf; |
| 444 | *vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f; |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 445 | #endif |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 446 | *divB = serial_early_get_div(); |
| 447 | serial_putc('c'); |
Mike Frysinger | 8445130 | 2008-12-10 12:33:54 -0500 | [diff] [blame] | 448 | } |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 449 | |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 450 | serial_putc('d'); |
Mike Frysinger | 0198676 | 2009-02-13 17:10:58 -0500 | [diff] [blame] | 451 | |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 452 | #ifdef CONFIG_HW_WATCHDOG |
| 453 | # ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE |
| 454 | # define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000 |
| 455 | # endif |
| 456 | /* Program the watchdog with an initial timeout of ~20 seconds. |
| 457 | * Hopefully that should be long enough to load the u-boot LDR |
| 458 | * (from wherever) and then the common u-boot code can take over. |
| 459 | * In bypass mode, the start.S would have already set a much lower |
| 460 | * timeout, so don't clobber that. |
| 461 | */ |
| 462 | if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) { |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 463 | serial_putc('e'); |
Bob Liu | 6cdbce6 | 2011-12-27 15:05:53 +0800 | [diff] [blame] | 464 | #ifdef __ADSPBF60x__ |
| 465 | bfin_write_SEC_GCTL(0x2); |
| 466 | SSYNC(); |
| 467 | bfin_write_SEC_FCTL(0xc1); |
| 468 | bfin_write_SEC_SCTL(2, bfin_read_SEC_SCTL(2) | 0x6); |
| 469 | |
| 470 | bfin_write_SEC_CCTL(0x2); |
| 471 | SSYNC(); |
| 472 | bfin_write_SEC_GCTL(0x1); |
| 473 | bfin_write_SEC_CCTL(0x1); |
| 474 | #endif |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 475 | bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE)); |
Bob Liu | 6cdbce6 | 2011-12-27 15:05:53 +0800 | [diff] [blame] | 476 | #if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 477 | bfin_write_WDOG_CTL(0); |
Bob Liu | 6cdbce6 | 2011-12-27 15:05:53 +0800 | [diff] [blame] | 478 | #endif |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 479 | serial_putc('f'); |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 480 | } |
| 481 | #endif |
| 482 | |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 483 | serial_putc('g'); |
| 484 | |
| 485 | /* Blackfin bootroms use the SPI slow read opcode instead of the SPI |
| 486 | * fast read, so we need to slow down the SPI clock a lot more during |
| 487 | * boot. Once we switch over to u-boot's SPI flash driver, we'll |
| 488 | * increase the speed appropriately. |
| 489 | */ |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 490 | #ifdef SPI_BAUD |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 491 | if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) { |
| 492 | serial_putc('h'); |
| 493 | if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4) |
| 494 | bs->dFlags |= BFLAG_FASTREAD; |
| 495 | bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK); |
| 496 | serial_putc('i'); |
| 497 | } |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 498 | #endif |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 499 | |
| 500 | serial_putc('j'); |
| 501 | } |
| 502 | |
| 503 | __attribute__((always_inline)) static inline bool |
| 504 | maybe_self_refresh(ADI_BOOT_DATA *bs) |
| 505 | { |
| 506 | serial_putc('a'); |
| 507 | |
| 508 | if (!CONFIG_MEM_SIZE) |
| 509 | return false; |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 510 | |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 511 | #ifdef __ADSPBF60x__ |
Steven Miao | e8505bb | 2012-03-31 16:01:50 +0800 | [diff] [blame] | 512 | /* resume from hibernate, return false let ddr initialize */ |
| 513 | if ((bfin_read32(DPM0_STAT) & 0xF0) == 0x50) { |
| 514 | serial_putc('b'); |
| 515 | return false; |
| 516 | } |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 517 | |
| 518 | #else /* __ADSPBF60x__ */ |
| 519 | |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 520 | /* If external memory is enabled, put it into self refresh first. */ |
Mike Frysinger | 134db0d | 2010-12-17 15:25:09 -0500 | [diff] [blame] | 521 | #if defined(EBIU_RSTCTL) |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 522 | if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) { |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 523 | serial_putc('b'); |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 524 | bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ); |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 525 | return true; |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 526 | } |
Mike Frysinger | 134db0d | 2010-12-17 15:25:09 -0500 | [diff] [blame] | 527 | #elif defined(EBIU_SDGCTL) |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 528 | if (bfin_read_EBIU_SDBCTL() & EBE) { |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 529 | serial_putc('b'); |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 530 | bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS); |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 531 | return true; |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 532 | } |
| 533 | #endif |
| 534 | |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 535 | #endif /* __ADSPBF60x__ */ |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 536 | serial_putc('c'); |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 537 | |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 538 | return false; |
| 539 | } |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 540 | |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 541 | __attribute__((always_inline)) static inline u16 |
| 542 | program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs) |
| 543 | { |
| 544 | u16 vr_ctl; |
| 545 | |
| 546 | serial_putc('a'); |
| 547 | |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 548 | #ifdef __ADSPBF60x__ |
| 549 | if (bfin_read_DMC0_STAT() & MEMINITDONE) { |
| 550 | bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ); |
| 551 | SSYNC(); |
| 552 | while (!(bfin_read_DMC0_STAT() & SRACK)) |
| 553 | continue; |
| 554 | } |
| 555 | |
| 556 | /* Don't set the same value of MSEL and DF to CGU_CTL */ |
| 557 | if ((bfin_read_CGU_CTL() & (MSEL_MASK | DF_MASK)) |
| 558 | != CONFIG_CGU_CTL_VAL) { |
| 559 | bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL); |
| 560 | bfin_write_CGU_CTL(CONFIG_CGU_CTL_VAL); |
| 561 | while ((bfin_read_CGU_STAT() & (CLKSALGN | PLLBP)) || |
| 562 | !(bfin_read_CGU_STAT() & PLLLK)) |
| 563 | continue; |
| 564 | } |
| 565 | |
| 566 | bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL | UPDT); |
| 567 | while (bfin_read_CGU_STAT() & CLKSALGN) |
| 568 | continue; |
| 569 | |
| 570 | if (bfin_read_DMC0_STAT() & MEMINITDONE) { |
| 571 | bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ); |
| 572 | SSYNC(); |
| 573 | while (bfin_read_DMC0_STAT() & SRACK) |
| 574 | continue; |
| 575 | } |
| 576 | |
| 577 | #else /* __ADSPBF60x__ */ |
| 578 | |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 579 | vr_ctl = bfin_read_VR_CTL(); |
| 580 | |
| 581 | serial_putc('b'); |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 582 | |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 583 | /* If we're entering self refresh, make sure it has happened. */ |
| 584 | if (put_into_srfs) |
Mike Frysinger | 134db0d | 2010-12-17 15:25:09 -0500 | [diff] [blame] | 585 | #if defined(EBIU_RSTCTL) |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 586 | while (!(bfin_read_EBIU_RSTCTL() & SRACK)) |
Mike Frysinger | 134db0d | 2010-12-17 15:25:09 -0500 | [diff] [blame] | 587 | continue; |
| 588 | #elif defined(EBIU_SDGCTL) |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 589 | while (!(bfin_read_EBIU_SDSTAT() & SDSRA)) |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 590 | continue; |
Mike Frysinger | 134db0d | 2010-12-17 15:25:09 -0500 | [diff] [blame] | 591 | #else |
| 592 | ; |
| 593 | #endif |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 594 | |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 595 | serial_putc('c'); |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 596 | |
Mike Frysinger | 1114d0e | 2008-06-01 01:29:57 -0400 | [diff] [blame] | 597 | /* With newer bootroms, we use the helper function to set up |
| 598 | * the memory controller. Older bootroms lacks such helpers |
| 599 | * so we do it ourselves. |
| 600 | */ |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 601 | if (!ANOMALY_05000386) { |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 602 | serial_putc('d'); |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 603 | |
Mike Frysinger | e8aea4a | 2009-04-04 08:29:55 -0400 | [diff] [blame] | 604 | /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */ |
Mike Frysinger | 1114d0e | 2008-06-01 01:29:57 -0400 | [diff] [blame] | 605 | ADI_SYSCTRL_VALUES memory_settings; |
Mike Frysinger | b91d7d9 | 2010-10-14 14:29:17 -0400 | [diff] [blame] | 606 | uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_LOCKCNT; |
| 607 | if (!ANOMALY_05000440) |
| 608 | actions |= SYSCTRL_PLLDIV; |
Mike Frysinger | 446d570 | 2008-10-11 21:56:08 -0400 | [diff] [blame] | 609 | if (CONFIG_HAS_VR) { |
| 610 | actions |= SYSCTRL_VRCTL; |
| 611 | if (CONFIG_VR_CTL_VAL & FREQ_MASK) |
| 612 | actions |= SYSCTRL_INTVOLTAGE; |
| 613 | else |
| 614 | actions |= SYSCTRL_EXTVOLTAGE; |
| 615 | memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL; |
| 616 | } else |
| 617 | actions |= SYSCTRL_EXTVOLTAGE; |
Mike Frysinger | 1114d0e | 2008-06-01 01:29:57 -0400 | [diff] [blame] | 618 | memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL; |
| 619 | memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL; |
| 620 | memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL; |
Mike Frysinger | f9d004b | 2008-12-06 18:06:58 -0500 | [diff] [blame] | 621 | #if ANOMALY_05000432 |
| 622 | bfin_write_SIC_IWR1(0); |
| 623 | #endif |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 624 | serial_putc('e'); |
Mike Frysinger | 446d570 | 2008-10-11 21:56:08 -0400 | [diff] [blame] | 625 | bfrom_SysControl(actions, &memory_settings, NULL); |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 626 | serial_putc('f'); |
Mike Frysinger | b91d7d9 | 2010-10-14 14:29:17 -0400 | [diff] [blame] | 627 | if (ANOMALY_05000440) |
| 628 | bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL); |
Mike Frysinger | f9d004b | 2008-12-06 18:06:58 -0500 | [diff] [blame] | 629 | #if ANOMALY_05000432 |
| 630 | bfin_write_SIC_IWR1(-1); |
| 631 | #endif |
Mike Frysinger | 1f1ac0a | 2009-04-04 08:09:24 -0400 | [diff] [blame] | 632 | #if ANOMALY_05000171 |
| 633 | bfin_write_SICA_IWR0(-1); |
| 634 | bfin_write_SICA_IWR1(-1); |
| 635 | #endif |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 636 | serial_putc('g'); |
Mike Frysinger | 1114d0e | 2008-06-01 01:29:57 -0400 | [diff] [blame] | 637 | } else { |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 638 | serial_putc('h'); |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 639 | |
| 640 | /* Disable all peripheral wakeups except for the PLL event. */ |
| 641 | #ifdef SIC_IWR0 |
| 642 | bfin_write_SIC_IWR0(1); |
| 643 | bfin_write_SIC_IWR1(0); |
| 644 | # ifdef SIC_IWR2 |
| 645 | bfin_write_SIC_IWR2(0); |
| 646 | # endif |
| 647 | #elif defined(SICA_IWR0) |
| 648 | bfin_write_SICA_IWR0(1); |
| 649 | bfin_write_SICA_IWR1(0); |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 650 | #elif defined(SIC_IWR) |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 651 | bfin_write_SIC_IWR(1); |
| 652 | #endif |
| 653 | |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 654 | serial_putc('i'); |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 655 | |
Mike Frysinger | e8aea4a | 2009-04-04 08:29:55 -0400 | [diff] [blame] | 656 | /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */ |
Mike Frysinger | 1114d0e | 2008-06-01 01:29:57 -0400 | [diff] [blame] | 657 | bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL); |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 658 | |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 659 | serial_putc('j'); |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 660 | |
Mike Frysinger | 1114d0e | 2008-06-01 01:29:57 -0400 | [diff] [blame] | 661 | /* Only reprogram when needed to avoid triggering unnecessary |
| 662 | * PLL relock sequences. |
| 663 | */ |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 664 | if (vr_ctl != CONFIG_VR_CTL_VAL) { |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 665 | serial_putc('?'); |
Mike Frysinger | 1114d0e | 2008-06-01 01:29:57 -0400 | [diff] [blame] | 666 | bfin_write_VR_CTL(CONFIG_VR_CTL_VAL); |
| 667 | asm("idle;"); |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 668 | serial_putc('!'); |
Mike Frysinger | 1114d0e | 2008-06-01 01:29:57 -0400 | [diff] [blame] | 669 | } |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 670 | |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 671 | serial_putc('k'); |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 672 | |
Mike Frysinger | 1114d0e | 2008-06-01 01:29:57 -0400 | [diff] [blame] | 673 | bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL); |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 674 | |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 675 | serial_putc('l'); |
Mike Frysinger | 1114d0e | 2008-06-01 01:29:57 -0400 | [diff] [blame] | 676 | |
| 677 | /* Only reprogram when needed to avoid triggering unnecessary |
| 678 | * PLL relock sequences. |
| 679 | */ |
Mike Frysinger | 43ed696 | 2009-04-04 08:10:22 -0400 | [diff] [blame] | 680 | if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) { |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 681 | serial_putc('?'); |
Mike Frysinger | 1114d0e | 2008-06-01 01:29:57 -0400 | [diff] [blame] | 682 | bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL); |
| 683 | asm("idle;"); |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 684 | serial_putc('!'); |
Mike Frysinger | 1114d0e | 2008-06-01 01:29:57 -0400 | [diff] [blame] | 685 | } |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 686 | |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 687 | serial_putc('m'); |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 688 | |
| 689 | /* Restore all peripheral wakeups. */ |
| 690 | #ifdef SIC_IWR0 |
| 691 | bfin_write_SIC_IWR0(-1); |
| 692 | bfin_write_SIC_IWR1(-1); |
| 693 | # ifdef SIC_IWR2 |
| 694 | bfin_write_SIC_IWR2(-1); |
| 695 | # endif |
| 696 | #elif defined(SICA_IWR0) |
| 697 | bfin_write_SICA_IWR0(-1); |
| 698 | bfin_write_SICA_IWR1(-1); |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 699 | #elif defined(SIC_IWR) |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 700 | bfin_write_SIC_IWR(-1); |
| 701 | #endif |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 702 | |
| 703 | serial_putc('n'); |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 704 | } |
| 705 | |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 706 | #endif /* __ADSPBF60x__ */ |
| 707 | |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 708 | serial_putc('o'); |
| 709 | |
| 710 | return vr_ctl; |
| 711 | } |
| 712 | |
| 713 | __attribute__((always_inline)) static inline void |
| 714 | update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB) |
| 715 | { |
| 716 | serial_putc('a'); |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 717 | |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 718 | /* Since we've changed the SCLK above, we may need to update |
| 719 | * the UART divisors (UART baud rates are based on SCLK). |
Mike Frysinger | 8445130 | 2008-12-10 12:33:54 -0500 | [diff] [blame] | 720 | * Do the division by hand as there are no native instructions |
| 721 | * for dividing which means we'd generate a libgcc reference. |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 722 | */ |
Mike Frysinger | 8445130 | 2008-12-10 12:33:54 -0500 | [diff] [blame] | 723 | if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) { |
| 724 | unsigned int sdivR, vcoR; |
Mike Frysinger | 8445130 | 2008-12-10 12:33:54 -0500 | [diff] [blame] | 725 | int dividend = sdivB * divB * vcoR; |
| 726 | int divisor = vcoB * sdivR; |
| 727 | unsigned int quotient; |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 728 | |
| 729 | serial_putc('b'); |
| 730 | |
| 731 | #ifdef __ADSPBF60x__ |
| 732 | sdivR = bfin_read_CGU_DIV(); |
| 733 | sdivR = ((sdivR >> 8) & 0x1f) * ((sdivR >> 5) & 0x7); |
| 734 | vcoR = (bfin_read_CGU_CTL() >> 8) & 0x7f; |
| 735 | #else |
| 736 | sdivR = bfin_read_PLL_DIV() & 0xf; |
| 737 | vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f; |
| 738 | #endif |
| 739 | |
Mike Frysinger | 8445130 | 2008-12-10 12:33:54 -0500 | [diff] [blame] | 740 | for (quotient = 0; dividend > 0; ++quotient) |
| 741 | dividend -= divisor; |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 742 | serial_early_put_div(quotient - ANOMALY_05000230); |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 743 | serial_putc('c'); |
Mike Frysinger | 8445130 | 2008-12-10 12:33:54 -0500 | [diff] [blame] | 744 | } |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 745 | |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 746 | serial_putc('d'); |
| 747 | } |
| 748 | |
| 749 | __attribute__((always_inline)) static inline void |
| 750 | program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs) |
| 751 | { |
| 752 | serial_putc('a'); |
| 753 | |
| 754 | if (!CONFIG_MEM_SIZE) |
| 755 | return; |
| 756 | |
| 757 | serial_putc('b'); |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 758 | |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 759 | #ifdef __ADSPBF60x__ |
| 760 | int dlldatacycle; |
| 761 | int dll_ctl; |
| 762 | int i = 0; |
| 763 | |
| 764 | if (CONFIG_BFIN_GET_DCLK_M == 125) |
| 765 | i = 0; |
| 766 | else if (CONFIG_BFIN_GET_DCLK_M == 133) |
| 767 | i = 1; |
| 768 | else if (CONFIG_BFIN_GET_DCLK_M == 150) |
| 769 | i = 2; |
| 770 | else if (CONFIG_BFIN_GET_DCLK_M == 166) |
| 771 | i = 3; |
| 772 | else if (CONFIG_BFIN_GET_DCLK_M == 200) |
| 773 | i = 4; |
| 774 | else if (CONFIG_BFIN_GET_DCLK_M == 225) |
| 775 | i = 5; |
| 776 | else if (CONFIG_BFIN_GET_DCLK_M == 250) |
| 777 | i = 6; |
| 778 | |
| 779 | #if 0 |
| 780 | for (i = 0; i < ARRAY_SIZE(ddr_config_table); i++) |
| 781 | if (CONFIG_BFIN_GET_DCLK_M == ddr_config_table[i].ddr_clk) |
| 782 | break; |
| 783 | #endif |
| 784 | |
| 785 | #ifndef CONFIG_DMC_DDRCFG |
| 786 | bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg); |
| 787 | #else |
| 788 | bfin_write_DMC0_CFG(CONFIG_DMC_DDRCFG); |
| 789 | #endif |
| 790 | #ifndef CONFIG_DMC_DDRTR0 |
| 791 | bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0); |
| 792 | #else |
| 793 | bfin_write_DMC0_TR0(CONFIG_DMC_DDRTR0); |
| 794 | #endif |
| 795 | #ifndef CONFIG_DMC_DDRTR1 |
| 796 | bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1); |
| 797 | #else |
| 798 | bfin_write_DMC0_TR1(CONFIG_DMC_DDRTR1); |
| 799 | #endif |
| 800 | #ifndef CONFIG_DMC_DDRTR2 |
| 801 | bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2); |
| 802 | #else |
| 803 | bfin_write_DMC0_TR2(CONFIG_DMC_DDRTR2); |
| 804 | #endif |
| 805 | #ifndef CONFIG_DMC_DDRMR |
| 806 | bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr); |
| 807 | #else |
| 808 | bfin_write_DMC0_MR(CONFIG_DMC_DDRMR); |
| 809 | #endif |
| 810 | #ifndef CONFIG_DMC_DDREMR1 |
| 811 | bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1); |
| 812 | #else |
| 813 | bfin_write_DMC0_EMR1(CONFIG_DMC_DDREMR1); |
| 814 | #endif |
| 815 | #ifndef CONFIG_DMC_DDRCTL |
| 816 | bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl); |
| 817 | #else |
| 818 | bfin_write_DMC0_CTL(CONFIG_DMC_DDRCTL); |
| 819 | #endif |
| 820 | |
| 821 | SSYNC(); |
| 822 | while (!(bfin_read_DMC0_STAT() & MEMINITDONE)) |
| 823 | continue; |
| 824 | |
| 825 | dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >> |
| 826 | PHYRDPHASE_OFFSET; |
| 827 | dll_ctl = bfin_read_DMC0_DLLCTL(); |
| 828 | dll_ctl &= 0x0ff; |
| 829 | bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET)); |
| 830 | |
| 831 | SSYNC(); |
| 832 | while (!(bfin_read_DMC0_STAT() & DLLCALDONE)) |
| 833 | continue; |
| 834 | serial_putc('!'); |
Steven Miao | e8505bb | 2012-03-31 16:01:50 +0800 | [diff] [blame] | 835 | |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 836 | #else /* __ADSPBF60x__ */ |
| 837 | |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 838 | /* Program the external memory controller before we come out of |
| 839 | * self-refresh. This only works with our SDRAM controller. |
| 840 | */ |
Mike Frysinger | 134db0d | 2010-12-17 15:25:09 -0500 | [diff] [blame] | 841 | #ifdef EBIU_SDGCTL |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 842 | # ifdef CONFIG_EBIU_SDRRC_VAL |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 843 | bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL); |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 844 | # endif |
| 845 | # ifdef CONFIG_EBIU_SDBCTL_VAL |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 846 | bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL); |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 847 | # endif |
| 848 | # ifdef CONFIG_EBIU_SDGCTL_VAL |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 849 | bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL); |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 850 | # endif |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 851 | #endif |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 852 | |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 853 | serial_putc('c'); |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 854 | |
| 855 | /* Now that we've reprogrammed, take things out of self refresh. */ |
| 856 | if (put_into_srfs) |
Mike Frysinger | 134db0d | 2010-12-17 15:25:09 -0500 | [diff] [blame] | 857 | #if defined(EBIU_RSTCTL) |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 858 | bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ)); |
Mike Frysinger | 134db0d | 2010-12-17 15:25:09 -0500 | [diff] [blame] | 859 | #elif defined(EBIU_SDGCTL) |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 860 | bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS)); |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 861 | #endif |
| 862 | |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 863 | serial_putc('d'); |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 864 | |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 865 | /* Our DDR controller sucks and cannot be programmed while in |
| 866 | * self-refresh. So we have to pull it out before programming. |
| 867 | */ |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 868 | #ifdef EBIU_RSTCTL |
Mike Frysinger | 4368ea2 | 2009-11-09 19:38:23 -0500 | [diff] [blame] | 869 | # ifdef CONFIG_EBIU_RSTCTL_VAL |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 870 | bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL); |
Mike Frysinger | 4368ea2 | 2009-11-09 19:38:23 -0500 | [diff] [blame] | 871 | # endif |
| 872 | # ifdef CONFIG_EBIU_DDRCTL0_VAL |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 873 | bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL); |
Mike Frysinger | 4368ea2 | 2009-11-09 19:38:23 -0500 | [diff] [blame] | 874 | # endif |
| 875 | # ifdef CONFIG_EBIU_DDRCTL1_VAL |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 876 | bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL); |
Mike Frysinger | 4368ea2 | 2009-11-09 19:38:23 -0500 | [diff] [blame] | 877 | # endif |
| 878 | # ifdef CONFIG_EBIU_DDRCTL2_VAL |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 879 | bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL); |
Mike Frysinger | 4368ea2 | 2009-11-09 19:38:23 -0500 | [diff] [blame] | 880 | # endif |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 881 | # ifdef CONFIG_EBIU_DDRCTL3_VAL |
| 882 | /* default is disable, so don't need to force this */ |
| 883 | bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL); |
| 884 | # endif |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 885 | # ifdef CONFIG_EBIU_DDRQUE_VAL |
| 886 | bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | CONFIG_EBIU_DDRQUE_VAL); |
| 887 | # endif |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 888 | #endif |
| 889 | |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 890 | #endif /* __ADSPBF60x__ */ |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 891 | serial_putc('e'); |
| 892 | } |
| 893 | |
| 894 | __attribute__((always_inline)) static inline void |
| 895 | check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs) |
| 896 | { |
| 897 | serial_putc('a'); |
| 898 | |
| 899 | if (!CONFIG_MEM_SIZE) |
| 900 | return; |
| 901 | |
| 902 | serial_putc('b'); |
Steven Miao | e8505bb | 2012-03-31 16:01:50 +0800 | [diff] [blame] | 903 | #ifdef __ADSPBF60x__ |
| 904 | if (bfin_read32(DPM0_RESTORE0) != 0) { |
| 905 | uint32_t reg = bfin_read_DMC0_CTL(); |
| 906 | reg &= ~0x8; |
| 907 | bfin_write_DMC0_CTL(reg); |
| 908 | |
| 909 | while ((bfin_read_DMC0_STAT() & 0x8)) |
| 910 | continue; |
| 911 | while (!(bfin_read_DMC0_STAT() & 0x1)) |
| 912 | continue; |
| 913 | |
| 914 | serial_putc('z'); |
| 915 | uint32_t *hibernate_magic = bfin_read32(DPM0_RESTORE4); |
| 916 | SSYNC(); /* make sure memory controller is done */ |
| 917 | if (hibernate_magic[0] == 0xDEADBEEF) { |
| 918 | serial_putc('c'); |
| 919 | SSYNC(); |
| 920 | bfin_write_EVT15(hibernate_magic[1]); |
| 921 | bfin_write_IMASK(EVT_IVG15); |
| 922 | __asm__ __volatile__ ( |
| 923 | /* load reti early to avoid anomaly 281 */ |
| 924 | "reti = %2;" |
| 925 | /* clear hibernate magic */ |
| 926 | "[%0] = %1;" |
| 927 | /* load stack pointer */ |
| 928 | "SP = [%0 + 8];" |
| 929 | /* lower ourselves from reset ivg to ivg15 */ |
| 930 | "raise 15;" |
| 931 | "nop;nop;nop;" |
| 932 | "rti;" |
| 933 | : |
| 934 | : "p"(hibernate_magic), |
| 935 | "d"(0x2000 /* jump.s 0 */), |
| 936 | "d"(0xffa00000) |
| 937 | ); |
| 938 | } |
| 939 | |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 940 | |
Steven Miao | e8505bb | 2012-03-31 16:01:50 +0800 | [diff] [blame] | 941 | } |
| 942 | #else |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 943 | /* Are we coming out of hibernate (suspend to memory) ? |
| 944 | * The memory layout is: |
| 945 | * 0x0: hibernate magic for anomaly 307 (0xDEADBEEF) |
| 946 | * 0x4: return address |
| 947 | * 0x8: stack pointer |
| 948 | * |
| 949 | * SCKELOW is unreliable on older parts (anomaly 307) |
| 950 | */ |
| 951 | if (ANOMALY_05000307 || vr_ctl & 0x8000) { |
| 952 | uint32_t *hibernate_magic = 0; |
Sonic Zhang | a99f03e | 2012-08-16 11:56:14 +0800 | [diff] [blame] | 953 | |
| 954 | SSYNC(); |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 955 | if (hibernate_magic[0] == 0xDEADBEEF) { |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 956 | serial_putc('c'); |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 957 | bfin_write_EVT15(hibernate_magic[1]); |
| 958 | bfin_write_IMASK(EVT_IVG15); |
| 959 | __asm__ __volatile__ ( |
| 960 | /* load reti early to avoid anomaly 281 */ |
| 961 | "reti = %0;" |
| 962 | /* clear hibernate magic */ |
| 963 | "[%0] = %1;" |
| 964 | /* load stack pointer */ |
| 965 | "SP = [%0 + 8];" |
| 966 | /* lower ourselves from reset ivg to ivg15 */ |
| 967 | "raise 15;" |
| 968 | "rti;" |
| 969 | : |
| 970 | : "p"(hibernate_magic), "d"(0x2000 /* jump.s 0 */) |
| 971 | ); |
| 972 | } |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 973 | serial_putc('d'); |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 974 | } |
Steven Miao | e8505bb | 2012-03-31 16:01:50 +0800 | [diff] [blame] | 975 | #endif |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 976 | |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 977 | serial_putc('e'); |
| 978 | } |
| 979 | |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 980 | BOOTROM_CALLED_FUNC_ATTR |
| 981 | void initcode(ADI_BOOT_DATA *bs) |
| 982 | { |
| 983 | ADI_BOOT_DATA bootstruct_scratch; |
| 984 | |
Mike Frysinger | eb2a399 | 2010-05-05 02:07:44 -0400 | [diff] [blame] | 985 | /* Setup NMI handler before anything else */ |
| 986 | program_nmi_handler(); |
| 987 | |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 988 | serial_init(); |
| 989 | |
| 990 | serial_putc('A'); |
| 991 | |
| 992 | /* If the bootstruct is NULL, then it's because we're loading |
| 993 | * dynamically and not via LDR (bootrom). So set the struct to |
| 994 | * some scratch space. |
| 995 | */ |
| 996 | if (!bs) |
| 997 | bs = &bootstruct_scratch; |
| 998 | |
| 999 | serial_putc('B'); |
| 1000 | bool put_into_srfs = maybe_self_refresh(bs); |
| 1001 | |
| 1002 | serial_putc('C'); |
| 1003 | uint sdivB, divB, vcoB; |
| 1004 | program_early_devices(bs, &sdivB, &divB, &vcoB); |
| 1005 | |
| 1006 | serial_putc('D'); |
| 1007 | u16 vr_ctl = program_clocks(bs, put_into_srfs); |
| 1008 | |
| 1009 | serial_putc('E'); |
| 1010 | update_serial_clocks(bs, sdivB, divB, vcoB); |
| 1011 | |
| 1012 | serial_putc('F'); |
| 1013 | program_memory_controller(bs, put_into_srfs); |
| 1014 | |
| 1015 | serial_putc('G'); |
| 1016 | check_hibernation(bs, vr_ctl, put_into_srfs); |
| 1017 | |
| 1018 | serial_putc('H'); |
| 1019 | program_async_controller(bs); |
Mike Frysinger | 268dbf5 | 2008-10-11 21:58:33 -0400 | [diff] [blame] | 1020 | |
Mike Frysinger | a48e0ed | 2009-04-24 23:39:41 -0400 | [diff] [blame] | 1021 | #ifdef CONFIG_BFIN_BOOTROM_USES_EVT1 |
Mike Frysinger | 3343bfa | 2009-11-09 19:44:04 -0500 | [diff] [blame] | 1022 | serial_putc('I'); |
Mike Frysinger | 1100b69 | 2010-04-29 02:49:41 -0400 | [diff] [blame] | 1023 | /* Tell the bootrom where our entry point is so that it knows |
| 1024 | * where to jump to when finishing processing the LDR. This |
| 1025 | * allows us to avoid small jump blocks in the LDR, and also |
| 1026 | * works around anomaly 05000389 (init address in external |
| 1027 | * memory causes bootrom to trigger external addressing IVHW). |
| 1028 | */ |
Mike Frysinger | 9959368 | 2008-10-18 04:04:49 -0400 | [diff] [blame] | 1029 | if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) |
| 1030 | bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE); |
Mike Frysinger | a48e0ed | 2009-04-24 23:39:41 -0400 | [diff] [blame] | 1031 | #endif |
Mike Frysinger | 9959368 | 2008-10-18 04:04:49 -0400 | [diff] [blame] | 1032 | |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 1033 | serial_putc('>'); |
| 1034 | serial_putc('\n'); |
| 1035 | |
| 1036 | serial_deinit(); |
| 1037 | } |