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git01.mediatek.com / filogic / uboot / 56a931cdb7c462688f361f70e1dbe36ae37e7f63 / . / arch / arm / cpu / armv7 / s5p-common / sromc.c
blob: 806456fe8ad5ec4c140c8e49a9dc9caf167077e1 [file] [log] [blame]
Naveen Krishna CH4b3bece2010-03-05 17:15:38 +0900[diff] [blame]1/*
2 * Copyright (C) 2010 Samsung Electronics
3 * Naveen Krishna Ch <ch.naveen@samsung.com>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Naveen Krishna CH4b3bece2010-03-05 17:15:38 +0900[diff] [blame]6 */
7
8#include <common.h>
9#include <asm/io.h>
Chander Kashyap9c88fb82011-04-14 19:05:18 +0000[diff] [blame]10#include <asm/arch/sromc.h>
Naveen Krishna CH4b3bece2010-03-05 17:15:38 +0900[diff] [blame]11
12/*
Chander Kashyap9c88fb82011-04-14 19:05:18 +0000[diff] [blame]13 * s5p_config_sromc() - select the proper SROMC Bank and configure the
14 * band width control and bank control registers
15 * srom_bank - SROM
16 * srom_bw_conf - SMC Band witdh reg configuration value
17 * srom_bc_conf - SMC Bank Control reg configuration value
Naveen Krishna CH4b3bece2010-03-05 17:15:38 +0900[diff] [blame]18 */
Chander Kashyap9c88fb82011-04-14 19:05:18 +0000[diff] [blame]19void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf)
Naveen Krishna CH4b3bece2010-03-05 17:15:38 +0900[diff] [blame]20{
21 u32 tmp;
Chander Kashyap9c88fb82011-04-14 19:05:18 +0000[diff] [blame]22 struct s5p_sromc *srom =
23 (struct s5p_sromc *)samsung_get_base_sromc();
Naveen Krishna CH4b3bece2010-03-05 17:15:38 +0900[diff] [blame]24
25 /* Configure SMC_BW register to handle proper SROMC bank */
26 tmp = srom->bw;
27 tmp &= ~(0xF << (srom_bank * 4));
Chander Kashyap9c88fb82011-04-14 19:05:18 +0000[diff] [blame]28 tmp |= srom_bw_conf;
Naveen Krishna CH4b3bece2010-03-05 17:15:38 +0900[diff] [blame]29 srom->bw = tmp;
30
31 /* Configure SMC_BC register */
Chander Kashyap9c88fb82011-04-14 19:05:18 +0000[diff] [blame]32 srom->bc[srom_bank] = srom_bc_conf;
Naveen Krishna CH4b3bece2010-03-05 17:15:38 +0900[diff] [blame]33}