Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 2 | /* |
| 3 | * pinmux setup for siemens rut board |
| 4 | * |
| 5 | * (C) Copyright 2013 Siemens Schweiz AG |
| 6 | * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. |
| 7 | * |
| 8 | * Based on: |
| 9 | * u-boot:/board/ti/am335x/mux.c |
| 10 | * |
| 11 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 12 | */ |
| 13 | |
| 14 | #include <common.h> |
| 15 | #include <asm/arch/sys_proto.h> |
| 16 | #include <asm/arch/hardware.h> |
| 17 | #include <asm/arch/mux.h> |
| 18 | #include <asm/io.h> |
| 19 | #include <i2c.h> |
| 20 | |
| 21 | static struct module_pin_mux uart0_pin_mux[] = { |
| 22 | {OFFSET(uart0_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* UART0_RXD */ |
| 23 | {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)}, /* UART0_TXD */ |
| 24 | {-1}, |
| 25 | }; |
| 26 | |
| 27 | static struct module_pin_mux ddr_pin_mux[] = { |
| 28 | {OFFSET(ddr_resetn), (MODE(0))}, |
| 29 | {OFFSET(ddr_csn0), (MODE(0) | PULLUP_EN)}, |
| 30 | {OFFSET(ddr_ck), (MODE(0))}, |
| 31 | {OFFSET(ddr_nck), (MODE(0))}, |
| 32 | {OFFSET(ddr_casn), (MODE(0) | PULLUP_EN)}, |
| 33 | {OFFSET(ddr_rasn), (MODE(0) | PULLUP_EN)}, |
| 34 | {OFFSET(ddr_wen), (MODE(0) | PULLUP_EN)}, |
| 35 | {OFFSET(ddr_ba0), (MODE(0) | PULLUP_EN)}, |
| 36 | {OFFSET(ddr_ba1), (MODE(0) | PULLUP_EN)}, |
| 37 | {OFFSET(ddr_ba2), (MODE(0) | PULLUP_EN)}, |
| 38 | {OFFSET(ddr_a0), (MODE(0) | PULLUP_EN)}, |
| 39 | {OFFSET(ddr_a1), (MODE(0) | PULLUP_EN)}, |
| 40 | {OFFSET(ddr_a2), (MODE(0) | PULLUP_EN)}, |
| 41 | {OFFSET(ddr_a3), (MODE(0) | PULLUP_EN)}, |
| 42 | {OFFSET(ddr_a4), (MODE(0) | PULLUP_EN)}, |
| 43 | {OFFSET(ddr_a5), (MODE(0) | PULLUP_EN)}, |
| 44 | {OFFSET(ddr_a6), (MODE(0) | PULLUP_EN)}, |
| 45 | {OFFSET(ddr_a7), (MODE(0) | PULLUP_EN)}, |
| 46 | {OFFSET(ddr_a8), (MODE(0) | PULLUP_EN)}, |
| 47 | {OFFSET(ddr_a9), (MODE(0) | PULLUP_EN)}, |
| 48 | {OFFSET(ddr_a10), (MODE(0) | PULLUP_EN)}, |
| 49 | {OFFSET(ddr_a11), (MODE(0) | PULLUP_EN)}, |
| 50 | {OFFSET(ddr_a12), (MODE(0) | PULLUP_EN)}, |
| 51 | {OFFSET(ddr_a13), (MODE(0) | PULLUP_EN)}, |
| 52 | {OFFSET(ddr_a14), (MODE(0) | PULLUP_EN)}, |
| 53 | {OFFSET(ddr_a15), (MODE(0) | PULLUP_EN)}, |
| 54 | {OFFSET(ddr_odt), (MODE(0))}, |
| 55 | {OFFSET(ddr_d0), (MODE(0) | RXACTIVE)}, |
| 56 | {OFFSET(ddr_d1), (MODE(0) | RXACTIVE)}, |
| 57 | {OFFSET(ddr_d2), (MODE(0) | RXACTIVE)}, |
| 58 | {OFFSET(ddr_d3), (MODE(0) | RXACTIVE)}, |
| 59 | {OFFSET(ddr_d4), (MODE(0) | RXACTIVE)}, |
| 60 | {OFFSET(ddr_d5), (MODE(0) | RXACTIVE)}, |
| 61 | {OFFSET(ddr_d6), (MODE(0) | RXACTIVE)}, |
| 62 | {OFFSET(ddr_d7), (MODE(0) | RXACTIVE)}, |
| 63 | {OFFSET(ddr_d8), (MODE(0) | RXACTIVE)}, |
| 64 | {OFFSET(ddr_d9), (MODE(0) | RXACTIVE)}, |
| 65 | {OFFSET(ddr_d10), (MODE(0) | RXACTIVE)}, |
| 66 | {OFFSET(ddr_d11), (MODE(0) | RXACTIVE)}, |
| 67 | {OFFSET(ddr_d12), (MODE(0) | RXACTIVE)}, |
| 68 | {OFFSET(ddr_d13), (MODE(0) | RXACTIVE)}, |
| 69 | {OFFSET(ddr_d14), (MODE(0) | RXACTIVE)}, |
| 70 | {OFFSET(ddr_d15), (MODE(0) | RXACTIVE)}, |
| 71 | {OFFSET(ddr_dqm0), (MODE(0) | PULLUP_EN)}, |
| 72 | {OFFSET(ddr_dqm1), (MODE(0) | PULLUP_EN)}, |
| 73 | {OFFSET(ddr_dqs0), (MODE(0) | RXACTIVE)}, |
| 74 | {OFFSET(ddr_dqsn0), (MODE(0) | RXACTIVE | PULLUP_EN)}, |
| 75 | {OFFSET(ddr_dqs1), (MODE(0) | RXACTIVE)}, |
| 76 | {OFFSET(ddr_dqsn1), (MODE(0) | RXACTIVE | PULLUP_EN)}, |
| 77 | {OFFSET(ddr_vref), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 78 | {OFFSET(ddr_vtp), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 79 | {-1}, |
| 80 | }; |
| 81 | |
| 82 | static struct module_pin_mux lcd_pin_mux[] = { |
| 83 | {OFFSET(gpmc_ad8), (MODE(1))}, |
| 84 | {OFFSET(gpmc_ad9), (MODE(1))}, |
| 85 | {OFFSET(gpmc_ad10), (MODE(1))}, |
| 86 | {OFFSET(gpmc_ad11), (MODE(1))}, |
| 87 | {OFFSET(gpmc_ad12), (MODE(1))}, |
| 88 | {OFFSET(gpmc_ad13), (MODE(1))}, |
| 89 | {OFFSET(gpmc_ad14), (MODE(1))}, |
| 90 | {OFFSET(gpmc_ad15), (MODE(1))}, |
| 91 | {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, |
| 92 | {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, |
| 93 | {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, |
| 94 | {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, |
| 95 | {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, |
| 96 | {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, |
| 97 | {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, |
| 98 | {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, |
| 99 | {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, |
| 100 | {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, |
| 101 | {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, |
| 102 | {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, |
| 103 | {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, |
| 104 | {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, |
| 105 | {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, |
| 106 | {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, |
| 107 | {OFFSET(lcd_vsync), (MODE(0))}, |
| 108 | {OFFSET(lcd_hsync), (MODE(0))}, |
| 109 | {OFFSET(lcd_pclk), (MODE(0))}, |
| 110 | {OFFSET(lcd_ac_bias_en), (MODE(0))}, |
| 111 | {-1}, |
| 112 | }; |
| 113 | |
| 114 | static struct module_pin_mux mmc0_pin_mux[] = { |
| 115 | {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, |
| 116 | {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, |
| 117 | {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, |
| 118 | {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, |
| 119 | {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, |
| 120 | {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, |
| 121 | {-1}, |
| 122 | }; |
| 123 | |
| 124 | static struct module_pin_mux mii_pin_mux[] = { |
| 125 | {OFFSET(mii1_crs), (MODE(1) | RXACTIVE)}, |
| 126 | {OFFSET(mii1_rxerr), (MODE(1) | RXACTIVE)}, |
| 127 | {OFFSET(mii1_txen), (MODE(1))}, |
| 128 | {OFFSET(mii1_txd1), (MODE(1))}, |
| 129 | {OFFSET(mii1_txd0), (MODE(1))}, |
| 130 | {OFFSET(mii1_rxd1), (MODE(1) | RXACTIVE)}, |
| 131 | {OFFSET(mii1_rxd0), (MODE(1) | RXACTIVE)}, |
| 132 | {OFFSET(rmii1_refclk), (MODE(0) | RXACTIVE)}, |
| 133 | {OFFSET(mdio_data), (MODE(0) | RXACTIVE | PULLUP_EN)}, |
| 134 | {OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)}, |
| 135 | {-1}, |
| 136 | }; |
| 137 | |
| 138 | static struct module_pin_mux gpio_pin_mux[] = { |
| 139 | {OFFSET(mii1_col), (MODE(7) | RXACTIVE)}, |
| 140 | {OFFSET(uart1_ctsn), (MODE(7) | RXACTIVE | PULLUDDIS)}, |
| 141 | {OFFSET(uart1_rtsn), (MODE(7) | RXACTIVE | PULLUDDIS)}, |
| 142 | {OFFSET(uart1_rxd), (MODE(7) | RXACTIVE | PULLUDDIS)}, |
| 143 | {OFFSET(uart1_txd), (MODE(7) | RXACTIVE | PULLUDDIS)}, |
| 144 | {OFFSET(mii1_rxdv), (MODE(7) | RXACTIVE)}, |
| 145 | {OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)}, |
| 146 | {OFFSET(mii1_txd2), (MODE(7) | RXACTIVE)}, |
| 147 | {OFFSET(mii1_txclk), (MODE(7) | RXACTIVE)}, |
| 148 | {OFFSET(mii1_rxclk), (MODE(7) | RXACTIVE)}, |
| 149 | {OFFSET(mii1_rxd3), (MODE(7) | RXACTIVE)}, |
| 150 | {OFFSET(mii1_rxd2), (MODE(7) | RXACTIVE)}, |
| 151 | {OFFSET(gpmc_a0), (MODE(7) | RXACTIVE)}, |
| 152 | {OFFSET(gpmc_a1), (MODE(7) | RXACTIVE)}, |
| 153 | {OFFSET(gpmc_a4), (MODE(7) | RXACTIVE)}, |
| 154 | {OFFSET(gpmc_a5), (MODE(7) | RXACTIVE)}, |
| 155 | {OFFSET(gpmc_a6), (MODE(7) | RXACTIVE)}, |
| 156 | {OFFSET(gpmc_a7), (MODE(7) | RXACTIVE)}, |
| 157 | {OFFSET(gpmc_a8), (MODE(7) | RXACTIVE)}, |
| 158 | {OFFSET(gpmc_a9), (MODE(7) | RXACTIVE)}, |
| 159 | {OFFSET(gpmc_a10), (MODE(7) | RXACTIVE)}, |
| 160 | {OFFSET(gpmc_a11), (MODE(7) | RXACTIVE)}, |
| 161 | {OFFSET(gpmc_wpn), (MODE(7) | RXACTIVE | PULLUP_EN)}, |
| 162 | {OFFSET(gpmc_be1n), (MODE(7) | RXACTIVE | PULLUP_EN)}, |
| 163 | {OFFSET(gpmc_csn1), (MODE(7) | RXACTIVE | PULLUP_EN)}, |
| 164 | {OFFSET(gpmc_csn2), (MODE(7) | RXACTIVE | PULLUP_EN)}, |
| 165 | {OFFSET(gpmc_csn3), (MODE(7) | RXACTIVE | PULLUP_EN)}, |
| 166 | {OFFSET(mcasp0_aclkr), (MODE(7) | RXACTIVE)}, |
| 167 | {OFFSET(mcasp0_fsr), (MODE(7))}, |
| 168 | {OFFSET(mcasp0_axr1), (MODE(7) | RXACTIVE)}, |
| 169 | {OFFSET(mcasp0_ahclkx), (MODE(7) | RXACTIVE)}, |
| 170 | {OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE | PULLUDDIS)}, |
| 171 | {OFFSET(xdma_event_intr1), (MODE(7) | RXACTIVE | PULLUDDIS)}, |
| 172 | {-1}, |
| 173 | }; |
| 174 | |
| 175 | static struct module_pin_mux i2c0_pin_mux[] = { |
| 176 | {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 177 | {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 178 | {-1}, |
| 179 | }; |
| 180 | |
| 181 | static struct module_pin_mux i2c1_pin_mux[] = { |
| 182 | {OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE | PULLUDDIS)}, |
| 183 | {OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE | PULLUDDIS)}, |
| 184 | {-1}, |
| 185 | }; |
| 186 | |
| 187 | static struct module_pin_mux usb0_pin_mux[] = { |
| 188 | {OFFSET(usb0_dm), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 189 | {OFFSET(usb0_dp), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 190 | {OFFSET(usb0_ce), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 191 | {OFFSET(usb0_id), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 192 | {OFFSET(usb0_vbus), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 193 | {OFFSET(usb0_drvvbus), (MODE(0))}, |
| 194 | {-1}, |
| 195 | }; |
| 196 | |
| 197 | static struct module_pin_mux usb1_pin_mux[] = { |
| 198 | {OFFSET(usb1_dm), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 199 | {OFFSET(usb1_dp), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 200 | {OFFSET(usb1_ce), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 201 | {OFFSET(usb1_id), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 202 | {OFFSET(usb1_vbus), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 203 | {OFFSET(usb1_drvvbus), (MODE(0))}, |
| 204 | {-1}, |
| 205 | }; |
| 206 | |
| 207 | static struct module_pin_mux spi0_pin_mux[] = { |
| 208 | {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 209 | {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 210 | {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 211 | {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 212 | {OFFSET(spi0_cs1), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 213 | {-1}, |
| 214 | }; |
| 215 | |
| 216 | static struct module_pin_mux spi1_pin_mux[] = { |
| 217 | {OFFSET(mcasp0_aclkx), (MODE(3) | RXACTIVE | PULLUP_EN)}, |
| 218 | {OFFSET(mcasp0_fsx), (MODE(3) | RXACTIVE | PULLUP_EN)}, |
| 219 | {OFFSET(mcasp0_axr0), (MODE(3) | RXACTIVE | PULLUP_EN)}, |
| 220 | {OFFSET(mcasp0_ahclkr), (MODE(3) | RXACTIVE | PULLUP_EN)}, |
| 221 | {-1}, |
| 222 | }; |
| 223 | |
| 224 | static struct module_pin_mux jtag_pin_mux[] = { |
| 225 | {OFFSET(tms), (MODE(0) | RXACTIVE | PULLUP_EN)}, |
| 226 | {OFFSET(tdi), (MODE(0) | RXACTIVE | PULLUP_EN)}, |
| 227 | {OFFSET(tdo), (MODE(0) | PULLUP_EN)}, |
| 228 | {OFFSET(tck), (MODE(0) | RXACTIVE | PULLUP_EN)}, |
| 229 | {OFFSET(ntrst), (MODE(0) | RXACTIVE)}, |
| 230 | {-1}, |
| 231 | }; |
| 232 | |
| 233 | static struct module_pin_mux nand_pin_mux[] = { |
| 234 | {OFFSET(gpmc_ad0), (MODE(0) | RXACTIVE)}, |
| 235 | {OFFSET(gpmc_ad1), (MODE(0) | RXACTIVE)}, |
| 236 | {OFFSET(gpmc_ad2), (MODE(0) | RXACTIVE)}, |
| 237 | {OFFSET(gpmc_ad3), (MODE(0) | RXACTIVE)}, |
| 238 | {OFFSET(gpmc_ad4), (MODE(0) | RXACTIVE)}, |
| 239 | {OFFSET(gpmc_ad5), (MODE(0) | RXACTIVE)}, |
| 240 | {OFFSET(gpmc_ad6), (MODE(0) | RXACTIVE)}, |
| 241 | {OFFSET(gpmc_ad7), (MODE(0) | RXACTIVE)}, |
| 242 | {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUP_EN)}, |
| 243 | {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUP_EN)}, |
| 244 | {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, |
| 245 | {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUP_EN)}, |
| 246 | {OFFSET(gpmc_wen), (MODE(0) | PULLUP_EN)}, |
| 247 | {-1}, |
| 248 | }; |
| 249 | |
| 250 | static struct module_pin_mux ainx_pin_mux[] = { |
| 251 | {OFFSET(ain7), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 252 | {OFFSET(ain6), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 253 | {OFFSET(ain5), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 254 | {OFFSET(ain4), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 255 | {OFFSET(ain3), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 256 | {OFFSET(ain2), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 257 | {OFFSET(ain1), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 258 | {OFFSET(ain0), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 259 | {-1}, |
| 260 | }; |
| 261 | |
| 262 | static struct module_pin_mux rtc_pin_mux[] = { |
| 263 | {OFFSET(osc1_in), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 264 | {OFFSET(osc1_out), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 265 | {OFFSET(rtc_porz), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 266 | {OFFSET(enz_kaldo_1p8v), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 267 | {-1}, |
| 268 | }; |
| 269 | |
| 270 | static struct module_pin_mux gpmc_pin_mux[] = { |
| 271 | {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, |
| 272 | {OFFSET(gpmc_clk), (MODE(0) | RXACTIVE)}, |
| 273 | {-1}, |
| 274 | }; |
| 275 | |
| 276 | static struct module_pin_mux pmic_pin_mux[] = { |
| 277 | {OFFSET(pmic_power_en), (MODE(0) | PULLUP_EN)}, |
| 278 | {-1}, |
| 279 | }; |
| 280 | |
| 281 | static struct module_pin_mux osc_pin_mux[] = { |
| 282 | {OFFSET(osc0_in), (MODE(0) | RXACTIVE | PULLUP_EN)}, |
| 283 | {OFFSET(osc0_out), (MODE(0) | PULLUP_EN)}, |
| 284 | {-1}, |
| 285 | }; |
| 286 | |
| 287 | static struct module_pin_mux pwm_pin_mux[] = { |
| 288 | {OFFSET(ecap0_in_pwm0_out), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 289 | {OFFSET(gpmc_a2), (MODE(6))}, |
| 290 | {OFFSET(gpmc_a3), (MODE(6))}, |
| 291 | {-1}, |
| 292 | }; |
| 293 | |
| 294 | static struct module_pin_mux emu_pin_mux[] = { |
| 295 | {OFFSET(emu0), (MODE(0) | RXACTIVE | PULLUP_EN)}, |
| 296 | {OFFSET(emu1), (MODE(0) | RXACTIVE | PULLUP_EN)}, |
| 297 | {-1}, |
| 298 | }; |
| 299 | |
| 300 | static struct module_pin_mux vref_pin_mux[] = { |
| 301 | {OFFSET(vrefp), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 302 | {OFFSET(vrefn), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 303 | {-1}, |
| 304 | }; |
| 305 | |
| 306 | static struct module_pin_mux misc_pin_mux[] = { |
| 307 | {OFFSET(porz), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 308 | {OFFSET(nnmi), (MODE(0) | RXACTIVE | PULLUDDIS)}, |
| 309 | {OFFSET(ext_wakeup), (MODE(0) | RXACTIVE)}, |
| 310 | {-1}, |
| 311 | }; |
| 312 | |
| 313 | void enable_uart0_pin_mux(void) |
| 314 | { |
| 315 | configure_module_pin_mux(uart0_pin_mux); |
| 316 | } |
| 317 | |
| 318 | void enable_i2c0_pin_mux(void) |
| 319 | { |
| 320 | configure_module_pin_mux(i2c0_pin_mux); |
| 321 | } |
| 322 | |
| 323 | void enable_board_pin_mux(void) |
| 324 | { |
| 325 | configure_module_pin_mux(ddr_pin_mux); |
| 326 | configure_module_pin_mux(lcd_pin_mux); |
| 327 | configure_module_pin_mux(mmc0_pin_mux); |
| 328 | configure_module_pin_mux(mii_pin_mux); |
| 329 | configure_module_pin_mux(gpio_pin_mux); |
| 330 | configure_module_pin_mux(i2c1_pin_mux); |
| 331 | configure_module_pin_mux(usb0_pin_mux); |
| 332 | configure_module_pin_mux(usb1_pin_mux); |
| 333 | configure_module_pin_mux(spi0_pin_mux); |
| 334 | configure_module_pin_mux(spi1_pin_mux); |
| 335 | configure_module_pin_mux(jtag_pin_mux); |
| 336 | configure_module_pin_mux(nand_pin_mux); |
| 337 | configure_module_pin_mux(ainx_pin_mux); |
| 338 | configure_module_pin_mux(rtc_pin_mux); |
| 339 | configure_module_pin_mux(gpmc_pin_mux); |
| 340 | configure_module_pin_mux(pmic_pin_mux); |
| 341 | configure_module_pin_mux(osc_pin_mux); |
| 342 | configure_module_pin_mux(pwm_pin_mux); |
| 343 | configure_module_pin_mux(emu_pin_mux); |
| 344 | configure_module_pin_mux(vref_pin_mux); |
| 345 | configure_module_pin_mux(misc_pin_mux); |
| 346 | } |