Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Ben Whitten | 44b7fc8 | 2017-11-23 13:47:48 +0000 | [diff] [blame] | 2 | /* |
Ben Whitten | 44b7fc8 | 2017-11-23 13:47:48 +0000 | [diff] [blame] | 3 | */ |
| 4 | |
| 5 | #include <common.h> |
| 6 | #include <asm/io.h> |
Tudor Ambarus | 680897a | 2019-09-27 13:09:00 +0000 | [diff] [blame] | 7 | #include <asm/arch/at91_sfr.h> |
Ben Whitten | 44b7fc8 | 2017-11-23 13:47:48 +0000 | [diff] [blame] | 8 | #include <asm/arch/sama5d3_smc.h> |
| 9 | #include <asm/arch/at91_common.h> |
| 10 | #include <asm/arch/at91_pmc.h> |
| 11 | #include <asm/arch/at91_rstc.h> |
| 12 | #include <asm/arch/gpio.h> |
| 13 | #include <asm/arch/clk.h> |
Simon Glass | 5e6201b | 2019-08-01 09:46:51 -0600 | [diff] [blame] | 14 | #include <env.h> |
Ben Whitten | 44b7fc8 | 2017-11-23 13:47:48 +0000 | [diff] [blame] | 15 | #include <micrel.h> |
| 16 | #include <net.h> |
| 17 | #include <netdev.h> |
| 18 | #include <spl.h> |
| 19 | #include <asm/arch/atmel_mpddrc.h> |
| 20 | #include <asm/arch/at91_wdt.h> |
| 21 | |
| 22 | DECLARE_GLOBAL_DATA_PTR; |
| 23 | |
| 24 | /* ------------------------------------------------------------------------- */ |
| 25 | /* |
| 26 | * Miscelaneous platform dependent initialisations |
| 27 | */ |
| 28 | |
| 29 | void wb50n_nand_hw_init(void) |
| 30 | { |
| 31 | struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; |
| 32 | |
| 33 | at91_periph_clk_enable(ATMEL_ID_SMC); |
| 34 | |
| 35 | /* Configure SMC CS3 for NAND/SmartMedia */ |
| 36 | writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) | |
| 37 | AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1), |
| 38 | &smc->cs[3].setup); |
| 39 | writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | |
| 40 | AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5), |
| 41 | &smc->cs[3].pulse); |
| 42 | writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8), |
| 43 | &smc->cs[3].cycle); |
| 44 | writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) | |
| 45 | AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) | |
| 46 | AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3) | |
| 47 | AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); |
| 48 | writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | |
| 49 | AT91_SMC_MODE_EXNW_DISABLE | |
| 50 | AT91_SMC_MODE_DBW_8 | |
| 51 | AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode); |
| 52 | |
| 53 | /* Disable Flash Write Protect Line */ |
| 54 | at91_set_pio_output(AT91_PIO_PORTE, 14, 1); |
| 55 | } |
| 56 | |
| 57 | int board_early_init_f(void) |
| 58 | { |
| 59 | at91_periph_clk_enable(ATMEL_ID_PIOA); |
| 60 | at91_periph_clk_enable(ATMEL_ID_PIOB); |
| 61 | at91_periph_clk_enable(ATMEL_ID_PIOC); |
| 62 | at91_periph_clk_enable(ATMEL_ID_PIOD); |
| 63 | at91_periph_clk_enable(ATMEL_ID_PIOE); |
| 64 | |
| 65 | at91_seriald_hw_init(); |
| 66 | |
| 67 | return 0; |
| 68 | } |
| 69 | |
| 70 | int board_init(void) |
| 71 | { |
| 72 | /* adress of boot parameters */ |
| 73 | gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
| 74 | |
| 75 | wb50n_nand_hw_init(); |
| 76 | |
| 77 | at91_macb_hw_init(); |
| 78 | |
| 79 | return 0; |
| 80 | } |
| 81 | |
| 82 | int dram_init(void) |
| 83 | { |
| 84 | gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, |
| 85 | CONFIG_SYS_SDRAM_SIZE); |
| 86 | return 0; |
| 87 | } |
| 88 | |
| 89 | int board_phy_config(struct phy_device *phydev) |
| 90 | { |
| 91 | /* rx data delay */ |
| 92 | ksz9021_phy_extended_write(phydev, |
| 93 | MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x2222); |
| 94 | /* tx data delay */ |
| 95 | ksz9021_phy_extended_write(phydev, |
| 96 | MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x2222); |
| 97 | /* rx/tx clock delay */ |
| 98 | ksz9021_phy_extended_write(phydev, |
| 99 | MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf2f4); |
| 100 | |
| 101 | return 0; |
| 102 | } |
| 103 | |
| 104 | int board_eth_init(bd_t *bis) |
| 105 | { |
| 106 | int rc = 0; |
| 107 | |
| 108 | rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); |
| 109 | |
| 110 | return rc; |
| 111 | } |
| 112 | |
| 113 | #ifdef CONFIG_BOARD_LATE_INIT |
| 114 | #include <linux/ctype.h> |
| 115 | int board_late_init(void) |
| 116 | { |
| 117 | #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
| 118 | const char *LAIRD_NAME = "lrd_name"; |
| 119 | char name[32], *p; |
| 120 | |
| 121 | strcpy(name, get_cpu_name()); |
| 122 | for (p = name; *p != '\0'; *p = tolower(*p), p++) |
| 123 | ; |
| 124 | strcat(name, "-wb50n"); |
| 125 | env_set(LAIRD_NAME, name); |
| 126 | |
| 127 | #endif |
| 128 | |
| 129 | return 0; |
| 130 | } |
| 131 | #endif |
| 132 | |
| 133 | /* SPL */ |
| 134 | #ifdef CONFIG_SPL_BUILD |
| 135 | void spl_board_init(void) |
| 136 | { |
| 137 | wb50n_nand_hw_init(); |
| 138 | } |
| 139 | |
| 140 | static void ddr2_conf(struct atmel_mpddrc_config *ddr2) |
| 141 | { |
| 142 | ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM); |
| 143 | |
| 144 | ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_9 | |
| 145 | ATMEL_MPDDRC_CR_NR_ROW_13 | |
| 146 | ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | |
| 147 | ATMEL_MPDDRC_CR_NDQS_DISABLED | |
| 148 | ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | |
| 149 | ATMEL_MPDDRC_CR_UNAL_SUPPORTED); |
| 150 | |
| 151 | ddr2->rtr = 0x411; |
| 152 | |
| 153 | ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | |
| 154 | 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | |
| 155 | 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | |
| 156 | 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | |
| 157 | 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | |
| 158 | 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | |
| 159 | 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | |
| 160 | 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); |
| 161 | |
| 162 | ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | |
| 163 | 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | |
| 164 | 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | |
| 165 | 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); |
| 166 | |
| 167 | ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | |
| 168 | 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | |
| 169 | 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | |
| 170 | 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | |
| 171 | 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); |
| 172 | } |
| 173 | |
| 174 | void mem_init(void) |
| 175 | { |
Ben Whitten | 44b7fc8 | 2017-11-23 13:47:48 +0000 | [diff] [blame] | 176 | struct atmel_mpddrc_config ddr2; |
| 177 | |
| 178 | ddr2_conf(&ddr2); |
| 179 | |
Eugen Hristev | 19ac3ca | 2019-08-08 07:48:31 +0000 | [diff] [blame] | 180 | configure_ddrcfg_input_buffers(true); |
Ben Whitten | 44b7fc8 | 2017-11-23 13:47:48 +0000 | [diff] [blame] | 181 | |
| 182 | /* enable MPDDR clock */ |
| 183 | at91_periph_clk_enable(ATMEL_ID_MPDDRC); |
| 184 | at91_system_clk_enable(AT91_PMC_DDR); |
| 185 | |
| 186 | /* DDRAM2 Controller initialize */ |
| 187 | ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); |
| 188 | } |
| 189 | |
| 190 | void at91_pmc_init(void) |
| 191 | { |
| 192 | u32 tmp; |
| 193 | |
| 194 | tmp = AT91_PMC_PLLAR_29 | |
| 195 | AT91_PMC_PLLXR_PLLCOUNT(0x3f) | |
| 196 | AT91_PMC_PLLXR_MUL(43) | AT91_PMC_PLLXR_DIV(1); |
| 197 | at91_plla_init(tmp); |
| 198 | |
| 199 | at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3)); |
| 200 | |
| 201 | tmp = AT91_PMC_MCKR_MDIV_4 | AT91_PMC_MCKR_CSS_PLLA; |
| 202 | at91_mck_init(tmp); |
| 203 | } |
| 204 | #endif |