blob: 038f60565f7eea4c28c85ca0582bed84b30dd2e0 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +08002/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +08004 */
5
6#include <common.h>
7#include <asm/fsl_law.h>
8#include <asm/mmu.h>
9
10struct law_entry law_table[] = {
11 SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
12#ifdef CONFIG_SYS_BMAN_MEM_PHYS
13 SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
14#endif
15#ifdef CONFIG_SYS_QMAN_MEM_PHYS
16 SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
17#endif
Chunhe Lanc3eb88d2014-09-12 14:47:09 +080018#ifdef CONFIG_SYS_CPLD_BASE_PHYS
19 SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
20#endif
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +080021#ifdef CONFIG_SYS_DCSRBAR_PHYS
22 /* Limit DCSR to 32M to access NPC Trace Buffer */
23 SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
24#endif
25#ifdef CONFIG_SYS_NAND_BASE_PHYS
26 SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
27#endif
28};
29
30int num_law_entries = ARRAY_SIZE(law_table);