blob: 0f116fbf2d981d2cfa4779ba34cfd852c95c6373 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Ley Foon Tan10b69642017-04-26 02:44:46 +08002/*
3 * Copyright (C) 2015-2017 Altera Corporation <www.altera.com>
Ley Foon Tan10b69642017-04-26 02:44:46 +08004 */
5
6#ifndef __CONFIG_SOCFGPA_ARRIA10_H__
7#define __CONFIG_SOCFGPA_ARRIA10_H__
8
9#include <asm/arch/base_addr_a10.h>
Tom Rinid8532af2017-06-02 11:03:50 -040010
Ley Foon Tan10b69642017-04-26 02:44:46 +080011/* Booting Linux */
12#define CONFIG_LOADADDR 0x01000000
13#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
14
15/*
16 * U-Boot general configurations
17 */
Ley Foon Tan10b69642017-04-26 02:44:46 +080018
19/* Memory configurations */
20#define PHYS_SDRAM_1_SIZE 0x40000000
21
22/* Ethernet on SoC (EMAC) */
Ley Foon Tan10b69642017-04-26 02:44:46 +080023
24/*
25 * U-Boot environment configurations
26 */
Ley Foon Tan10b69642017-04-26 02:44:46 +080027
28/*
Ley Foon Tan10b69642017-04-26 02:44:46 +080029 * Serial / UART configurations
30 */
31#define CONFIG_SYS_NS16550_MEM32
32#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
33
34/*
35 * L4 OSC1 Timer 0
36 */
37/* reload value when timer count to zero */
38#define TIMER_LOAD_VAL 0xFFFFFFFF
39
40/*
41 * Flash configurations
42 */
43#define CONFIG_SYS_MAX_FLASH_BANKS 1
44
45/* The rest of the configuration is shared */
46#include <configs/socfpga_common.h>
47
48#endif /* __CONFIG_SOCFGPA_ARRIA10_H__ */