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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Andy Fleming422effd2011-04-08 02:10:54 -05002/*
Claudiu Manoil401b94f2013-09-30 12:44:43 +03003 * Copyright 2009-2010, 2013 Freescale Semiconductor, Inc.
Andy Fleming422effd2011-04-08 02:10:54 -05004 * Jun-jie Zhang <b18070@freescale.com>
5 * Mingkai Hu <Mingkai.hu@freescale.com>
Andy Fleming422effd2011-04-08 02:10:54 -05006 */
Bin Meng79cd33a2016-01-11 22:41:18 -08007
Andy Fleming422effd2011-04-08 02:10:54 -05008#include <common.h>
9#include <miiphy.h>
10#include <phy.h>
11#include <fsl_mdio.h>
12#include <asm/io.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090013#include <linux/errno.h>
Andy Fleming422effd2011-04-08 02:10:54 -050014
Claudiu Manoil401b94f2013-09-30 12:44:43 +030015void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
Andy Fleming422effd2011-04-08 02:10:54 -050016 int dev_addr, int regnum, int value)
17{
18 int timeout = 1000000;
19
20 out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f));
21 out_be32(&phyregs->miimcon, value);
Alison Wang884f1c12014-09-05 13:52:37 +080022 /* Memory barrier */
23 mb();
Andy Fleming422effd2011-04-08 02:10:54 -050024
25 while ((in_be32(&phyregs->miimind) & MIIMIND_BUSY) && timeout--)
26 ;
27}
28
Claudiu Manoil401b94f2013-09-30 12:44:43 +030029int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr,
Andy Fleming422effd2011-04-08 02:10:54 -050030 int dev_addr, int regnum)
31{
32 int value;
33 int timeout = 1000000;
34
Bin Meng79cd33a2016-01-11 22:41:18 -080035 /* Put the address of the phy, and the register number into MIIMADD */
Andy Fleming422effd2011-04-08 02:10:54 -050036 out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f));
37
38 /* Clear the command register, and wait */
39 out_be32(&phyregs->miimcom, 0);
Alison Wang884f1c12014-09-05 13:52:37 +080040 /* Memory barrier */
41 mb();
Andy Fleming422effd2011-04-08 02:10:54 -050042
43 /* Initiate a read command, and wait */
44 out_be32(&phyregs->miimcom, MIIMCOM_READ_CYCLE);
Alison Wang884f1c12014-09-05 13:52:37 +080045 /* Memory barrier */
46 mb();
Andy Fleming422effd2011-04-08 02:10:54 -050047
48 /* Wait for the the indication that the read is done */
49 while ((in_be32(&phyregs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))
50 && timeout--)
51 ;
52
53 /* Grab the value read from the PHY */
54 value = in_be32(&phyregs->miimstat);
55
56 return value;
57}
58
59static int fsl_pq_mdio_reset(struct mii_dev *bus)
60{
Claudiu Manoil401b94f2013-09-30 12:44:43 +030061 struct tsec_mii_mng __iomem *regs =
62 (struct tsec_mii_mng __iomem *)bus->priv;
Andy Fleming422effd2011-04-08 02:10:54 -050063
64 /* Reset MII (due to new addresses) */
65 out_be32(&regs->miimcfg, MIIMCFG_RESET_MGMT);
66
67 out_be32(&regs->miimcfg, MIIMCFG_INIT_VALUE);
68
69 while (in_be32(&regs->miimind) & MIIMIND_BUSY)
70 ;
71
72 return 0;
73}
74
75int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum)
76{
Claudiu Manoil401b94f2013-09-30 12:44:43 +030077 struct tsec_mii_mng __iomem *phyregs =
78 (struct tsec_mii_mng __iomem *)bus->priv;
Andy Fleming422effd2011-04-08 02:10:54 -050079
80 return tsec_local_mdio_read(phyregs, addr, dev_addr, regnum);
81}
82
83int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
84 u16 value)
85{
Claudiu Manoil401b94f2013-09-30 12:44:43 +030086 struct tsec_mii_mng __iomem *phyregs =
87 (struct tsec_mii_mng __iomem *)bus->priv;
Andy Fleming422effd2011-04-08 02:10:54 -050088
89 tsec_local_mdio_write(phyregs, addr, dev_addr, regnum, value);
90
91 return 0;
92}
93
94int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info)
95{
96 struct mii_dev *bus = mdio_alloc();
97
98 if (!bus) {
99 printf("Failed to allocate FSL MDIO bus\n");
100 return -1;
101 }
102
103 bus->read = tsec_phy_read;
104 bus->write = tsec_phy_write;
105 bus->reset = fsl_pq_mdio_reset;
Ben Whitten34fd6c92015-12-30 13:05:58 +0000106 strcpy(bus->name, info->name);
Andy Fleming422effd2011-04-08 02:10:54 -0500107
Claudiu Manoil401b94f2013-09-30 12:44:43 +0300108 bus->priv = (void *)info->regs;
Andy Fleming422effd2011-04-08 02:10:54 -0500109
110 return mdio_register(bus);
111}