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git01.mediatek.com / filogic / uboot / 56596e1a803c431b1829c653cd343a5cb47b4442 / . / board / nvidia / dts / tegra20-harmony.dts
blob: b115f87821dba4172f097988c4345e195b32f270 [file] [log] [blame]
Stephen Warrenc7382852012-05-21 10:04:27 +0000[diff] [blame]1/dts-v1/;
2
Tom Warrenf6236152013-02-21 12:31:27 +0000[diff] [blame]3#include "tegra20.dtsi"
Stephen Warrenc7382852012-05-21 10:04:27 +0000[diff] [blame]4
5/ {
Allen Martin55d98a12012-08-31 08:30:00 +0000[diff] [blame]6 model = "NVIDIA Tegra20 Harmony evaluation board";
Stephen Warrenc7382852012-05-21 10:04:27 +0000[diff] [blame]7 compatible = "nvidia,harmony", "nvidia,tegra20";
8
9 aliases {
10 usb0 = "/usb@c5008000";
Stephen Warrenb03192e2012-10-12 09:45:48 +0000[diff] [blame]11 usb1 = "/usb@c5004000";
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]12 sdhci0 = "/sdhci@c8000600";
13 sdhci1 = "/sdhci@c8000200";
Stephen Warrenc7382852012-05-21 10:04:27 +0000[diff] [blame]14 };
15
16 memory {
17 reg = <0x00000000 0x40000000>;
18 };
19
Stephen Warrenf0083342013-06-18 09:46:51 -0600[diff] [blame]20 host1x {
21 status = "okay";
22 dc@54200000 {
23 status = "okay";
24 rgb {
25 status = "okay";
26 nvidia,panel = <&lcd_panel>;
27 };
28 };
29 };
30
Stephen Warrenc7382852012-05-21 10:04:27 +0000[diff] [blame]31 serial@70006300 {
32 clock-frequency = < 216000000 >;
33 };
34
Allen Martin0398dcb2013-01-16 13:12:24 +0000[diff] [blame]35 nand-controller@70008000 {
36 nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
37 nvidia,width = <8>;
38 nvidia,timing = <26 100 20 80 20 10 12 10 70>;
39 nand@0 {
40 reg = <0>;
41 compatible = "hynix,hy27uf4g2b", "nand-flash";
42 };
43 };
44
Stephen Warrenc7382852012-05-21 10:04:27 +0000[diff] [blame]45 i2c@7000c000 {
46 status = "disabled";
47 };
48
49 i2c@7000c400 {
50 status = "disabled";
51 };
52
53 i2c@7000c500 {
54 status = "disabled";
55 };
56
57 i2c@7000d000 {
58 status = "disabled";
59 };
60
61 usb@c5000000 {
62 status = "disabled";
63 };
64
65 usb@c5004000 {
Stephen Warrenb03192e2012-10-12 09:45:48 +0000[diff] [blame]66 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
Stephen Warrenc7382852012-05-21 10:04:27 +0000[diff] [blame]67 };
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]68
69 sdhci@c8000200 {
70 status = "okay";
71 cd-gpios = <&gpio 69 1>; /* gpio PI5 */
72 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
73 power-gpios = <&gpio 155 0>; /* gpio PT3 */
74 bus-width = <4>;
75 };
76
77 sdhci@c8000600 {
78 status = "okay";
79 cd-gpios = <&gpio 58 1>; /* gpio PH2 */
80 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
81 power-gpios = <&gpio 70 0>; /* gpio PI6 */
82 bus-width = <8>;
83 };
Stephen Warrenf0083342013-06-18 09:46:51 -0600[diff] [blame]84
85 lcd_panel: panel {
86 clock = <42430000>;
87 xres = <1024>;
88 yres = <600>;
89 left-margin = <138>;
90 right-margin = <34>;
91 hsync-len = <136>;
92 lower-margin = <4>;
93 upper-margin = <21>;
94 vsync-len = <4>;
95 hsync-active-high;
96 vsyncx-active-high;
97 nvidia,bits-per-pixel = <16>;
98 nvidia,pwm = <&pwm 0 0>;
99 nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */
100 nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
101 nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
102 nvidia,panel-vdd-gpios = <&gpio 22 0>; /* PC6 */
103 nvidia,panel-timings = <0 0 200 0 0>;
104 };
Stephen Warrenc7382852012-05-21 10:04:27 +0000[diff] [blame]105};