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git01.mediatek.com / filogic / uboot / 5639fc633d3a4965b5ea779cd0ba067e9c2de3ed / . / board / samsung / universal_c210 / lowlevel_init.S
blob: 67635bbfb230567c175eb6aa45efdbe7348b1b71 [file] [log] [blame]
Minkyu Kang0aa1a6b2011-01-24 15:33:50 +0900[diff] [blame]1/*
2 * Lowlevel setup for universal board based on S5PC210
3 *
4 * Copyright (C) 2010 Samsung Electronics
5 * Kyungmin Park <kyungmin.park@samsung.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <config.h>
27#include <version.h>
28#include <asm/arch/cpu.h>
29#include <asm/arch/clock.h>
30
31/*
32 * Register usages:
33 *
34 * r5 has zero always
35 * r7 has GPIO part1 base 0x11400000
36 * r6 has GPIO part2 base 0x11000000
37 */
38
39 .globl lowlevel_init
40lowlevel_init:
41 mov r11, lr
42
43 /* r5 has always zero */
44 mov r5, #0
45
46 ldr r7, =S5PC210_GPIO_PART1_BASE
47 ldr r6, =S5PC210_GPIO_PART2_BASE
48
49 /* System Timer */
50 ldr r0, =S5PC210_SYSTIMER_BASE
51 ldr r1, =0x5000
52 str r1, [r0, #0x0]
53 ldr r1, =0xffffffff
54 str r1, [r0, #0x8]
55 ldr r1, =0x49
56 str r1, [r0, #0x4]
57
58 /* PMIC manual reset */
59 /* nPOWER: XEINT_23: GPX2[7] */
60 add r0, r6, #0xC40 @ S5PC210_GPIO_X2_OFFSET
61 ldr r1, [r0, #0x0]
62 bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
63 orr r1, r1, #(0x1 << 28) @ Output
64 str r1, [r0, #0x0]
65
66 ldr r1, [r0, #0x4]
67 orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
68 str r1, [r0, #0x4]
69
70 /* init system clock */
71 bl system_clock_init
72
73 /* Disable Watchdog */
74 ldr r0, =S5PC210_WATCHDOG_BASE @0x10060000
75 str r5, [r0]
76
77 /* UART */
78 bl uart_asm_init
79
80 /* PMU init */
81 bl system_power_init
82
83 bl tzpc_init
84
85 mov lr, r11
86 mov pc, lr
87 nop
88 nop
89 nop
90
91/*
92 * uart_asm_init: Initialize UART's pins
93 */
94uart_asm_init:
95 /*
96 * setup UART0-UART4 GPIOs (part1)
97 * GPA1CON[3] = I2C_3_SCL (3)
98 * GPA1CON[2] = I2C_3_SDA (3)
99 */
100 mov r0, r7
101 ldr r1, =0x22222222
102 str r1, [r0, #0x00] @ S5PC210_GPIO_A0_OFFSET
103 ldr r1, =0x00223322
104 str r1, [r0, #0x20] @ S5PC210_GPIO_A1_OFFSET
105
106 /* UART_SEL GPY4[7] (part2) at S5PC210 */
107 add r0, r6, #0x1A0 @ S5PC210_GPIO_Y4_OFFSET
108 ldr r1, [r0, #0x0]
109 bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
110 orr r1, r1, #(0x1 << 28)
111 str r1, [r0, #0x0]
112
113 ldr r1, [r0, #0x8]
114 bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit
115 orr r1, r1, #(0x3 << 14) @ Pull-up enabled
116 str r1, [r0, #0x8]
117
118 ldr r1, [r0, #0x4]
119 orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
120 str r1, [r0, #0x4]
121
122 mov pc, lr
123 nop
124 nop
125 nop
126
127system_clock_init:
128 ldr r0, =S5PC210_CLOCK_BASE
129
130 /* APLL(1), MPLL(1), CORE(0), HPM(0) */
131 ldr r1, =0x0101
132 ldr r2, =0x14200 @ CLK_SRC_CPU
133 str r1, [r0, r2]
134
135 /* wait ?us */
136 mov r1, #0x10000
1371: subs r1, r1, #1
138 bne 1b
139
140 /*
141 * CLK_SRC_TOP0
142 * MUX_ONENAND_SEL[28] 0: DOUT133, 1: DOUT166
143 * MUX_VPLL_SEL[8] 0: FINPLL, 1: FOUTVPLL
144 * MUX_EPLL_SEL[4] 0: FINPLL, 1: FOUTEPLL
145 */
146 ldr r1, =0x10000110
147 ldr r2, =0x0C210 @ CLK_SRC_TOP
148 str r1, [r0, r2]
149
150 /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
151 ldr r1, =0x0066666
152 ldr r2, =0x0C240 @ CLK_SRC_FSYS
153 str r1, [r0, r2]
154 /* UART[0:5], PWM: SCLKMPLL(6) */
155 ldr r1, =0x6666666
156 ldr r2, =0x0C250 @ CLK_SRC_PERIL0_OFFSET
157 str r1, [r0, r2]
158
159 /* CPU0: CORE, COREM0, COREM1, PERI, ATB, PCLK_DBG, APLL */
160 ldr r1, =0x0133730
161 ldr r2, =0x14500 @ CLK_DIV_CPU0
162 str r1, [r0, r2]
163 /* CPU1: COPY, HPM */
164 ldr r1, =0x03
165 ldr r2, =0x14504 @ CLK_DIV_CPU1
166 str r1, [r0, r2]
167 /* DMC0: ACP, ACP_PCLK, DPHY, DMC, DMCD, DMCP, COPY2 CORE_TIMER */
168 ldr r1, =0x13111113
169 ldr r2, =0x10500 @ CLK_DIV_DMC0
170 str r1, [r0, r2]
171 /* DMC1: PWI, DVSEM, DPM */
172 ldr r1, =0x01010100
173 ldr r2, =0x10504 @ CLK_DIV_DMC1
174 str r1, [r0, r2]
175 /* LEFTBUS: GDL, GPL */
176 ldr r1, =0x13
177 ldr r2, =0x04500 @ CLK_DIV_LEFTBUS
178 str r1, [r0, r2]
179 /* RIGHHTBUS: GDR, GPR */
180 ldr r1, =0x13
181 ldr r2, =0x08500 @ CLK_DIV_RIGHTBUS
182 str r1, [r0, r2]
183 /*
184 * CLK_DIV_TOP
185 * ONENAND_RATIOD[18:16]: 0 SCLK_ONENAND = MOUTONENAND / (n + 1)
186 * ACLK_200, ACLK_100, ACLK_160, ACLK_133,
187 */
188 ldr r1, =0x00005473
189 ldr r2, =0x0C510 @ CLK_DIV_TOP
190 str r1, [r0, r2]
191 /* MMC[0:1] */
192 ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
193 ldr r2, =0x0C544 @ CLK_DIV_FSYS1
194 str r1, [r0, r2]
195 /* MMC[2:3] */
196 ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
197 ldr r2, =0x0C548 @ CLK_DIV_FSYS2
198 str r1, [r0, r2]
199 /* MMC4 */
200 ldr r1, =0x000f /* 800(MPLL) / (15 + 1) */
201 ldr r2, =0x0C54C @ CLK_DIV_FSYS3
202 str r1, [r0, r2]
203 /* UART[0:5] */
204 ldr r1, =0x774777
205 ldr r2, =0x0C550 @ CLK_DIV_PERIL0
206 str r1, [r0, r2]
207 /* SLIMBUS: ???, PWM */
208 ldr r1, =0x8
209 ldr r2, =0x0C55C @ CLK_DIV_PERIL3
210 str r1, [r0, r2]
211
212 /* PLL Setting */
213 ldr r1, =0x1C20
214 ldr r2, =0x14000 @ APLL_LOCK
215 str r1, [r0, r2]
216 ldr r2, =0x14008 @ MPLL_LOCK
217 str r1, [r0, r2]
218 ldr r2, =0x0C010 @ EPLL_LOCK
219 str r1, [r0, r2]
220 ldr r2, =0x0C020 @ VPLL_LOCK
221 str r1, [r0, r2]
222
223 /* APLL */
224 ldr r1, =0x8000001c
225 ldr r2, =0x14104 @ APLL_CON1
226 str r1, [r0, r2]
227 ldr r1, =0x80c80601 @ 800MHz
228 ldr r2, =0x14100 @ APLL_CON0
229 str r1, [r0, r2]
230 /* MPLL */
231 ldr r1, =0x8000001C
232 ldr r2, =0x1410C @ MPLL_CON1
233 str r1, [r0, r2]
234 ldr r1, =0x80c80601 @ 800MHz
235 ldr r2, =0x14108 @ MPLL_CON0
236 str r1, [r0, r2]
237 /* EPLL */
238 ldr r1, =0x0
239 ldr r2, =0x0C114 @ EPLL_CON1
240 str r1, [r0, r2]
241 ldr r1, =0x80300302 @ 96MHz
242 ldr r2, =0x0C110 @ EPLL_CON0
243 str r1, [r0, r2]
244 /* VPLL */
245 ldr r1, =0x11000400
246 ldr r2, =0x0C124 @ VPLL_CON1
247 str r1, [r0, r2]
248 ldr r1, =0x80350302 @ 108MHz
249 ldr r2, =0x0C120 @ VPLL_CON0
250 str r1, [r0, r2]
251
252 /*
253 * SMMUJPEG[11], JPEG[6], CSIS1[5] : 0111 1001
254 * Turn off all
255 */
256 ldr r1, =0xFFF80000
257 ldr r2, =0x0C920 @ CLK_GATE_IP_CAM
258 str r1, [r0, r2]
259
260 /* Turn off all */
261 ldr r1, =0xFFFFFFC0
262 ldr r2, =0x0C924 @ CLK_GATE_IP_VP
263 str r1, [r0, r2]
264
265 /* Turn off all */
266 ldr r1, =0xFFFFFFE0
267 ldr r2, =0x0C928 @ CLK_GATE_IP_MFC
268 str r1, [r0, r2]
269
270 /* Turn off all */
271 ldr r1, =0xFFFFFFFC
272 ldr r2, =0x0C92C @ CLK_GATE_IP_G3D
273 str r1, [r0, r2]
274
275 /* Turn off all */
276 ldr r1, =0xFFFFFC00
277 ldr r2, =0x0C930 @ CLK_GATE_IP_IMAGE
278 str r1, [r0, r2]
279
280 /* DSIM0[3], MDNIE0[2], MIE0[1] : 0001 */
281 ldr r1, =0xFFFFFFF1
282 ldr r2, =0x0C934 @ CLK_GATE_IP_LCD0
283 str r1, [r0, r2]
284
285 /* Turn off all */
286 ldr r1, =0xFFFFFFC0
287 ldr r2, =0x0C938 @ CLK_GATE_IP_LCD1
288 str r1, [r0, r2]
289
290 /*
291 * SMMUPCIE[18], NFCON[16] : 1111 1010
292 * PCIE[14], SATA[10], SDMMC43[9:8] : 1011 1000
293 * SDMMC1[6], TSI[4], SATAPHY[3], PCIEPHY[2] : 1010 0011
294 */
295 ldr r1, =0xFFFAB8A3
296 ldr r2, =0x0C940 @ CLK_GATE_IP_FSYS
297 str r1, [r0, r2]
298
299 /* Turn off all */
300 ldr r1, =0xFFFFFFFC
301 ldr r2, =0x0C94C @ CLK_GATE_IP_GPS
302 str r1, [r0, r2]
303
304 /*
305 * AC97[27], SPDIF[26], SLIMBUS[25] : 1111 0001
306 * I2C2[8] : 1111 1110
307 */
308 ldr r1, =0xF1FFFEFF
309 ldr r2, =0x0C950 @ CLK_GATE_IP_PERIL
310 str r1, [r0, r2]
311
312 /*
313 * KEYIF[16] : 1111 1110
314 */
315 ldr r1, =0xFFFEFFFF
316 ldr r2, =0x0C960 @ CLK_GATE_IP_PERIR
317 str r1, [r0, r2]
318
319 /* LCD1[5], G3D[3], MFC[2], TV[1] : 1101 0001 */
320 ldr r1, =0xFFFFFFD1
321 ldr r2, =0x0C970 @ CLK_GATE_BLOCK
322 str r1, [r0, r2]
323 mov pc, lr
324 nop
325 nop
326 nop
327
328system_power_init:
329 ldr r0, =S5PC210_POWER_BASE @ 0x10020000
330
331 ldr r2, =0x330C @ PS_HOLD_CONTROL
332 ldr r1, [r0, r2]
333 orr r1, r1, #(0x3 << 8) @ Data High, Output En
334 str r1, [r0, r2]
335
336 /* Power Down */
337 add r2, r0, #0x3000
338 str r5, [r2, #0xC20] @ TV_CONFIGURATION
339 str r5, [r2, #0xC40] @ MFC_CONFIGURATION
340 str r5, [r2, #0xC60] @ G3D_CONFIGURATION
341 str r5, [r2, #0xCA0] @ LCD1_CONFIGURATION
342 str r5, [r2, #0xCE0] @ GPS_CONFIGURATION
343
344 mov pc, lr
345 nop
346 nop
347 nop
348
349tzpc_init:
350 ldr r0, =0x10110000
351 mov r1, #0x0
352 str r1, [r0]
353 mov r1, #0xff
354 str r1, [r0, #0x0804]
355 str r1, [r0, #0x0810]
356 str r1, [r0, #0x081C]
357 str r1, [r0, #0x0828]
358
359 ldr r0, =0x10120000
360 mov r1, #0x0
361 str r1, [r0]
362 mov r1, #0xff
363 str r1, [r0, #0x0804]
364 str r1, [r0, #0x0810]
365 str r1, [r0, #0x081C]
366 str r1, [r0, #0x0828]
367
368 ldr r0, =0x10130000
369 mov r1, #0x0
370 str r1, [r0]
371 mov r1, #0xff
372 str r1, [r0, #0x0804]
373 str r1, [r0, #0x0810]
374 str r1, [r0, #0x081C]
375 str r1, [r0, #0x0828]
376
377 ldr r0, =0x10140000
378 mov r1, #0x0
379 str r1, [r0]
380 mov r1, #0xff
381 str r1, [r0, #0x0804]
382 str r1, [r0, #0x0810]
383 str r1, [r0, #0x081C]
384 str r1, [r0, #0x0828]
385
386 ldr r0, =0x10150000
387 mov r1, #0x0
388 str r1, [r0]
389 mov r1, #0xff
390 str r1, [r0, #0x0804]
391 str r1, [r0, #0x0810]
392 str r1, [r0, #0x081C]
393 str r1, [r0, #0x0828]
394
395 mov pc, lr