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git01.mediatek.com / filogic / uboot / 5639eeb920200bd97baba2535caba125da60f2ca / . / include / configs / socfpga_cyclone5_socdk.h
blob: 18da8496ef851c69e0800b3d7912e54bb79f8239 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Dinh Nguyenad51f7c2012-10-04 06:46:02 +0000[diff] [blame]2/*
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200[diff] [blame]3 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
Dinh Nguyenad51f7c2012-10-04 06:46:02 +0000[diff] [blame]4 */
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200[diff] [blame]5#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__
6#define __CONFIG_SOCFPGA_CYCLONE5_H__
Dinh Nguyenad51f7c2012-10-04 06:46:02 +0000[diff] [blame]7
Dinh Nguyeneca8b5c2015-11-23 17:27:17 -0600[diff] [blame]8#include <asm/arch/base_addr_ac5.h>
Dinh Nguyenad51f7c2012-10-04 06:46:02 +0000[diff] [blame]9
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200[diff] [blame]10/* Memory configurations */
Marek Vasutd4a4db12014-09-08 14:08:45 +0200[diff] [blame]11#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
Dinh Nguyenad51f7c2012-10-04 06:46:02 +0000[diff] [blame]12
Marek Vasutd4a4db12014-09-08 14:08:45 +0200[diff] [blame]13/* Booting Linux */
Marek Vasut2bff5402015-07-22 06:18:19 +0200[diff] [blame]14#define CONFIG_LOADADDR 0x01000000
Marek Vasutd4a4db12014-09-08 14:08:45 +0200[diff] [blame]15#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
Dinh Nguyenad51f7c2012-10-04 06:46:02 +0000[diff] [blame]16
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200[diff] [blame]17/* Ethernet on SoC (EMAC) */
Pavel Machekce340e92014-07-14 14:14:17 +0200[diff] [blame]18
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200[diff] [blame]19/* The rest of the configuration is shared */
20#include <configs/socfpga_common.h>
Chin Liang See561c9d42014-06-10 01:11:04 -0500[diff] [blame]21
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200[diff] [blame]22#endif /* __CONFIG_SOCFPGA_CYCLONE5_H__ */