blob: 6308d9632a8115f83daf765ca860133c2fd340fa [file] [log] [blame]
Stefan Roese84569692018-10-04 13:39:07 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Ralink / Mediatek RT288x/RT3xxx/MT76xx built-in hardware watchdog timer
4 *
5 * Copyright (C) 2018 Stefan Roese <sr@denx.de>
6 *
7 * Based on the Linux driver version which is:
8 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
9 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
10 */
11
Stefan Roese84569692018-10-04 13:39:07 +020012#include <dm.h>
13#include <wdt.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060014#include <asm/global_data.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060015#include <linux/bitops.h>
Stefan Roese84569692018-10-04 13:39:07 +020016#include <linux/io.h>
17
18DECLARE_GLOBAL_DATA_PTR;
19
20struct mt762x_wdt {
21 void __iomem *regs;
22};
23
24#define TIMER_REG_TMRSTAT 0x00
25#define TIMER_REG_TMR1CTL 0x20
26#define TIMER_REG_TMR1LOAD 0x24
27
28#define TMR1CTL_ENABLE BIT(7)
29#define TMR1CTL_RESTART BIT(9)
30#define TMR1CTL_PRESCALE_SHIFT 16
31
32static int mt762x_wdt_ping(struct mt762x_wdt *priv)
33{
34 writel(TMR1CTL_RESTART, priv->regs + TIMER_REG_TMRSTAT);
35
36 return 0;
37}
38
39static int mt762x_wdt_start(struct udevice *dev, u64 ms, ulong flags)
40{
41 struct mt762x_wdt *priv = dev_get_priv(dev);
42
43 /* set the prescaler to 1ms == 1000us */
44 writel(1000 << TMR1CTL_PRESCALE_SHIFT, priv->regs + TIMER_REG_TMR1CTL);
45 writel(ms, priv->regs + TIMER_REG_TMR1LOAD);
46
47 setbits_le32(priv->regs + TIMER_REG_TMR1CTL, TMR1CTL_ENABLE);
48
49 return 0;
50}
51
52static int mt762x_wdt_stop(struct udevice *dev)
53{
54 struct mt762x_wdt *priv = dev_get_priv(dev);
55
56 mt762x_wdt_ping(priv);
57
58 clrbits_le32(priv->regs + TIMER_REG_TMR1CTL, TMR1CTL_ENABLE);
59
60 return 0;
61}
62
63static int mt762x_wdt_reset(struct udevice *dev)
64{
65 struct mt762x_wdt *priv = dev_get_priv(dev);
66
67 mt762x_wdt_ping(priv);
68
69 return 0;
70}
71
72static int mt762x_wdt_probe(struct udevice *dev)
73{
74 struct mt762x_wdt *priv = dev_get_priv(dev);
75
76 priv->regs = dev_remap_addr(dev);
77 if (!priv->regs)
78 return -EINVAL;
79
80 mt762x_wdt_stop(dev);
81
82 return 0;
83}
84
85static const struct wdt_ops mt762x_wdt_ops = {
86 .start = mt762x_wdt_start,
87 .reset = mt762x_wdt_reset,
88 .stop = mt762x_wdt_stop,
89};
90
91static const struct udevice_id mt762x_wdt_ids[] = {
92 { .compatible = "mediatek,mt7621-wdt" },
93 {}
94};
95
96U_BOOT_DRIVER(mt762x_wdt) = {
97 .name = "mt762x_wdt",
98 .id = UCLASS_WDT,
99 .of_match = mt762x_wdt_ids,
100 .probe = mt762x_wdt_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700101 .priv_auto = sizeof(struct mt762x_wdt),
Stefan Roese84569692018-10-04 13:39:07 +0200102 .ops = &mt762x_wdt_ops,
103};