| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Vikas Manocha | 33913c5 | 2014-11-18 10:42:22 -0800 | [diff] [blame] | 2 | /* |
| Patrice Chotard | cc55116 | 2017-10-23 09:53:59 +0200 | [diff] [blame] | 3 | * Copyright (C) 2014, STMicroelectronics - All Rights Reserved |
| 4 | * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. |
| Vikas Manocha | 33913c5 | 2014-11-18 10:42:22 -0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _ASM_ARCH_HARDWARE_H |
| 8 | #define _ASM_ARCH_HARDWARE_H |
| 9 | |
| 10 | /* STV0991 */ |
| 11 | #define SRAM0_BASE_ADDR 0x00000000UL |
| 12 | #define SRAM1_BASE_ADDR 0x00068000UL |
| 13 | #define SRAM2_BASE_ADDR 0x000D0000UL |
| 14 | #define SRAM3_BASE_ADDR 0x00138000UL |
| 15 | #define CFS_SRAM0_BASE_ADDR 0x00198000UL |
| 16 | #define CFS_SRAM1_BASE_ADDR 0x001B8000UL |
| 17 | #define FAST_SRAM_BASE_ADDR 0x001D8000UL |
| 18 | #define FLASH_BASE_ADDR 0x40000000UL |
| 19 | #define PL310_BASE_ADDR 0x70000000UL |
| 20 | #define HSAXIM_BASE_ADDR 0x70100000UL |
| 21 | #define IMGSS_BASE_ADDR 0x70200000UL |
| 22 | #define ADC_BASE_ADDR 0x80000000UL |
| 23 | #define GPIOA_BASE_ADDR 0x80001000UL |
| 24 | #define GPIOB_BASE_ADDR 0x80002000UL |
| 25 | #define GPIOC_BASE_ADDR 0x80003000UL |
| 26 | #define HDM_BASE_ADDR 0x80004000UL |
| 27 | #define THSENS_BASE_ADDR 0x80200000UL |
| 28 | #define GPTIMER2_BASE_ADDR 0x80201000UL |
| 29 | #define GPTIMER1_BASE_ADDR 0x80202000UL |
| 30 | #define QSPI_BASE_ADDR 0x80203000UL |
| 31 | #define CGU_BASE_ADDR 0x80204000UL |
| 32 | #define CREG_BASE_ADDR 0x80205000UL |
| 33 | #define PEC_BASE_ADDR 0x80206000UL |
| 34 | #define WDRU_BASE_ADDR 0x80207000UL |
| 35 | #define BSEC_BASE_ADDR 0x80208000UL |
| 36 | #define DAP_ROM_BASE_ADDR 0x80210000UL |
| 37 | #define SOC_CTI_BASE_ADDR 0x80211000UL |
| 38 | #define TPIU_BASE_ADDR 0x80212000UL |
| 39 | #define TMC_ETF_BASE_ADDR 0x80213000UL |
| 40 | #define R4_ETM_BASE_ADDR 0x80214000UL |
| 41 | #define R4_CTI_BASE_ADDR 0x80215000UL |
| 42 | #define R4_DBG_BASE_ADDR 0x80216000UL |
| 43 | #define GMAC_BASE_ADDR 0x80300000UL |
| 44 | #define RNSS_BASE_ADDR 0x80302000UL |
| 45 | #define CRYP_BASE_ADDR 0x80303000UL |
| 46 | #define HASH_BASE_ADDR 0x80304000UL |
| 47 | #define GPDMA_BASE_ADDR 0x80305000UL |
| 48 | #define ISA_BASE_ADDR 0x8032A000UL |
| 49 | #define HCI_BASE_ADDR 0x80400000UL |
| 50 | #define I2C1_BASE_ADDR 0x80401000UL |
| 51 | #define I2C2_BASE_ADDR 0x80402000UL |
| 52 | #define SAI_BASE_ADDR 0x80403000UL |
| 53 | #define USI_BASE_ADDR 0x80404000UL |
| 54 | #define SPI1_BASE_ADDR 0x80405000UL |
| 55 | #define UART_BASE_ADDR 0x80406000UL |
| 56 | #define SPI2_BASE_ADDR 0x80500000UL |
| 57 | #define CAN_BASE_ADDR 0x80501000UL |
| 58 | #define USART1_BASE_ADDR 0x80502000UL |
| 59 | #define USART2_BASE_ADDR 0x80503000UL |
| 60 | #define USART3_BASE_ADDR 0x80504000UL |
| 61 | #define USART4_BASE_ADDR 0x80505000UL |
| 62 | #define USART5_BASE_ADDR 0x80506000UL |
| 63 | #define USART6_BASE_ADDR 0x80507000UL |
| 64 | #define SDI2_BASE_ADDR 0x80600000UL |
| 65 | #define SDI1_BASE_ADDR 0x80601000UL |
| 66 | #define VICA_BASE_ADDR 0x81000000UL |
| 67 | #define VICB_BASE_ADDR 0x81001000UL |
| 68 | #define STM_CHANNELS_BASE_ADDR 0x81100000UL |
| 69 | #define STM_BASE_ADDR 0x81110000UL |
| 70 | #define SROM_BASE_ADDR 0xFFFF0000UL |
| 71 | |
| 72 | #endif /* _ASM_ARCH_HARDWARE_H */ |